diff options
| author | Dino Li <dino.li@ite.com.tw> | 2014-03-17 15:01:55 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-18 11:24:24 +0000 |
| commit | fa9f407a66e10b4871d02b118952a9b0ac7e3263 (patch) | |
| tree | 53c0a4d4910206a61fe1c128c984bb501205f8fb | |
| parent | 24417669a626fcda285c79aa8fa54268683d695a (diff) | |
| download | chrome-ec-fa9f407a66e10b4871d02b118952a9b0ac7e3263.tar.gz | |
it8380dev: fix firmware can't startup (re-generate)
Some section(entry point, interrupt vector, e-flash signature
and so on) of linker script file are not linked.
The start address of e-flash signature should always at 00000080h.
Default firmware treats VCC logic high to prevent pin 11 logic low
but use following functions.
(EC2I, KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=Firmware can startup on IT8380 emulation board.
Change-Id: I9860ac5b99dcc6e9e00dbc9d1e79a141237b7789
Reviewed-on: https://chromium-review.googlesource.com/190008
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Dino Li <dino.li@ite.com.tw>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
| -rw-r--r-- | chip/it83xx/clock.c | 10 | ||||
| -rw-r--r-- | core/nds32/ec.lds.S | 8 | ||||
| -rw-r--r-- | core/nds32/init.S | 1 |
3 files changed, 15 insertions, 4 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index f2e2a6d37b..437cb3b4b7 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -37,6 +37,16 @@ void clock_init(void) /* Set EC Clock Frequency to PLL frequency. */ IT83XX_ECPM_SCDCR3 &= 0xf0; + /* + * The VCC power status is treated as power-on. + * The VCC supply of LPC and related functions (EC2I, + * KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI). + * It means VCC (pin 11) should be logic high before using + * these functions, or firmware treats VCC logic high + * as following setting. + */ + IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40; + /* Turn off auto clock gating. */ IT83XX_ECPM_AUTOCG = 0x00; } diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 84e08d34bc..f66412cd6d 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -22,7 +22,7 @@ MEMORY SECTIONS { .text : { - OUTDIR/core/CORE/init.o (.text.vecttable) + KEEP(OUTDIR/core/CORE/init.o (.text.vecttable)) . = ALIGN(4); __version_struct_offset = .; KEEP(*(.rodata.ver)) @@ -31,8 +31,8 @@ SECTIONS #else . = ALIGN(4); #endif - OUTDIR/core/CORE/init.o (.text.vectirq) - OUTDIR/core/CORE/init.o (.text) + KEEP(OUTDIR/core/CORE/init.o (.text.vectirq)) + KEEP(OUTDIR/core/CORE/init.o (.text)) *(.text*) #ifdef COMPILE_FOR_RAM } > IRAM @@ -48,7 +48,7 @@ SECTIONS . = ALIGN(4); __irqhandler = .; - OUTDIR/core/CORE/init.o (.rodata.vecthandlers) + KEEP(OUTDIR/core/CORE/init.o (.rodata.vecthandlers)) . = ALIGN(4); __cmds = .; diff --git a/core/nds32/init.S b/core/nds32/init.S index bd166ef668..0f2c0710d6 100644 --- a/core/nds32/init.S +++ b/core/nds32/init.S @@ -73,6 +73,7 @@ vector irq_14 /* HW 14 */ vector irq_15 /* HW 15 */ /* E-flash signature */ +.org 0x80 .balign 16 .global eflash_sig eflash_sig: |