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authorVincent Palatin <vpalatin@chromium.org>2013-11-01 15:08:47 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2013-11-02 01:07:20 +0000
commite18eb27f3a65b57f103c10a24c02bfe933288c61 (patch)
treed5a1462ed011a347c1867e9e7abe09f72d306f33
parent88503ab4ec8f68c19d36ec4b6d3516848d71404a (diff)
downloadchrome-ec-e18eb27f3a65b57f103c10a24c02bfe933288c61.tar.gz
cortex-m: ensure we use the right subset of the instruction set
Cortex-M3 and Cortex-M4 are not using exactly the same instruction set. Cortex-M3 is using ARMv7-M ISA which is a subset of the ARMv7E-M used by the Cortex-M4 core (even though the delta is small). Let's restrict each core to the right subset of instruction by pushing the -mcpu/-march configuration in the chip specific area. Note: GCC 4.8 is now using the full ARMv7E-M instruction set and will emit "undefined instruction" on Cortex-M3 without this patch. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:314194 TEST=build *and* run on Spring and Link. Change-Id: I2f9b87fec689e8d1097809cab437a2bd32dfa194 Reviewed-on: https://chromium-review.googlesource.com/175487 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
-rw-r--r--chip/lm4/build.mk4
-rw-r--r--chip/stm32/build.mk2
-rw-r--r--core/cortex-m/build.mk2
3 files changed, 6 insertions, 2 deletions
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
index f6472aae92..279f15c65d 100644
--- a/chip/lm4/build.mk
+++ b/chip/lm4/build.mk
@@ -6,8 +6,10 @@
# LM4 chip specific files build
#
-# LM4 SoC has a Cortex-M4 ARM core
+# LM4 SoC has a Cortex-M4F ARM core
CORE:=cortex-m
+# Allow the full Cortex-M4 instruction set
+CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
# Required chip modules
chip-y=clock.o gpio.o hwtimer.o jtag.o system.o uart.o
diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 8db57f86bf..957478282c 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -8,6 +8,8 @@
# STM32 SoC family has a Cortex-M3 ARM core
CORE:=cortex-m
+# Force Cortex-M3 subset of instructions
+CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
chip-y=dma.o hwtimer.o system.o uart.o
chip-y+=jtag-$(CHIP_FAMILY).o clock-$(CHIP_FAMILY).o gpio-$(CHIP_FAMILY).o
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index 5f036bc522..c3ae55a521 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -10,7 +10,7 @@
CFLAGS_FPU-$(CONFIG_FPU)=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
# CPU specific compilation flags
-CFLAGS_CPU=-mcpu=cortex-m4 -mthumb -Os -mno-sched-prolog
+CFLAGS_CPU+=-mthumb -Os -mno-sched-prolog
CFLAGS_CPU+=-mno-unaligned-access
CFLAGS_CPU+=$(CFLAGS_FPU-y)