diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-06-05 12:15:45 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-06-05 14:12:13 -0700 |
| commit | 26475135b551a742f2d148d426c4aa18b338f5ca (patch) | |
| tree | 10d6d23555c37d3afcc206d34c9e088d9117ef78 | |
| parent | d5fece8ce541074fe29899fcc14088edbae63283 (diff) | |
| download | chrome-ec-26475135b551a742f2d148d426c4aa18b338f5ca.tar.gz | |
Pit stays on HSI instead of using PLL with the same 16MHz frequency.
Leaving the PLL turned off saves about 0.5 mW (and also presumably
speeds up boot a tiny amount, since we don't need to wait for the PLL
to lock).
BUG=chrome-os-partner:19951
BRANCH=none
TEST=system boots normally. power consumption on P1.8V_MICOM rail is lower.
Change-Id: I93dc1efabbf6c6b0b5a43ffebe1068d18c689bef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57645
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | chip/stm32/clock-stm32l15x.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/chip/stm32/clock-stm32l15x.c b/chip/stm32/clock-stm32l15x.c index 057888f68f..59f53c6400 100644 --- a/chip/stm32/clock-stm32l15x.c +++ b/chip/stm32/clock-stm32l15x.c @@ -28,7 +28,7 @@ void clock_init(void) /* * The initial state : - * SYSCLK from HSI (=16MHz), no divider on AHB, APB1, APB2 + * SYSCLK from MSI (=2MHz), no divider on AHB, APB1, APB2 * PLL unlocked, RTC enabled on LSE */ @@ -41,7 +41,8 @@ void clock_init(void) ; } - /* Set the recommended flash settings for 16MHz clock. + /* + * Set the recommended flash settings for 16MHz clock. * * The 3 bits must be programmed strictly sequentially, * but it is faster not to read-back the value of the ACR register @@ -58,11 +59,13 @@ void clock_init(void) tmp_acr |= (1 << 0); STM32_FLASH_ACR = tmp_acr; +#ifdef CONFIG_USE_PLL /* - * stays on HSI, no prescaler, PLLSRC = HSI, PLLMUL = x3, PLLDIV = /3, - * no MCO => PLLVCO = 48 MHz and PLLCLK = 16 Mhz + * Switch to HSI, no prescaler, PLLSRC = HSI, PLLMUL = x3, PLLDIV = /3, + * no MCO => PLLVCO = 48 MHz and PLLCLK = 16 Mhz. */ STM32_RCC_CFGR = 0x00800001; + /* Enable the PLL */ STM32_RCC_CR |= 1 << 24; /* Wait for the PLL to lock */ @@ -73,4 +76,8 @@ void clock_init(void) /* wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0xc) ; +#else + /* Switch to HSI */ + STM32_RCC_CFGR = 0x00000001; +#endif } |