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| author | Vincent Palatin <vpalatin@chromium.org> | 2013-04-10 09:00:08 -0700 |
|---|---|---|
| committer | ChromeBot <chrome-bot@google.com> | 2013-04-26 09:06:40 -0700 |
| commit | 79c3c04045ab4effb048e6acea6b80ea21769b0c (patch) | |
| tree | b27ef0be06e896306f403080ea5b99e143e29cc4 | |
| parent | 45bc5c1a2135eaae05978d371cff17fb810b9951 (diff) | |
| download | chrome-ec-79c3c04045ab4effb048e6acea6b80ea21769b0c.tar.gz | |
stm32: do not enable interrupts on I2C1
We don't have any interrupt handler for I2C1, so enabling of the I2C1
interrupts will just end up triggering a panic everytime the interrupt
fires.
By the way, I2C1 is used as master and all communications happen without
using the I2C interrupt.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=spring
BUG=chrome-os-partner:18499
TEST=On Spring, run EC flashing in a loop from the AP
while true
do
flashrom --fast-verify -p internal:bus=lpc -w ec.bin
flashrom --fast-verify -p internal:bus=lpc -w ec_autest_image.bin
done
and check that we always succeed and have no panic.
Original-Change-Id: I6b071f309218410840707380d296bdf14b10e9f5
Reviewed-on: https://gerrit.chromium.org/gerrit/47749
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 8b3262d644003b3c9727998dc8d4b0c749450aef)
Change-Id: Ie2fc30e5661e7eade024e6893eaf16427f94cac2
Reviewed-on: https://gerrit.chromium.org/gerrit/49192
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
| -rw-r--r-- | chip/stm32/i2c.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/chip/stm32/i2c.c b/chip/stm32/i2c.c index cbb8db3e1d..2b968b0dd2 100644 --- a/chip/stm32/i2c.c +++ b/chip/stm32/i2c.c @@ -482,8 +482,6 @@ static void i2c_init(void) i2c_init_port(I2C2); /* Enable event and error interrupts */ - task_enable_irq(STM32_IRQ_I2C1_EV); - task_enable_irq(STM32_IRQ_I2C1_ER); task_enable_irq(STM32_IRQ_I2C2_EV); task_enable_irq(STM32_IRQ_I2C2_ER); } |