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authorRandall Spangler <rspangler@chromium.org>2013-04-17 14:08:00 -0700
committerChromeBot <chrome-bot@google.com>2013-04-19 14:11:38 -0700
commitaa18085df2da169160b6dcb4fba355e6741cb93a (patch)
tree7688ac8c07b42025b92367baa08b6066a7dd5381
parent8164026327a8087255b0eb216489c6ec97d3ee2a (diff)
downloadchrome-ec-aa18085df2da169160b6dcb4fba355e6741cb93a.tar.gz
Support power button LED on pitstabilize-4035.0.B
Pit uses GPIO PA2=TIM2_CH3 instead of Snow's PB3=TIM2_CH2. Other than that, the timer setup is identical (STM32F and STM32L are compatible in this respect, anyway). BUG=chrome-os-partner:18657 BRANCH=none TEST=build snow, pit; no pit boards to test on yet Change-Id: I8ba68f99641038e12c9a9c9dd29e3b64410a5eef Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48403 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
-rw-r--r--board/pit/ec.tasklist1
-rw-r--r--chip/stm32/power_led.c43
2 files changed, 33 insertions, 11 deletions
diff --git a/board/pit/ec.tasklist b/board/pit/ec.tasklist
index 7f1f1de257..4cf8e75954 100644
--- a/board/pit/ec.tasklist
+++ b/board/pit/ec.tasklist
@@ -17,6 +17,7 @@
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(VBOOTHASH, vboot_hash_task, NULL, TASK_STACK_SIZE) \
+ TASK_NOTEST(POWERLED, power_led_task, NULL, 256) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
index bad0c23d17..6fbfb720ec 100644
--- a/chip/stm32/power_led.c
+++ b/chip/stm32/power_led.c
@@ -38,14 +38,33 @@ void powerled_set_state(enum powerled_state new_state)
task_wake(TASK_ID_POWERLED);
}
-static void power_led_use_pwm(void)
+static void power_led_set_duty(int percent)
{
- uint32_t val;
+ ASSERT((percent >= 0) && (percent <= 100));
+ power_led_percent = percent;
+ /*
+ * Set the duty cycle. CCRx = percent * ARR / 100. Since we set
+ * ARR=100, this is just percent.
+ */
+#ifdef BOARD_pit
+ STM32_TIM_CCR3(2) = percent;
+#else
+ STM32_TIM_CCR2(2) = percent;
+#endif
+}
+static void power_led_use_pwm(void)
+{
/* Configure power LED GPIO for TIM2/PWM alternate function */
- val = STM32_GPIO_CRL(GPIO_B) & ~0x0000f000;
+#ifdef BOARD_pit
+ /* PA2 = TIM2_CH3 */
+ gpio_set_alternate_function(GPIO_A, (1 << 2), GPIO_ALT_TIM2);
+#else
+ /* PB3 = TIM2_CH2 */
+ uint32_t val = STM32_GPIO_CRL(GPIO_B) & ~0x0000f000;
val |= 0x00009000; /* alt. function (TIM2/PWM) */
STM32_GPIO_CRL(GPIO_B) = val;
+#endif
/* Enable TIM2 clock */
STM32_RCC_APB1ENR |= 0x1;
@@ -63,13 +82,22 @@ static void power_led_use_pwm(void)
*/
STM32_TIM_PSC(2) = CPU_CLOCK / 10000; /* pre-scaler */
STM32_TIM_ARR(2) = 100; /* auto-reload value */
- STM32_TIM_CCR2(2) = 100; /* duty cycle */
+ power_led_set_duty(100);
+
+#ifdef BOARD_PIT
+ /* CC3 configured as output, PWM mode 1, preload enable */
+ STM32_TIM_CCMR2(2) = (6 << 4) | (1 << 3);
+
+ /* CC3 output enable, active low */
+ STM32_TIM_CCER(2) = (1 << 8) | (1 << 9);
+#else
/* CC2 configured as output, PWM mode 1, preload enable */
STM32_TIM_CCMR1(2) = (6 << 12) | (1 << 11);
/* CC2 output enable, active low */
STM32_TIM_CCER(2) = (1 << 4) | (1 << 5);
+#endif
/* Generate update event to force loading of shadow registers */
STM32_TIM_EGR(2) |= 1;
@@ -99,13 +127,6 @@ static void power_led_manual_off(void)
using_pwm = 0;
}
-static void power_led_set_duty(int percent)
-{
- ASSERT((percent >= 0) && (percent <= 100));
- power_led_percent = percent;
- STM32_TIM_CCR2(2) = (STM32_TIM_ARR(2) / 100) * percent;
-}
-
/**
* Return the timeout period (in us) for the current step.
*/