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authorRandall Spangler <rspangler@chromium.org>2012-12-06 14:29:04 -0800
committerGerrit <chrome-bot@google.com>2012-12-06 17:58:31 -0800
commit3d0d2adb63b9ca148216d866c772ea0b6e5e2598 (patch)
treefc0c8ccfe434a61113a868e1961fcd12ee793cbc
parent52440ef89387809af91051671a98ea9c36ce27ca (diff)
downloadchrome-ec-3d0d2adb63b9ca148216d866c772ea0b6e5e2598.tar.gz
link: Enable +5VALW at boot and leave it enabled
This works around a problem where disabling +5VALW glitches +3VALW_EC, which may cause the EC to brown out or hang. BUG=chrome-os-partner:16600 BRANCH=link TEST=manual 1. When the system boots, look for this line as the first x86 power state: [0.004977 x86 power state 0 = G3, in 0x0001] 2. Boot the system. Should boot normally. 3. Shut down the system using the power button. 4. After ~10 seconds, you should see that line of output again. 5. At the EC console: 'gpioget enable_5valw' should output: 1* ENABLE_5VALW This should ideally be combined with a hardware fix to add 30+ ms of delay to EC_EN_5V, since when the EC is reset via power+refresh that tri-states EC_EN_5V, and it takes ~22ms for the EC to boot and start driving EC_EN_5V again. Change-Id: Iba4d961d064105faf988a35c2277e9d7406e39e2 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/39334 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
-rw-r--r--board/link/board.c2
-rw-r--r--common/x86_power.c14
2 files changed, 8 insertions, 8 deletions
diff --git a/board/link/board.c b/board/link/board.c
index dae823e3b6..bb72fdccc1 100644
--- a/board/link/board.c
+++ b/board/link/board.c
@@ -76,7 +76,7 @@ const struct gpio_info gpio_list[GPIO_COUNT] = {
/* Outputs; all unasserted by default except for reset signals */
{"CPU_PROCHOT", LM4_GPIO_F, (1<<2), GPIO_OUT_LOW, NULL},
{"ENABLE_1_5V_DDR", LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
- {"ENABLE_5VALW", LM4_GPIO_K, (1<<4), GPIO_OUT_LOW, NULL},
+ {"ENABLE_5VALW", LM4_GPIO_K, (1<<4), GPIO_OUT_HIGH, NULL},
{"ENABLE_BACKLIGHT", LM4_GPIO_H, (1<<4), GPIO_OUT_LOW, NULL},
{"ENABLE_TOUCHPAD", LM4_GPIO_C, (1<<6), GPIO_OUT_LOW, NULL},
{"ENABLE_VCORE", LM4_GPIO_F, (1<<7), GPIO_OUT_LOW, NULL},
diff --git a/common/x86_power.c b/common/x86_power.c
index 2bbe8e469e..75c2905700 100644
--- a/common/x86_power.c
+++ b/common/x86_power.c
@@ -359,7 +359,6 @@ static void x86_power_init(void)
gpio_set_level(GPIO_ENABLE_1_5V_DDR, 0);
gpio_set_level(GPIO_PCH_RSMRSTn, 0);
gpio_set_level(GPIO_PCH_DPWROK, 0);
- gpio_set_level(GPIO_ENABLE_5VALW, 0);
}
}
@@ -513,8 +512,6 @@ void x86_power_task(void)
break;
case X86_S5S3:
- /* Switch on +5V always-on */
- gpio_set_level(GPIO_ENABLE_5VALW, 1);
/* Wait for the always-on rails to be good */
wait_in_signals(IN_PGOOD_ALWAYS_ON);
@@ -625,14 +622,17 @@ void x86_power_task(void)
/*
* Put touchscreen and lightbar in reset, so we won't
- * leak +3VALW through the reset line.
+ * leak +3VALW through the reset line to chips powered
+ * by +5VALW.
+ *
+ * (Note that we're no longer powering down +5VALW due
+ * to crosbug.com/p/16600, but to minimize side effects
+ * of that change we'll still reset these components in
+ * S5.)
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESETn, 0);
gpio_set_level(GPIO_LIGHTBAR_RESETn, 0);
- /* Switch off +5V always-on */
- gpio_set_level(GPIO_ENABLE_5VALW, 0);
-
state = X86_S5;
break;