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| author | Eric Yilun Lin <yllin@chromium.org> | 2023-02-16 10:25:43 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-22 04:42:22 +0000 |
| commit | 981fbf3f2b537b19e910f84d43e260d2dd963d6e (patch) | |
| tree | d4b04b986e6d4f8149163988f6ba25dc42f27891 | |
| parent | 7855bedf46aa476bdd87c596c2d7f939cf5161bc (diff) | |
| download | chrome-ec-981fbf3f2b537b19e910f84d43e260d2dd963d6e.tar.gz | |
flash_ec: delay cold_reset releasing time
Using cold_reset (which was EC reset, and now changes to GSC reset),
and not enough sleep time would cause a race condition of FW_UP_L
and EC_RST. The booting sequence would be:
1. GSC_RESET on
2. EC_RESET on
2. FW_UP_L on
3. GSC_REST off
4. EC_RESET off
5. FW_UP_L off
The race condition happens at the step 4 and step 5 if the EC reset
released too lade.
This causes an issue entering the EC flashing mode on the new Ti50
platforms. We extend the sleep time between FW_UP_L release and
COLD_RESET release to 0.2, which should be sufficient by the
data we measured.
BUG=b:269182955
TEST=flash over ccd and servo_micro on hayato (cr50,ite),
kingler (ti50, npcx), geralt (ti50, ite)
BRANCH=none
Change-Id: I5a8b5c30bc44779f03ec4ed95cb505e7aaf1a0f0
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4259125
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
Tested-by: Eric Yilun Lin <yllin@google.com>
| -rwxr-xr-x | util/flash_ec | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/util/flash_ec b/util/flash_ec index 0a6044c012..5a81cc4759 100755 --- a/util/flash_ec +++ b/util/flash_ec @@ -988,21 +988,23 @@ function flash_flashrom() { # Set GP_SEL# as low then start ec dut_control fw_up:on - sleep 0.1 + sleep 0.2 dut_control cold_reset:off fi # Enable SPI programming mode. if [[ "${CHIP}" == "ite_spi" || - "${CHIP}" == "ite_spi_ccd_i2c" || - "${CHIP}" == "it8xxx2" ]]; then - # Set hardware strap pin (GPG6) of SPI programming as low then start ec - dut_control fw_up:on - sleep 0.1 - dut_control cold_reset:off - sleep 0.1 - # We have to release the HW strap pin because it also SPI clock pin. - dut_control fw_up:off + "${CHIP}" == "ite_spi_ccd_i2c" || + "${CHIP}" == "it8xxx2" ]]; then + # Set hardware strap pin (GPG6) of SPI + # programming as low then start ec + dut_control fw_up:on + sleep 0.1 + dut_control cold_reset:off + sleep 0.2 + # We have to release the HW strap pin + # because it also SPI clock pin. + dut_control fw_up:off fi servo_save_add "spi1_vref" "off" @@ -1022,7 +1024,7 @@ function flash_flashrom() { # Set GP_SEL# as low then start ec dut_control cold_reset:on dut_control fw_up:on - # sleep 0.1 + sleep 0.2 dut_control cold_reset:off else # Assert EC reset. |