diff options
| author | Jes B. Klinke <jbk@chromium.org> | 2023-02-17 11:29:00 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-17 23:35:03 +0000 |
| commit | ccb519c2908100dfce949dd559c7d9ff3ab5dc9d (patch) | |
| tree | b919ec68557e4a256f52ada98ada3838b97d9139 | |
| parent | 547db3e2f3242f352f6ac49bc5369d67ca82bc57 (diff) | |
| download | chrome-ec-ccb519c2908100dfce949dd559c7d9ff3ab5dc9d.tar.gz | |
chip/stm32: ADC status register "write 1 to clear"
The convention of the STM32_ADC1_ISR register is that writing a 1 to any
bit clears that one latched interrupt status bit. Existing code wrongly
uses |= on this register, effectively clearing every latched bit in the
register, not merely the intended one.
BUG=b:269621551
TEST=Observe ADC conversions on HyperDebug
Change-Id: Ia9fe3f6ca6f2f67614628b23bc7ba2e3a3caf058
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265221
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
| -rw-r--r-- | chip/stm32/adc-stm32l4.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/chip/stm32/adc-stm32l4.c b/chip/stm32/adc-stm32l4.c index acf8444e7c..7d769d8f7c 100644 --- a/chip/stm32/adc-stm32l4.c +++ b/chip/stm32/adc-stm32l4.c @@ -121,6 +121,12 @@ static void adc_configure(int ain_id, int ain_rank, STM32_ADC1_CFGR &= ~STM32_ADC1_CFGR_DMAEN; } +static void stm32_adc1_isr_clear(uint32_t bitmask) +{ + /* Write 1 to clear */ + STM32_ADC1_ISR = bitmask; +} + int adc_read_channel(enum adc_channel ch) { const struct adc_t *adc = adc_channels + ch; @@ -178,7 +184,7 @@ int adc_read_channel(enum adc_channel ch) } /* Enable ADC */ - STM32_ADC1_ISR |= STM32_ADC1_ISR_ADRDY; + stm32_adc1_isr_clear(STM32_ADC1_ISR_ADRDY); STM32_ADC1_CR |= STM32_ADC1_CR_ADEN; wait_loop_index = ((ADC_ENABLE_TIMEOUT_US * (CPU_CLOCK / (100000 * 2))) / @@ -188,6 +194,7 @@ int adc_read_channel(enum adc_channel ch) if (wait_loop_index == 0) break; } + stm32_adc1_isr_clear(STM32_ADC1_ISR_ADRDY); adc1_initialized = 1; } @@ -204,7 +211,7 @@ int adc_read_channel(enum adc_channel ch) } /* Clear JEOS bit */ - STM32_ADC1_ISR |= BIT(6); + stm32_adc1_isr_clear(BIT(6)); /* read converted value */ if (adc->rank == 1) |