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authorMary Ruthven <mruthven@chromium.org>2022-04-26 11:47:36 -0500
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>2022-04-27 17:33:05 +0000
commit822cee0013e48bfc6bab95aba17afb9477f1847e (patch)
tree8801153d2f1f93945bd1b2817910d6013468218a
parent76d059d1441f3d87b38b100a2a477ac0d73b1cc7 (diff)
downloadchrome-ec-822cee0013e48bfc6bab95aba17afb9477f1847e.tar.gz
cr50: add GPIO_SLEEP_DIS flags to EC flashing signals
GPIO_EC_FLASH_SELECT is only used in usb_spi.c and EC_TX_CR50_RX_OUT isn't used anywhere by cr50. These are both debug signals mainly used by servo or ccd for flashing the EC. Disable sleep when they're asserted. Add GPIO_SLEEP_DIS_HIGH to EC_FLASH_SELECT, so sleep is disabled when it's set to 1. Add GPIO_SLEEP_DIS_LOW to EC_TX_CR50_RX_OUT, so sleep is disabled when it's set to 0. BUG=none TEST=gpioset EC_TX_CR50_RX_OUT and gpiset EC_FLASH_SELECT change the gpiocfg sleepmask. Change-Id: Ice4c0d85349eeb547644b134904f95e4a4fe375b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3605882 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
-rw-r--r--board/cr50/gpio.inc12
1 files changed, 8 insertions, 4 deletions
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index d224189042..43e97ccc0e 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -149,12 +149,14 @@ GPIO(EC_TX_CR50_RX, PIN(1, 11), GPIO_INPUT)
/* Pull this low to interrupt the AP */
GPIO(INT_AP_L, PIN(0, 0), GPIO_OUT_HIGH)
-/* Use these to take over the AP & EC flash (only when AP & EC are off!) */
-GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW)
+/*
+ * Use these to take over the AP & EC flash (only when AP & EC are off!)
+ * Disable sleep when they're set to 1.
+ */
+GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW | GPIO_SLEEP_DIS_HIGH)
/*
* If this gpio is changed, you must update the AP_FLASH_SELECT pinmux
* setup in board.c accordingly.
- * Disable sleep when the signal is set high.
*/
GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW | GPIO_SLEEP_DIS_HIGH)
@@ -221,8 +223,10 @@ GPIO(I2CP_SDA, PIN(0, 14), GPIO_INPUT)
* Fake open drain on EC_TX_CR50_RX_OUT. When asserted, the signal can be used
* to enable UART programming mode on the EC. The signal needs to fake open
* drain so it can still be used as the cr50 rx signal when it is deasserted.
+ *
+ * Disable sleep when cr50 sets it to 0.
*/
-GPIO(EC_TX_CR50_RX_OUT, PIN(0, 15), GPIO_ODR_HIGH)
+GPIO(EC_TX_CR50_RX_OUT, PIN(0, 15), GPIO_ODR_HIGH | GPIO_SLEEP_DIS_LOW)
/*
* ENTERING_RW is not a GPIO in H1, but an input pin to RBOX module.