zephyr: ap_pwrseq: move some functions to be common

Move functions that should be common from chipset file to
common file.
De-assert system reset pin is not necessary to power up; so remove
init_chipset_pwr_seq_state().

BUG=none
BRANCH=None
TEST=zmake build nivviks; power up.

Signed-off-by: Li Feng <li1.feng@intel.com>
Change-Id: I364d91503af8cb923342aead03120042cebe9420
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3630830
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>

2 files changed, 38 insertions, 50 deletions

diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
index 869e27aca9..84e528b1df 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c
@@ -8,7 +8,7 @@
 
 LOG_MODULE_DECLARE(ap_pwrseq, CONFIG_AP_PWRSEQ_LOG_LEVEL);
 
-void ap_off(void)
+static void ap_off(void)
 {
 	power_signal_set(PWR_VCCST_PWRGD, 0);
 	power_signal_set(PWR_PCH_PWROK, 0);
@@ -120,48 +120,6 @@ void s0_action_handler(void)
 	generate_sys_pwrok_handler();
 }
 
-void intel_x86_sys_reset_delay(void)
-{
-	/*
-	 * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
-	 * to be safe.
-	 */
-	k_msleep(AP_PWRSEQ_DT_VALUE(sys_reset_delay));
-}
-
-void ap_power_reset(enum ap_power_shutdown_reason reason)
-{
-	/*
-	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
-	 * perform an AP reset. RCIN# which was used earlier to trigger
-	 * a warm reset is known to not work in certain cases where the CPU
-	 * is in a bad state (crbug.com/721853).
-	 *
-	 * The EC cannot control warm vs cold reset of the AP using
-	 * SYS_RESET_L; it's more of a request.
-	 */
-	LOG_DBG("%s: %d", __func__, reason);
-
-	/*
-	 * Toggling SYS_RESET_L will not have any impact when it's already
-	 * low (i,e. AP is in reset state).
-	 */
-	if (power_signal_get(PWR_SYS_RST)) {
-		LOG_DBG("Chipset is in reset state");
-		return;
-	}
-
-	power_signal_set(PWR_SYS_RST, 1);
-	intel_x86_sys_reset_delay();
-	power_signal_set(PWR_SYS_RST, 0);
-	ap_power_ev_send_callbacks(AP_POWER_RESET);
-}
-
-void ap_power_force_shutdown(enum ap_power_shutdown_reason reason)
-{
-	board_ap_power_force_shutdown();
-}
-
 void s3s0_action_handler(void)
 {
 }
@@ -184,12 +142,6 @@ enum power_states_ndsx g3s5_action_handler(void)
 	return SYS_POWER_STATE_S5G3;
 }
 
-void init_chipset_pwr_seq_state(void)
-{
-	/* Deassert reset pin */
-	power_signal_set(PWR_SYS_RST, 0);
-}
-
 /**
  * Determine the current state of the CPU from the
  * power signals.
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
index f13a55c74a..5639e719a9 100644
--- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
+++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_common_pwrseq_sm_handler.c
@@ -115,6 +115,11 @@ static bool chipset_is_exit_hardoff(void)
 	return pwrseq_ctx.want_g3_exit;
 }
 
+void ap_power_force_shutdown(enum ap_power_shutdown_reason reason)
+{
+	board_ap_power_force_shutdown();
+}
+
 static void shutdown_and_notify(enum ap_power_shutdown_reason reason)
 {
 	ap_power_force_shutdown(reason);
@@ -135,6 +140,38 @@ void apshutdown(void)
 	}
 }
 
+void ap_power_reset(enum ap_power_shutdown_reason reason)
+{
+	/*
+	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
+	 * perform an AP reset. RCIN# which was used earlier to trigger
+	 * a warm reset is known to not work in certain cases where the CPU
+	 * is in a bad state (crbug.com/721853).
+	 *
+	 * The EC cannot control warm vs cold reset of the AP using
+	 * SYS_RESET_L; it's more of a request.
+	 */
+	LOG_DBG("%s: %d", __func__, reason);
+
+	/*
+	 * Toggling SYS_RESET_L will not have any impact when it's already
+	 * low (i,e. AP is in reset state).
+	 */
+	if (power_signal_get(PWR_SYS_RST)) {
+		LOG_DBG("Chipset is in reset state");
+		return;
+	}
+
+	power_signal_set(PWR_SYS_RST, 1);
+	/*
+	 * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
+	 * to be safe.
+	 */
+	k_msleep(AP_PWRSEQ_DT_VALUE(sys_reset_delay));
+	power_signal_set(PWR_SYS_RST, 0);
+	ap_power_ev_send_callbacks(AP_POWER_RESET);
+}
+
 /* Check RSMRST is fine to move from S5 to higher state */
 int rsmrst_power_is_good(void)
 {
@@ -507,7 +544,6 @@ void ap_pwrseq_task_start(void)
 
 static void init_pwr_seq_state(void)
 {
-	init_chipset_pwr_seq_state();
 	request_exit_hardoff(false);
 	/*
 	 * The state of the CPU needs to be determined now