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| author | Rajesh Kumar <rajesh3.kumar@intel.com> | 2022-02-09 14:25:42 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-22 20:16:44 +0000 |
| commit | c1b71b7d52b5c466e228d6e6c4a212ab9f452e2d (patch) | |
| tree | ca5347b97c880103ffa9a588aef67e7f18a39ac8 | |
| parent | 59a155a91616c8456def1aac594602dd646bb2f0 (diff) | |
| download | chrome-ec-c1b71b7d52b5c466e228d6e6c4a212ab9f452e2d.tar.gz | |
zephyr: adlrvp: Use Zephyr API to set gpio signal ec_spi_oe_mecc
Use zephyr API gpio_pin_set_dt() to set gpio 'ec_spi_oe_mecc' signal
BUG=b:218684235
BRANCH=none
TEST=zmake -l DEBUG configure -B ~/tmp/adlrvp_npcx/ adlrvp_npcx -b
EC console command 'gpioget ec_spi_oe_mecc'
Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com>
Change-Id: I9221934945bb6aebe7f85dcffc1b015940977c37
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3451262
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
| -rw-r--r-- | zephyr/dts/bindings/gpio/gpio-enum-name.yaml | 1 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts | 3 | ||||
| -rw-r--r-- | zephyr/projects/intelrvp/src/intelrvp.c | 2 |
3 files changed, 2 insertions, 4 deletions
diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml index 1e79a34dc0..361d9956d3 100644 --- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml +++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml @@ -34,7 +34,6 @@ properties: - GPIO_EC_PMIC_EN_ODL - GPIO_EC_PMIC_WATCHDOG_L - GPIO_EC_PROCHOT_IN_L - - GPIO_EC_SPI_OE_MECC - GPIO_ENABLE_BACKLIGHT - GPIO_ENABLE_BACKLIGHT_L - GPIO_ENTERING_RW diff --git a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts index 7a43b43865..d7d4f4ee1b 100644 --- a/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts +++ b/zephyr/projects/intelrvp/adlrvp/adlrvp_npcx/gpio.dts @@ -114,9 +114,8 @@ gpios = <&gpio9 7 GPIO_ODR_HIGH>; enum-name = "GPIO_PCH_PWRBTN_L"; }; - ec_spi_oe_mecc { + ec_spi_oe_mecc: ec_spi_oe_mecc { gpios = <&gpio6 0 GPIO_OUT_LOW>; - enum-name = "GPIO_EC_SPI_OE_MECC"; }; ec_ds3 { gpios = <&gpioc 4 GPIO_OUT_LOW>; diff --git a/zephyr/projects/intelrvp/src/intelrvp.c b/zephyr/projects/intelrvp/src/intelrvp.c index 12288bae5b..26dc425132 100644 --- a/zephyr/projects/intelrvp/src/intelrvp.c +++ b/zephyr/projects/intelrvp/src/intelrvp.c @@ -9,6 +9,6 @@ static void board_init(void) { /* Enable SOC SPI */ - gpio_set_level(GPIO_EC_SPI_OE_MECC, 1); + gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(ec_spi_oe_mecc), 1); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_LAST); |