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| author | Aseda Aboagye <aaboagye@google.com> | 2020-02-03 11:25:29 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-05 08:28:47 +0000 |
| commit | 1e544609affc989a0b4bb75d69659d6a86291ec3 (patch) | |
| tree | 4e523d2e6691563363efc1be77c0cf06791a2531 | |
| parent | fc1e135e21727c73e25c7876fb8ef1ae4f54ce9e (diff) | |
| download | chrome-ec-1e544609affc989a0b4bb75d69659d6a86291ec3.tar.gz | |
power/icelake: JSL: Handle EC_AP_VCCST_PWRGD
For Jasperlake, the EC needs to assert EC_AP_VCCST power good with a 2ms
minimum delay after receiving the DRAM power good and the PP1050_ST
power good.
BUG=b:148688874
BRANCH=None
TEST=`make -j buildall`
Change-Id: Ieedabf5a8a7af3951910118504dc702f7f8058bc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036453
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
| -rw-r--r-- | board/jslrvp_ite/gpio.inc | 1 | ||||
| -rw-r--r-- | power/icelake.c | 24 |
2 files changed, 24 insertions, 1 deletions
diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc index 268b512852..629059df80 100644 --- a/board/jslrvp_ite/gpio.inc +++ b/board/jslrvp_ite/gpio.inc @@ -75,6 +75,7 @@ GPIO(EC_PCH_DSW_PWROK, PIN(L, 6), GPIO_OUT_LOW) */ UNIMPLEMENTED(PCH_SYS_PWROK) UNIMPLEMENTED(EN_VCCIO_EXT) +UNIMPLEMENTED(EC_AP_VCCST_PWRGD_OD) /* Host communication GPIOs */ GPIO(PCH_WAKE_L, PIN(J, 0), GPIO_ODR_HIGH) diff --git a/power/icelake.c b/power/icelake.c index 9fc92f7ff8..2a2d484b85 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -8,6 +8,7 @@ #include "chipset.h" #include "console.h" #include "gpio.h" +#include "hooks.h" #include "intel_x86.h" #include "power.h" #include "power_button.h" @@ -159,11 +160,19 @@ static void enable_pp5000_rail(void) } +#ifdef CONFIG_CHIPSET_JASPERLAKE +static void assert_ec_ap_vccst_pwrgd(void) +{ + GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 1); +} +DECLARE_DEFERRED(assert_ec_ap_vccst_pwrgd); +#endif /* CONFIG_CHIPSET_JASPERLAKE */ + enum power_state power_handle_state(enum power_state state) { int dswpwrok_in = intel_x86_get_pg_ec_dsw_pwrok(); static int dswpwrok_out = -1; - int all_sys_pwrgd_in; + int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd(); int all_sys_pwrgd_out; /* Pass-through DSW_PWROK to ICL. */ @@ -178,6 +187,19 @@ enum power_state power_handle_state(enum power_state state) dswpwrok_out = dswpwrok_in; } +#ifdef CONFIG_CHIPSET_JASPERLAKE + /* + * Assert VCCST power good when ALL_SYS_PWRGD is received with a 2ms + * delay minimum. + */ + if (all_sys_pwrgd_in && !gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { + hook_call_deferred(&assert_ec_ap_vccst_pwrgd_data, 2 * MSEC); + } else if (!all_sys_pwrgd_in && + gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { + GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 0); + } +#endif /* CONFIG_CHIPSET_JASPERLAKE */ + common_intel_x86_handle_rsmrst(state); switch (state) { |