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| author | Jun Lin <CHLin56@nuvoton.com> | 2022-02-15 16:53:42 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-16 02:02:45 +0000 |
| commit | 58c16e8755b77c3692acf626f2f7ac56b09a06de (patch) | |
| tree | d820161de92c1cf8a7f983d0f950d7159882fb98 | |
| parent | 43a3de42c65c469b4f1bf1bca93274943ed4d0c8 (diff) | |
| download | chrome-ec-58c16e8755b77c3692acf626f2f7ac56b09a06de.tar.gz | |
zephyr: npcx: shi: configure power down bit
This CL improves the power consumption by:
* CLear the power down bit for SHI module when SHI is enable.
* Set the power down bit for SHI module when SHI is disabled.
BUG=b:219388463
BRANCH=none
TEST=pass "zmake testall --clobber"
TEST=Check power down bit is set when the system at G3.
TEST=Check power down bit is cleard when the system at S0.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ib9b0f0b744221aef15791383a71bb7303ff39d44
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3461574
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
| -rw-r--r-- | zephyr/drivers/cros_shi/cros_shi_npcx.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c index 118c0c40ea..66ddee1957 100644 --- a/zephyr/drivers/cros_shi/cros_shi_npcx.c +++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c @@ -764,7 +764,16 @@ static void cros_shi_npcx_reset_prepare(struct shi_reg *const inst) static int cros_shi_npcx_enable(const struct device *dev) { const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev); + const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE); struct shi_reg *const inst = HAL_INSTANCE(dev); + int ret; + + ret = clock_control_on(clk_dev, + (clock_control_subsys_t *)&config->clk_cfg); + if (ret < 0) { + DEBUG_CPRINTF("Turn on SHI clock fail %d", ret); + return ret; + } cros_shi_npcx_reset_prepare(inst); npcx_miwu_irq_disable(&config->shi_cs_wui); @@ -782,6 +791,8 @@ static int cros_shi_npcx_enable(const struct device *dev) static int cros_shi_npcx_disable(const struct device *dev) { const struct cros_shi_npcx_config *const config = DRV_CONFIG(dev); + const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE); + int ret; state = SHI_STATE_DISABLED; @@ -791,6 +802,13 @@ static int cros_shi_npcx_disable(const struct device *dev) /* Configure pin-mux from SHI to GPIO. */ npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 0); + ret = clock_control_off(clk_dev, + (clock_control_subsys_t *)&config->clk_cfg); + if (ret < 0) { + DEBUG_CPRINTF("Turn off SHI clock fail %d", ret); + return ret; + } + /* * Allow deep sleep again in case CS dropped before ec was * informed in hook function and turn off SHI's interrupt in time. |