diff options
| author | Devin Lu <Devin.Lu@quantatw.com> | 2021-12-29 15:15:37 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-12-30 02:47:50 +0000 |
| commit | 7d13a7a0fde8c2ff82b98b150b3608895ae226e8 (patch) | |
| tree | 740bc7327c49c73d771b97569a585335d21668fc | |
| parent | fa85e4106944a6f0167c7b8b15e0a219a406e834 (diff) | |
| download | chrome-ec-7d13a7a0fde8c2ff82b98b150b3608895ae226e8.tar.gz | |
redrix: Update gpio table for board version 2
This patch sets some gpio pins to unused/reserved, since hardware
reserved the pins for further features.
BUG=none
BRANCH=none
TEST=make BOARD=redrix
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Change-Id: I1fdd89ba0eae7b9a11d0e30c6f8405209711c825
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3360324
Reviewed-by: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | board/redrix/gpio.inc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/board/redrix/gpio.inc b/board/redrix/gpio.inc index 21f8b51ee1..a658ec5927 100644 --- a/board/redrix/gpio.inc +++ b/board/redrix/gpio.inc @@ -82,6 +82,7 @@ GPIO(USB_C0_TCPC_RST_ODL, PIN(A, 7), GPIO_ODR_LOW) GPIO(USB_C1_TCPC_RST_ODL, PIN(A, 0), GPIO_ODR_LOW) GPIO(VCCST_PWRGD_OD, PIN(A, 4), GPIO_ODR_LOW) GPIO(PEN_RST_L, PIN(0, 2), GPIO_ODR_HIGH) +GPIO(LRA_DIS_ODL, PIN(0, 4), GPIO_ODR_HIGH) /* Reserved for disable haptic pad LRA */ /* LED */ GPIO(C0_CHARGE_LED_AMBER_L, PIN(C, 4), GPIO_OUT_HIGH) /* Amber C0 port */ @@ -116,12 +117,11 @@ ALTERNATE(PIN_MASK(4, 0x34), 0, MODULE_ADC, 0) /* GPIO42/ADC3/RI_L ALTERNATE(PIN_MASK(E, 0x02), 0, MODULE_ADC, 0) /* GPIOE1/ADC7 */ /* KB alternate functions */ -ALTERNATE(PIN_MASK(0, 0xf0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05, KSO13/GPIO04 */ +ALTERNATE(PIN_MASK(0, 0xe0), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO10&P80_CLK/GPIO07, KSO11&P80_DAT/GPIO06, KSO12/GPIO05 */ ALTERNATE(PIN_MASK(1, 0x7f), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO06/GPO13/GP_SEL_L, KSO07/GPO12/JEN_L, KSO03/GPIO16/JTAG_TDO0_SWO, KSO04/GPIO15/XNOR, KSO05/GPIO14, KSO08/GPIO11/CR_SOUT1, KSO09/GPIO10/CR_SIN1 */ ALTERNATE(PIN_MASK(2, 0xfc), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI2/GPIO27/TRACEDATA1, KSI3/GPIO26/TRACEDATA0, KSI4/GPIO25/TRACECLK/GP_SCLK, KSI5/GPIO24/GP_MISO, KSI6/GPIO23/S_SBUB, KSI7/GPIO22/S_SBUA */ ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO00/GPIO21/JTAG_TCK_SWCLK, KSO01/GPIO20/JTAG_TMS_SWIO */ ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KB, GPIO_INPUT | GPIO_PULL_UP) /* KSI0/GPIO31/TRACEDATA3/GP_MOSI, KSI1/GPIO30/TRACEDATA2/GP_CS_L */ -ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO14/GPIO82 */ /* PMU alternate functions */ ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) /* PSL_IN2_L&GPI00/GPIO00 */ @@ -133,6 +133,7 @@ UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */ UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */ UNUSED(PIN(6, 6)) /* GPO66/ARM_L_x86 */ +UNUSED(PIN(8, 2)) /* KSO14/GPIO82 */ /* Pre-configured PSL balls: J8 K6 */ |