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| author | Tom Hughes <tomhughes@chromium.org> | 2021-09-27 23:21:48 +0000 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-03 22:59:55 +0000 |
| commit | 2a0e0dcc0f0356c7bdf711a5e59af14e6629027c (patch) | |
| tree | 6897ec9880fa5b0fd8e939f6ea2aa3fbc0805005 | |
| parent | 1afc2d2704568e5d587eb2ceb18802a4d9bdf7af (diff) | |
| download | chrome-ec-2a0e0dcc0f0356c7bdf711a5e59af14e6629027c.tar.gz | |
core/cortex-m0: Fix atomic.h compilation with clang
clang warns about the following invalid instructions in the inline
assembly:
core/cortex-m0/atomic.h:44:9: error: invalid instruction, any one of the
following would fix this:
<inline asm>:4:1: note: instantiated into assembly here
orr r3, r3, r2
^
<inline asm>:4:1: note: instantiated into assembly here
bic r2, r2, r1
^
ld.lld: error: <inline asm>:1:5: invalid instruction, any one of the
following would fix this:
mov r1, #0
^
ld.lld: error: <inline asm>:4:1: invalid instruction, any one of the
following would fix this:
sub r2, r2, r1
^
The Cortex M0 instruction set only has the variant of these instructions
that set the condition codes (e.g., "bics", "orrs"):
https://developer.arm.com/documentation/ddi0432/c/CHDCICDF.
The "s" at the end indicates that the condition flags will be updated,
but we already indicate that we are clobbering condition codes with "cc"
in the inline asm.
We need to add ".syntax unified" to tell gcc's assembler we're using
unified assembler language
(https://developer.arm.com/documentation/dui0473/c/BABJIHGJ):
/tmp/ccnA5Gkb.s:15936: Error: instruction not supported in Thumb16 mode
-- `orrs r1,r1,r3'
/tmp/ccnA5Gkb.s:15996: Error: instruction not supported in Thumb16 mode
-- `bics r1,r1,r3'
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=burnet
TEST=CC=clang make BOARD=servo_micro
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ifafaf67080e25ab2c5d2aad3efc90a9d61978bf9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3188639
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
| -rw-r--r-- | core/cortex-m0/atomic.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 0c58e71e41..1774d90332 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -22,7 +22,8 @@ typedef atomic_t atomic_val_t; ({ \ uint32_t reg0, reg1; \ \ - __asm__ __volatile__(" cpsid i\n" \ + __asm__ __volatile__(".syntax unified\n" \ + " cpsid i\n" \ " ldr %0, [%2]\n" \ " mov %1, %0\n" \ #asm_op" %0, %0, %3\n" \ @@ -36,12 +37,12 @@ typedef atomic_t atomic_val_t; static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits) { - return ATOMIC_OP(bic, addr, bits); + return ATOMIC_OP(bics, addr, bits); } static inline atomic_val_t atomic_or(atomic_t *addr, atomic_val_t bits) { - return ATOMIC_OP(orr, addr, bits); + return ATOMIC_OP(orrs, addr, bits); } static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value) @@ -51,14 +52,14 @@ static inline atomic_val_t atomic_add(atomic_t *addr, atomic_val_t value) static inline atomic_val_t atomic_sub(atomic_t *addr, atomic_val_t value) { - return ATOMIC_OP(sub, addr, value); + return ATOMIC_OP(subs, addr, value); } static inline atomic_val_t atomic_clear(atomic_t *addr) { atomic_t ret; - __asm__ __volatile__(" mov %2, #0\n" + __asm__ __volatile__(" movs %2, #0\n" " cpsid i\n" " ldr %0, [%1]\n" " str %2, [%1]\n" |