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| author | Dom Rizzo <domrizzo@google.com> | 2016-07-30 14:25:06 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-29 13:31:01 -0700 |
| commit | 9bbce57c0fa48a58f1ac9e5a48d051acc651f72f (patch) | |
| tree | a85adddabea78db4326acc19e20d1cfc35c9307f | |
| parent | 64d7b3a113413034e53f735afdd73e4dbbc27c44 (diff) | |
| download | chrome-ec-9bbce57c0fa48a58f1ac9e5a48d051acc651f72f.tar.gz | |
Added additional macros for the TIMEUS module.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I5a63ae85441d492b7322a98bb05e42d9d236e005
Signed-off-by: Dom Rizzo <domrizzo@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377150
Commit-Ready: Dominic Rizzo <domrizzo@google.com>
Tested-by: Dominic Rizzo <domrizzo@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | chip/g/registers.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/chip/g/registers.h b/chip/g/registers.h index 7a47a9081a..86f7a4ce81 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -252,6 +252,23 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define GR_TIMEHS_MIS(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1MIS_OFFSET) #define GR_TIMEHS_BGLOAD(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1BGLOAD_OFFSET) +/* Microsecond timer registers */ +/* NOTE: module is always 0, timer is 0-3 */ +#define GR_TIMEUS_EN(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_ENABLE_CNTR##t##_OFFSET) +#define GR_TIMEUS_ONESHOT_MODE(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_ONESHOT_MODE_CNTR##t##_OFFSET) +#define GR_TIMEUS_MAXVAL(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_MAXVAL_CNTR##t##_OFFSET) +#define GR_TIMEUS_PROGVAL(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_PROGVAL_CNTR##t##_OFFSET) +#define GR_TIMEUS_DIVIDER(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_DIVIDER_CNTR##t##_OFFSET) +#define GR_TIMEUS_CUR_MAJOR(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_CUR_MAJOR_CNTR##t##_OFFSET) +#define GR_TIMEUS_CUR_MINOR(t) REG32(GC_TIMEUS_BASE_ADDR + \ + GC_TIMEUS_CUR_MINOR_CNTR##t##_OFFSET) + /* Watchdog */ #define GR_WDOG_REG(off) REG32(GC_WATCHDOG0_BASE_ADDR + (off)) #define GR_WATCHDOG_LOAD GR_WDOG_REG(GC_WATCHDOG_WDOGLOAD_OFFSET) |