zephyr: npcx: Move ecst configuration options to upstream

NPCX series ROM code changes the chip basic setting by firmware binary
header for loading the firmware from flash to RAM. All the NPCX series
chips could use it, so those configuration options are moved to
upstream.

The ecst chip version automatic select by CONFIG_SOC_NPCX7MNX.
Currently, the project setting doesn't set to the expected chip part
number. Change the following project to select the target chip &
configure ecst header:
- volteer: npcx7m7fc
- trogdor: npcx7m6fc
- kohaku: npcx7m6fc

BUG=b:184448653
BRANCH=none
TEST=zmake testall
TEST=volteer boot to OS

Cq-Depend: chromium:2872415
Signed-off-by: Yuval Peress <peress@chromium.org>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ieed6c21536401f70950ddd1f18d243b127d896ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867128
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Tested-by: Keith Short <keithshort@chromium.org>

13 files changed, 29 insertions, 183 deletions

diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 954a691a0b..4d7a2430eb 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -77,82 +77,6 @@ if(DEFINED CONFIG_PLATFORM_EC)
   endif()
 endif()
 
-# If a header is needed (should only be set for npcx) run the ecst.py script to
-# generate it.
-if (DEFINED CONFIG_PLATFORM_EC_RO_HEADER)
-    # Translate the CONFIG_FLASH_SIZE to the correct argument value.
-    if ("${CONFIG_FLASH_SIZE}" STREQUAL "512" OR "${CONFIG_FLASH_SIZE}" STREQUAL "1024")
-        set(flash_size 1)
-    elseif ("${CONFIG_FLASH_SIZE}" STREQUAL "2048")
-        set(flash_size 2)
-    elseif ("${CONFIG_FLASH_SIZE}" STREQUAL "4096")
-        set(flash_size 4)
-    elseif ("${CONFIG_FLASH_SIZE}" STREQUAL "8192")
-        set(flash_size 8)
-    elseif ("${CONFIG_FLASH_SIZE}" STREQUAL "16384")
-        set(flash_size 16)
-    endif()
-
-    if (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1)
-        set(spiclkratio 1)
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2)
-        set(spiclkratio 2)
-    else()
-        # Defaults to 1 if none are set.
-        set(spiclkratio 1)
-    endif()
-
-    if (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_20)
-        set(spimaxclk 20)
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_25)
-        set(spimaxclk 25)
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_33)
-        set(spimaxclk 33)
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_40)
-        set(spimaxclk 40)
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50)
-        set(spimaxclk 50)
-    else()
-        # Defaults to 20 if none are set.
-        set(spimaxclk 20)
-    endif()
-
-    if (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_NORMAL)
-        set(spireadmode "normal")
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_FAST)
-        set(spireadmode "fast")
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL)
-        set(spireadmode "dual")
-    elseif (DEFINED CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_QUAD)
-        set(spireadmode "quad")
-    else()
-        # Defaults to "dual" if none are set.
-        set(spireadmode "dual")
-    endif()
-
-    # Check for disabling header CRC.
-    if (NOT DEFINED CONFIG_PLATFORM_EC_RO_HEADER_ENABLE_HEADER_CRC)
-        set(hcrc "-nohcrc")
-    endif()
-
-    # Check for disabling firmware CRC.
-    if (NOT DEFINED CONFIG_PLATFORM_EC_RO_HEADER_ENABLE_FIRMWARE_CRC)
-        set(fcrc "-nofcrc")
-    endif()
-
-    # Note, we cannot get the chip from Kconfig because currently Zephyr doesn't
-    # support all the variations we need for NPCX. These values should be set
-    # in each project's board.cmake.
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-            COMMAND ${PYTHON_EXECUTABLE}
-            ${ZEPHYR_BASE}/boards/arm/npcx7m6fb_evb/support/ecst.py
-            -i ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
-            -o ${PROJECT_BINARY_DIR}/zephyr.packed.bin ${hcrc} ${fcrc}
-            -chip ${ECST_CHIP_ARG} -flashsize ${flash_size}
-            -spiclkratio ${spiclkratio} -spimaxclk ${spimaxclk}
-            -spireadmode ${spireadmode})
-endif()
-
 # Switch from the "zephyr" library to the "app" library for all Chromium OS
 # sources.
 set(ZEPHYR_CURRENT_LIBRARY app)
diff --git a/zephyr/Kconfig.header b/zephyr/Kconfig.header
index db5bd6ba76..3fc8181c9f 100644
--- a/zephyr/Kconfig.header
+++ b/zephyr/Kconfig.header
@@ -17,86 +17,15 @@ config PLATFORM_EC_RO_HEADER
 config PLATFORM_EC_RO_HEADER_OFFSET
 	hex "Offset in memory for the location of the header"
 	default 0x0
+	depends on PLATFORM_EC_RO_HEADER
 	help
 	  The offset (in bytes) of the header relative to the start address of
 	  the RO image.
 
 config PLATFORM_EC_RO_HEADER_SIZE
 	hex "Size of the RO header"
-	default 0x40
+	default 0x40 if SOC_FAMILY_NPCX
+	depends on PLATFORM_EC_RO_HEADER
 	help
 	  The size of the RO header in bytes. This values should come from the
 	  datasheet of the chip being used.
-
-config PLATFORM_EC_RO_HEADER_ENABLE_HEADER_CRC
-	bool "Enable header crc check"
-	help
-	  When enabled, the header will be verified at boot using a crc
-	  checksum.
-
-config PLATFORM_EC_RO_HEADER_ENABLE_FIRMWARE_CRC
-	bool "Enable firmware image crc check"
-	help
-	  When enabled, the firmware image will be verified at boot using a
-	  crc checksum.
-
-choice "core clock to SPI flash clock ratio"
-	prompt "The clock ratio between the core clock and the SPI clock"
-	default PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
-	help
-	  This sets the clock ratio (core clock / SPI clock)
-
-config PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
-	bool "SPI flash will operate with normal reading mode"
-	help
-	  The SPI flash clock has the same frequency as the core clock.
-
-config PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
-	bool "SPI flash will operate with fast reading mode"
-	help
-	  The core clock frequency is twice the flash clock frequency.
-
-endchoice # core clock to SPI flash clock ratio
-
-choice "SPI flash max clock rate"
-	prompt "Clock rate to use for SPI flash"
-	help
-	  This selects the max clock rate (one of 20, 25, 33, 40, or 50 MHz)
-	  that will be used for the SPI flash.
-
-config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_20
-	bool "SPI flash max clock rate of 20 MHz"
-
-config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_25
-	bool "SPI flash max clock rate of 25 MHz"
-
-config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_33
-	bool "SPI flash max clock rate of 33 MHz"
-
-config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_40
-	bool "SPI flash max clock rate of 40 MHz"
-
-config PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50
-	bool "SPI flash max clock rate of 50 MHz"
-
-endchoice # SPI flash max clock rate
-
-choice "SPI flash reading mode"
-	prompt "Reading mode used by the SPI flash"
-	help
-	  This will set the reading mode that can be used by the SPI flash.
-	  Reading modes supported are normal, fast, dual, and quad.
-
-config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_NORMAL
-	bool "SPI flash will operate with normal reading mode"
-
-config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_FAST
-	bool "SPI flash will operate with fast reading mode"
-
-config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL
-	bool "SPI flash will operate with dual reading mode"
-
-config PLATFORM_EC_RO_HEADER_SPI_READ_MODE_QUAD
-	bool "SPI flash will operate with quad reading mode"
-
-endchoice # SPI flash reading mode
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
index e31b4c1b7c..e24fa0ee15 100644
--- a/zephyr/include/cros/nuvoton/npcx.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -7,7 +7,7 @@
 /dts-v1/;
 
 #include <cros/binman.dtsi>
-#include <nuvoton/npcx7m6fb.dtsi>
+#include <nuvoton/npcx7.dtsi>
 
 / {
 
diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board b/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board
index 43cffd68e4..c1a1718847 100644
--- a/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board
+++ b/zephyr/projects/kohaku/boards/arm/kohaku/Kconfig.board
@@ -4,7 +4,7 @@
 
 config BOARD_KOHAKU
 	bool "Google Kohaku EC"
-	depends on SOC_NPCX7M6FB # Actually NPCX7M6FC; C has 512K Flash
+	depends on SOC_NPCX7M6FC
 	# NPCX doesn't actually have enough ram for coverage, but this will
 	# allow generating initial 0 line coverage.
 	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake b/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake
index 3ce47418ca..fd6fcd0656 100644
--- a/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake
+++ b/zephyr/projects/kohaku/boards/arm/kohaku/board.cmake
@@ -2,4 +2,4 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-set(ECST_CHIP_ARG npcx7m6)
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.packed.bin)
diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts
index 2ea08ec246..a2cbbde6c4 100644
--- a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts
+++ b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku.dts
@@ -7,7 +7,7 @@
 
 #include <cros/nuvoton/npcx.dtsi>
 #include <dt-bindings/gpio_defines.h>
-#include <nuvoton/npcx7m6fb.dtsi>
+#include <nuvoton/npcx7m6fc.dtsi>
 
 / {
 	model = "Google Kohaku EC";
@@ -368,11 +368,6 @@
 	};
 };
 
-/* Update flash size to 512KB from 196KB since we are using C variant */
-&flash0 {
-	reg = <0x10090000 0x80000>;
-};
-
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig
index 03ab175ef8..a92531faa1 100644
--- a/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig
+++ b/zephyr/projects/kohaku/boards/arm/kohaku/kohaku_defconfig
@@ -6,13 +6,14 @@
 CONFIG_SOC_SERIES_NPCX7=y
 
 # Platform Configuration
-CONFIG_SOC_NPCX7M6FB=y # Actually NPCX7M6FC; C just has 512K Flash
+CONFIG_SOC_NPCX7M6FC=y
 CONFIG_BOARD_KOHAKU=y
 
-# NPCX BootLoader Table Configuration
-CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
-CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50=y
-CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL=y
+# Enable NPCX firmware header generator
+CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
+CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
+CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
 
 # Serial Drivers
 CONFIG_SERIAL=y
diff --git a/zephyr/projects/trogdor/boards/arm/trogdor/board.cmake b/zephyr/projects/trogdor/boards/arm/trogdor/board.cmake
index 3ce47418ca..fd6fcd0656 100644
--- a/zephyr/projects/trogdor/boards/arm/trogdor/board.cmake
+++ b/zephyr/projects/trogdor/boards/arm/trogdor/board.cmake
@@ -2,4 +2,4 @@
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
-set(ECST_CHIP_ARG npcx7m6)
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.packed.bin)
diff --git a/zephyr/projects/trogdor/boards/arm/trogdor/trogdor_defconfig b/zephyr/projects/trogdor/boards/arm/trogdor/trogdor_defconfig
index b003216344..869f4b7c27 100644
--- a/zephyr/projects/trogdor/boards/arm/trogdor/trogdor_defconfig
+++ b/zephyr/projects/trogdor/boards/arm/trogdor/trogdor_defconfig
@@ -9,6 +9,12 @@ CONFIG_SOC_SERIES_NPCX7=y
 CONFIG_SOC_NPCX7M6FC=y
 CONFIG_BOARD_TROGDOR=y
 
+# Enable NPCX firmware header generator
+CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
+CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
+CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
+
 # Serial Drivers
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/zephyr/projects/volteer/boards/arm/volteer/Kconfig.board b/zephyr/projects/volteer/boards/arm/volteer/Kconfig.board
index d0d540ddb9..5a0390e16f 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/Kconfig.board
+++ b/zephyr/projects/volteer/boards/arm/volteer/Kconfig.board
@@ -7,7 +7,7 @@
 # have a 1:1 mapping.
 config BOARD_VOLTEER
 	bool "Google Volteer Baseboard"
-	depends on SOC_NPCX7M6FC
+	depends on SOC_NPCX7M6FC || SOC_NPCX7M7FC
 	# NPCX doesn't actually have enough ram for coverage, but this will
 	# allow generating initial 0 line coverage.
 	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/projects/volteer/boards/arm/volteer/board.cmake b/zephyr/projects/volteer/boards/arm/volteer/board.cmake
index b7a2cdde59..b58a705122 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/board.cmake
+++ b/zephyr/projects/volteer/boards/arm/volteer/board.cmake
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(ECST_CHIP_ARG npcx7m7)
\ No newline at end of file
+set(NPCX_IMAGE_FILE ${PROJECT_BINARY_DIR}/zephyr.packed.bin)
diff --git a/zephyr/projects/volteer/boards/arm/volteer/volteer.dts b/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
index d17428209b..1356a5e1ba 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
+++ b/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
@@ -10,7 +10,7 @@
 #include <dt-bindings/adc/adc.h>
 #include <dt-bindings/charger/intersil_isl9241.h>
 #include <dt-bindings/gpio_defines.h>
-#include <nuvoton/npcx7m6fb.dtsi>
+#include <nuvoton/npcx7m7fc.dtsi>
 
 / {
 	model = "Google Volteer EC";
@@ -220,16 +220,6 @@
 	};
 
 	/*
-	 * The NPCX loader copies our image from ROM to code RAM, so the flash
-	 * node actually represents the code RAM location and size.
-	 * Override the code RAM for the NPCX797FC.
-	 */
-	/delete-node/ flash@10090000;
-	flash0: flash@10070000 {
-		reg = <0x10070000 0x40000>;
-	};
-
-	/*
 	 * The CBI Second Source Factory Cache (SSFC) layout definition.
 	 * Specific fields values are defined per board.
 	 */
diff --git a/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig b/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
index 0b670885dd..0da58fbf16 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
+++ b/zephyr/projects/volteer/boards/arm/volteer/volteer_defconfig
@@ -4,15 +4,16 @@
 
 # Zephyr Kernel Configuration
 CONFIG_SOC_SERIES_NPCX7=y
-CONFIG_SOC_NPCX7M6FC=y
+CONFIG_SOC_NPCX7M7FC=y
 
 # Platform Configuration
 CONFIG_BOARD_VOLTEER=y
 
-# NPCX BootLoader Table Configuration
-CONFIG_PLATFORM_EC_RO_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
-CONFIG_PLATFORM_EC_RO_HEADER_SPI_MAX_CLOCK_50=y
-CONFIG_PLATFORM_EC_RO_HEADER_SPI_READ_MODE_DUAL=y
+# Enable NPCX firmware header generator
+CONFIG_NPCX_HEADER=y
+CONFIG_NPCX_HEADER_SPI_MAX_CLOCK_50=y
+CONFIG_NPCX_HEADER_SPI_READ_MODE_DUAL=y
+CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2=y
 
 # Serial Drivers
 CONFIG_SERIAL=y