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| author | Poornima Tom <poornima.tom@intel.com> | 2021-03-25 10:12:16 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-20 06:36:59 +0000 |
| commit | d7b6970b5ae24f86f9ab2b1e1b3ded3d3905f3b4 (patch) | |
| tree | b18f9e3e05cd5956cf00731b9d7ec7d348c9d530 | |
| parent | e51ceb7a8006998c5d3e3a6ae8508584a4dcc7db (diff) | |
| download | chrome-ec-d7b6970b5ae24f86f9ab2b1e1b3ded3d3905f3b4.tar.gz | |
mchp: Default espi configuration
In ESPI communication, when no specific configs are defined,
the default configuration must use Maximum frequency,
all channels and all modes.
BUG=b:186669325
BRANCH=none
TEST=make buildall -j
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I61caa65f22d394093bfd1ebd39c9d065d5c1b2d0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784334
Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
| -rw-r--r-- | chip/mchp/espi.c | 49 | ||||
| -rw-r--r-- | chip/mchp/registers.h | 18 |
2 files changed, 38 insertions, 29 deletions
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c index c7bea911bc..c64985252f 100644 --- a/chip/mchp/espi.c +++ b/chip/mchp/espi.c @@ -43,6 +43,24 @@ #define CPRINTS(...) #endif +/* Default config to use maximum frequency */ +#ifndef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ +#if defined(CHIP_FAMILY_MEC172X) +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_66M +#else +#define CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ MCHP_ESPI_CAP1_MAX_FREQ_50M +#endif +#endif + +/* Default config to support all modes */ +#ifndef CONFIG_HOSTCMD_ESPI_EC_MODE +#define CONFIG_HOSTCMD_ESPI_EC_MODE MCHP_ESPI_CAP1_ALL_MODE +#endif + +/* Default config to support all channels */ +#ifndef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP +#define CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP MCHP_ESPI_CAP0_ALL_CHAN_SUPP +#endif /* * eSPI slave to master virtual wire pulse timeout. */ @@ -1357,31 +1375,16 @@ void espi_init(void) */ gpio_config_module(MODULE_LPC, 1); - /* Override Boot-ROM configuration */ -#ifdef CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP + /* Set channel */ MCHP_ESPI_IO_CAP0 = CONFIG_HOSTCMD_ESPI_EC_CHAN_BITMAP; -#endif - -#ifdef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ - MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_MAX_FREQ_MASK); -#if CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 25 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_25M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 33 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_33M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 50 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_50M; -#elif CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ == 66 - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_66M; -#else - MCHP_ESPI_IO_CAP1 |= MCHP_ESPI_CAP1_MAX_FREQ_20M; -#endif -#endif -#ifdef CONFIG_HOSTCMD_ESPI_EC_MODE - MCHP_ESPI_IO_CAP1 &= ~(MCHP_ESPI_CAP1_IO_MASK); - MCHP_ESPI_IO_CAP1 |= ((CONFIG_HOSTCMD_ESPI_EC_MODE) - << MCHP_ESPI_CAP1_IO_BITPOS); -#endif + /* Set eSPI frequency & mode */ + MCHP_ESPI_IO_CAP1 = (MCHP_ESPI_IO_CAP1 & + (~(MCHP_ESPI_CAP1_MAX_FREQ_MASK | + MCHP_ESPI_CAP1_IO_MASK))) | + CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ | + (CONFIG_HOSTCMD_ESPI_EC_MODE + << MCHP_ESPI_CAP1_IO_BITPOS); #ifdef CONFIG_HOSTCMD_ESPI MCHP_ESPI_IO_PLTRST_SRC = MCHP_ESPI_PLTRST_SRC_VW; diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index a3a6da7f09..65936caa2d 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -512,14 +512,20 @@ /* Bits in MCHP_ESPI_IO_CAP1 */ #define MCHP_ESPI_CAP1_RW_MASK 0x37 #define MCHP_ESPI_CAP1_MAX_FREQ_MASK 0x07 -#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0x00 -#define MCHP_ESPI_CAP1_MAX_FREQ_25M 0x01 -#define MCHP_ESPI_CAP1_MAX_FREQ_33M 0x02 -#define MCHP_ESPI_CAP1_MAX_FREQ_50M 0x03 -#define MCHP_ESPI_CAP1_MAX_FREQ_66M 0x04 +#define MCHP_ESPI_CAP1_MAX_FREQ_20M 0 +#define MCHP_ESPI_CAP1_MAX_FREQ_25M 1 +#define MCHP_ESPI_CAP1_MAX_FREQ_33M 2 +#define MCHP_ESPI_CAP1_MAX_FREQ_50M 3 +#define MCHP_ESPI_CAP1_MAX_FREQ_66M 4 +#define MCHP_ESPI_CAP1_SINGLE_MODE 0 +#define MCHP_ESPI_CAP1_SINGLE_DUAL_MODE BIT(0) +#define MCHP_ESPI_CAP1_SINGLE_QUAD_MODE BIT(1) +#define MCHP_ESPI_CAP1_ALL_MODE (MCHP_ESPI_CAP1_SINGLE_MODE | \ + MCHP_ESPI_CAP1_SINGLE_DUAL_MODE | \ + MCHP_ESPI_CAP1_SINGLE_QUAD_MODE) #define MCHP_ESPI_CAP1_IO_BITPOS 4 #define MCHP_ESPI_CAP1_IO_MASK0 0x03 -#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << 4) +#define MCHP_ESPI_CAP1_IO_MASK (0x03ul << MCHP_ESPI_CAP1_IO_BITPOS) #define MCHP_ESPI_CAP1_IO1_VAL 0x00 #define MCHP_ESPI_CAP1_IO12_VAL 0x01 #define MCHP_ESPI_CAP1_IO24_VAL 0x02 |