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| author | Aseda Aboagye <aaboagye@google.com> | 2020-09-30 15:08:44 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-10-01 02:21:46 +0000 |
| commit | 1091354c0eadc65ab86b814e85d26960058d8e3f (patch) | |
| tree | 497d97fb940eafd77937a1ffea17b752b7d0ece2 | |
| parent | 61d13c88ae46439e4c002394cef75bc44d00e339 (diff) | |
| download | chrome-ec-1091354c0eadc65ab86b814e85d26960058d8e3f.tar.gz | |
waddledee/drawcia: Update default resistance
The default combined Rbatt resistance is actually higher than what was
currently specified. The wrong Rds(on) value was used as well as the
sense resistor was missed.
This commit updates the default resistances for these boards.
BUG=none
BRANCH=none
TEST=Build and flash drawlat, verify default resistance is updated.
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: I6b669dfcd1ec11cb2f456b19e83ac4c2783c0b8a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2441803
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | board/drawcia/board.h | 2 | ||||
| -rw-r--r-- | board/waddledee/board.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/board/drawcia/board.h b/board/drawcia/board.h index 8ebb78eafe..fb9a5db542 100644 --- a/board/drawcia/board.h +++ b/board/drawcia/board.h @@ -31,7 +31,7 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 5 /* R_DS(on) 5.3mOhm */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ /* PWM */ #define CONFIG_PWM diff --git a/board/waddledee/board.h b/board/waddledee/board.h index 2ed6e13671..5540fdcbe7 100644 --- a/board/waddledee/board.h +++ b/board/waddledee/board.h @@ -30,7 +30,7 @@ #define CONFIG_CHARGER_OTG #undef CONFIG_CHARGER_SINGLE_CHIP #define CONFIG_OCPC -#define CONFIG_OCPC_DEF_RBATT_MOHMS 5 /* R_DS(on) 5.3mOhm */ +#define CONFIG_OCPC_DEF_RBATT_MOHMS 21 /* R_DS(on) 10.7mOhm + 10mOhm sns rstr */ /* * GPIO for C1 interrupts, for baseboard use |