Introduce BOARD_CFG_LONG_INT_AP_BIT in TPM_BOARD_CFG register

This patch assigns the bit offset 0 in TPM_BOARD_CFG register to
indicate the status of INT_AP_L extension. The bit 1 means INT_AP_L
pulse extension is activated, and 0 means it is not.

BUG=b:148691139
TEST=tested on atlas and on careena.

1. Checked the default TPM_BOARD_CFG (PWRDN_SCRATCH21) value was zero
   and the INT_AP_L assertion duration was 4~10 microseconds.
  > md 0x400000f4 1     // memory dump on GC_PMU_PWRDN_SCRATCH21
  400000F4: 0x00000000

2. Attempted to change the board configuration (with a hacked UART
   command.). The register value was unchanged.
  > brdcfg 0x01
  TPM_BOARD_CFG = 0x00000000

  > md 0x400000f4 1
  400000F4: 0x00000000

3. Forced to write the board configuration with a hacked UART command.
   The register value was changed.
  > brdcfg 0x01 force
  TPM_BOARD_CFG = 0x80000001

  > md 0x400000f4 1
  400000F4: 0x80000001

4. Checked the INT_AP_L assertion duration extended to 110
   microseconds or longer.

5. After cr50 deep sleep, checked the pulse duration was still
   extended.
  - turned AP off.
  - disconnected Suzy-Qable.
  - waited three seconds
  - connected Suzy-Qable, and checked the reset cause was 'hibernate
    rbox'.
  > md 0x400000f4 1
  400000F4: 0x8000001

6. With 100 usec long INT_AP pulse, checked trunks_cliend
regression_test, stress_test and ext_command_test runs good.
Checked dmesg and found no TPM errors through all tests.
  (ap) $ trunks_client --regression_test
  (ap) $ trunks_client --stress_test
  (ap) $ trunks_client --ext_command_test

7.checked no character loss during uart_stress_tester.

  (chroot) $ uart_stress_tester.py -c -t 600 /dev/ttyUSB2 /dev/ttyUSB1

8. the shortest duration of INT_AP_L assertion and deassertion
observed in logic analyzer were 110 usec and 152 usec.

9. measured the depthcharge exit timestamp and cr50 flash time with
or without INT_AP pulse extended to 100 usec, on atlas and helios:
-----------------+-------------------+------------------
                 | atlas             | helios
-----------------+-------------------+------------------
boot (sec)       |  1.398 ->  1.402  |  1.004 ->  1.011
cr50 flash (sec) | 10.800 -> 14.609  | 16.024 -> 16.466
-----------------+-------------------+------------------

Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I2b9f9defb63cf05f9d91b741ccb4b49c4c6bc8e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202839
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>

4 files changed, 18 insertions, 14 deletions

diff --git a/board/cr50/board.c b/board/cr50/board.c
index 3c73181cc5..e20810cd42 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -763,6 +763,15 @@ static void maybe_trigger_ite_sync(void)
 	generate_ite_sync();
 }
 
+static void process_board_cfg(void)
+{
+	uint32_t tpm_board_cfg = board_cfg_reg_read();
+
+	if (tpm_board_cfg & BOARD_CFG_LONG_INT_AP_BIT)
+		int_ap_extension_enable();
+}
+DECLARE_DEFERRED(process_board_cfg);
+
 /* Initialize board. */
 static void board_init(void)
 {
@@ -856,6 +865,8 @@ static void board_init(void)
 	 * machines run in HOOK_SECOND, which first triggers right after
 	 * HOOK_INIT, not at +1.0 seconds.
 	 */
+
+	process_board_cfg();
 }
 DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_INIT_CR50_BOARD);
 
@@ -1803,6 +1814,9 @@ void board_cfg_reg_write(uint32_t value)
 
 	/* Store the tpm_board_cfg in power-down scratch. */
 	GREG32(PMU, PWRDN_SCRATCH21) = value|BOARD_CFG_LOCKED_BIT;
+
+	/* Process board_configuration change in a deferred function */
+	hook_call_deferred(&process_board_cfg_data, 0);
 }
 
 uint32_t board_cfg_reg_read(void)
diff --git a/board/cr50/board.h b/board/cr50/board.h
index 67cd0f7faf..9f6833e5f1 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -409,6 +409,8 @@ int board_in_prod_mode(void);
 
 /* Bit masks for each bit in TPM_BOARD_CFG register */
 enum board_cfg_reg_bitmask {
+	BOARD_CFG_LONG_INT_AP_BIT = BIT(0),
+
 	BOARD_CFG_LOCKED_BIT = BIT(31),
 };
 
diff --git a/chip/g/sps.c b/chip/g/sps.c
index 0387f8640e..5e26459dfc 100644
--- a/chip/g/sps.c
+++ b/chip/g/sps.c
@@ -284,15 +284,8 @@ static void sps_init(void)
 	gpio_set_wakepin(GPIO_STRAP_B1, GPIO_HIB_WAKE_FALLING);
 
 	int_ap_register(sps_int_ap_extension_enable_);
-
-	/*
-	 * TODO: if TPM_BOARD_CFG has INT_AP extension enabled, then call
-	 * int_ap_extension_enable().
-	 */
 }
-DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_DEFAULT);
-
-
+DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_INIT_CR50_BOARD - 1);
 
 /*****************************************************************************/
 /* Interrupt handler stuff */
diff --git a/common/i2cs_tpm.c b/common/i2cs_tpm.c
index edbe7aa967..27ee944c3c 100644
--- a/common/i2cs_tpm.c
+++ b/common/i2cs_tpm.c
@@ -258,13 +258,8 @@ static void i2cs_if_register(void)
 	i2cs_write_error_count = 0;
 
 	int_ap_register(i2cs_int_ap_extension_enable_);
-
-	/*
-	 * TODO: if TPM_BOARD_CFG has INT_AP extension enabled, then call
-	 * int_ap_extension_enable(), and set int_ap_extension_enabled_ true.
-	 */
 }
-DECLARE_HOOK(HOOK_INIT, i2cs_if_register, HOOK_PRIO_LAST);
+DECLARE_HOOK(HOOK_INIT, i2cs_if_register, HOOK_PRIO_INIT_CR50_BOARD - 1);
 
 static int command_i2cs(int argc, char **argv)
 {