chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202

GPIO, WUC and IRQ changes for chip it83201/it83202.

BRANCH=None
BUG=b:133460224
TEST=test GPIO group O, P, Q, R
     1.Input: external input 3.3v, GPDR of corresponding pin is 1.
              (GCR31, GCR32 select 1.8v, validate again for O and
               P group)
     2.Output: GPDR of corresponding pin set 1, measure 3.3v.
     3.INT: GPIO_INT input trigger => WU INT (select high, low,
            rising, falling, both edge trigger mode) => INT => CPU INT
     4.Test power-up and down with this CL on ampton.

Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704
Reviewed-by: Jett Rink <jettrink@chromium.org>

3 files changed, 282 insertions, 39 deletions

diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index 19a244c93a..24947cca59 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -18,12 +18,6 @@
 #include "timer.h"
 #include "util.h"
 
-/*
- * Converts port (ie GPIO A) to base address offset of the control register
- * (GPCRx0) for that port.
- */
-#define CTRL_BASE(port) ((port)*8 + ((port) < GPIO_K ? 8 : 56))
-
 /**
  * Convert wake-up controller (WUC) group to the corresponding wake-up edge
  * sense register (WUESR). Return pointer to the register.
@@ -189,6 +183,7 @@ static const struct {
 	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
 	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
 	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
+	[IT83XX_IRQ_WKO134] =   {GPIO_J, BIT(6),        14, BIT(6)},
 	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
 	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
 	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
@@ -206,9 +201,34 @@ static const struct {
 	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
 	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
 #endif
-	[IT83XX_IRQ_COUNT-1] =  {0,           0,         0,      0},
+#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	[IT83XX_IRQ_GPO0]   =   {GPIO_O, BIT(0),        19, BIT(0)},
+	[IT83XX_IRQ_GPO1]   =   {GPIO_O, BIT(1),        19, BIT(1)},
+	[IT83XX_IRQ_GPO2]   =   {GPIO_O, BIT(2),        19, BIT(2)},
+	[IT83XX_IRQ_GPO3]   =   {GPIO_O, BIT(3),        19, BIT(3)},
+	[IT83XX_IRQ_GPP0]   =   {GPIO_P, BIT(0),        20, BIT(0)},
+	[IT83XX_IRQ_GPP1]   =   {GPIO_P, BIT(1),        20, BIT(1)},
+	[IT83XX_IRQ_GPP2]   =   {GPIO_P, BIT(2),        20, BIT(2)},
+	[IT83XX_IRQ_GPP3]   =   {GPIO_P, BIT(3),        20, BIT(3)},
+	[IT83XX_IRQ_GPP4]   =   {GPIO_P, BIT(4),        20, BIT(4)},
+	[IT83XX_IRQ_GPP5]   =   {GPIO_P, BIT(5),        20, BIT(5)},
+	[IT83XX_IRQ_GPP6]   =   {GPIO_P, BIT(6),        20, BIT(6)},
+	[IT83XX_IRQ_GPQ0]   =   {GPIO_Q, BIT(0),        21, BIT(0)},
+	[IT83XX_IRQ_GPQ1]   =   {GPIO_Q, BIT(1),        21, BIT(1)},
+	[IT83XX_IRQ_GPQ2]   =   {GPIO_Q, BIT(2),        21, BIT(2)},
+	[IT83XX_IRQ_GPQ3]   =   {GPIO_Q, BIT(3),        21, BIT(3)},
+	[IT83XX_IRQ_GPQ4]   =   {GPIO_Q, BIT(4),        21, BIT(4)},
+	[IT83XX_IRQ_GPQ5]   =   {GPIO_Q, BIT(5),        21, BIT(5)},
+	[IT83XX_IRQ_GPR0]   =   {GPIO_R, BIT(0),        22, BIT(0)},
+	[IT83XX_IRQ_GPR1]   =   {GPIO_R, BIT(1),        22, BIT(1)},
+	[IT83XX_IRQ_GPR2]   =   {GPIO_R, BIT(2),        22, BIT(2)},
+	[IT83XX_IRQ_GPR3]   =   {GPIO_R, BIT(3),        22, BIT(3)},
+	[IT83XX_IRQ_GPR4]   =   {GPIO_R, BIT(4),        22, BIT(4)},
+	[IT83XX_IRQ_GPR5]   =   {GPIO_R, BIT(5),        22, BIT(5)},
+#endif
+	[IT83XX_IRQ_COUNT]  =   {     0,      0,         0,      0},
 };
-BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT + 1);
 
 /**
  * Given a GPIO port and mask, find the corresponding WKO interrupt number.
@@ -316,6 +336,19 @@ static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
 		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
 		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
 		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
+#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	[GPIO_O] = { [0] = {&IT83XX_GPIO_GCR31, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GCR31, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GCR31, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GCR31, BIT(3)} },
+	[GPIO_P] = { [0] = {&IT83XX_GPIO_GCR32, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GCR32, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GCR32, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GCR32, BIT(3)},
+		     [4] = {&IT83XX_GPIO_GCR32, BIT(4)},
+		     [5] = {&IT83XX_GPIO_GCR32, BIT(5)},
+		     [6] = {&IT83XX_GPIO_GCR32, BIT(6)} },
+#endif
 #else
 	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
 		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
@@ -376,11 +409,14 @@ static inline void it83xx_set_alt_func(uint32_t port, uint32_t pin,
 	 * Otherwise, turn the pin into an input as it's default.
 	 */
 	if (func != GPIO_ALT_FUNC_NONE)
-		IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) &= ~0xc0;
+		IT83XX_GPIO_CTRL(port, pin) &= ~(GPCR_PORT_PIN_MODE_OUTPUT |
+			GPCR_PORT_PIN_MODE_INPUT);
 	else
-		IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) =
-			(IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) | 0x80) & ~0x40;
+		IT83XX_GPIO_CTRL(port, pin) =
+			(IT83XX_GPIO_CTRL(port, pin) | GPCR_PORT_PIN_MODE_INPUT)
+			& ~GPCR_PORT_PIN_MODE_OUTPUT;
 }
+
 void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 				enum gpio_alternate_func func)
 {
@@ -390,7 +426,6 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask,
 	while (mask > 0) {
 		if (mask & 1)
 			it83xx_set_alt_func(port, pin, func);
-
 		pin++;
 		mask >>= 1;
 	}
@@ -458,7 +493,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 	uint32_t pin = 0;
 	uint32_t mask_copy = mask;
 
-	if (port > GPIO_KBS_OFF) {
+	if (port > GPIO_PORT_COUNT) {
 		/* set up GPIO of KSO/KSI pins (support input only). */
 		gpio_kbs_pin_gpio_mode(port, mask, flags);
 		return;
@@ -486,26 +521,32 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 		if (mask_copy & 1) {
 			/* Set input or output. */
 			if (flags & GPIO_OUTPUT)
-				IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) =
-				(IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) | 0x40)
-				& ~0x80;
+				IT83XX_GPIO_CTRL(port, pin) =
+				(IT83XX_GPIO_CTRL(port, pin) |
+				 GPCR_PORT_PIN_MODE_OUTPUT) &
+				~GPCR_PORT_PIN_MODE_INPUT;
 			else
-				IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) =
-				(IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) | 0x80)
-				& ~0x40;
+				IT83XX_GPIO_CTRL(port, pin) =
+				(IT83XX_GPIO_CTRL(port, pin) |
+				 GPCR_PORT_PIN_MODE_INPUT) &
+				~GPCR_PORT_PIN_MODE_OUTPUT;
 
 			/* Handle pullup / pulldown */
 			if (flags & GPIO_PULL_UP) {
-				IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) =
-				(IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) | 0x04)
-				& ~0x02;
+				IT83XX_GPIO_CTRL(port, pin) =
+				(IT83XX_GPIO_CTRL(port, pin) |
+				 GPCR_PORT_PIN_MODE_PULLUP) &
+				~GPCR_PORT_PIN_MODE_PULLDOWN;
 			} else if (flags & GPIO_PULL_DOWN) {
-				IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) =
-				(IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) | 0x02)
-				& ~0x04;
+				IT83XX_GPIO_CTRL(port, pin) =
+				(IT83XX_GPIO_CTRL(port, pin) |
+				 GPCR_PORT_PIN_MODE_PULLDOWN) &
+				~GPCR_PORT_PIN_MODE_PULLUP;
 			} else {
 				/* No pull up/down */
-				IT83XX_GPIO_CTRL(CTRL_BASE(port), pin) &= ~0x06;
+				IT83XX_GPIO_CTRL(port, pin) &=
+					~(GPCR_PORT_PIN_MODE_PULLUP |
+					  GPCR_PORT_PIN_MODE_PULLDOWN);
 			}
 
 			/* To select 1.8v or 3.3v support. */
@@ -631,6 +672,20 @@ void gpio_pre_init(void)
 	IT83XX_USB_P0MCR &= ~USB_DP_DM_PULL_DOWN_EN;
 #endif
 
+#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	/* Q group pins are default GPI mode, clear alternate setting. */
+	IT83XX_VBATPC_XLPIER = 0x0;
+	/*
+	 * R group pins are default alternate output low, we clear alternate
+	 * setting (sink power switch from VBAT to VSTBY) to become GPO output
+	 * low.
+	 * NOTE: GPR0~5 pins are output low by default. It should consider
+	 *       that if output low signal effect external circuit or not,
+	 *       until we reconfig these pins in gpio.inc.
+	 */
+	IT83XX_VBATPC_BGPOPSCR = 0x0;
+#endif
+
 	for (i = 0; i < GPIO_COUNT; i++, g++) {
 		flags = g->flags;
 
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
index 7b3e48946b..498b7446f0 100644
--- a/chip/it83xx/irq.c
+++ b/chip/it83xx/irq.c
@@ -19,7 +19,7 @@ static const struct {
 	uint8_t isr_off;
 	uint8_t ier_off;
 	uint8_t cpu_int[8];
-} irq_groups[23] = {
+} irq_groups[] = {
 	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
 	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
 	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
@@ -27,7 +27,7 @@ static const struct {
 	IRQ_GROUP(4,  {11, 11, 11, 11,  8,  9,  9,  9}),
 	IRQ_GROUP(5,  { 2,  2,  2,  2,  2,  2,  2,  2}),
 	IRQ_GROUP(6,  { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(7,  {10, 10,  3, -1,  3,  3,  3,  3}),
+	IRQ_GROUP(7,  {10, 10,  3, 12,  3,  3,  3,  3}),
 	IRQ_GROUP(8,  { 4,  4,  4,  4,  4,  4, -1, 12}),
 	IRQ_GROUP(9,  { 2,  2,  2,  2,  2,  2,  2,  2}),
 	IRQ_GROUP(10, { 3,  6, 12, 12,  5,  2,  2,  2}),
@@ -41,13 +41,22 @@ static const struct {
 	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
 	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
 	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
-#ifdef IT83XX_INTC_GROUP_21_22_SUPPORT
+#if defined(IT83XX_INTC_GROUP_21_22_SUPPORT)
 	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
 	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
+#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	IRQ_GROUP(21, {-1, -1, 12, 12, 12, 12, 12, 12}),
+	IRQ_GROUP(22, { 2,  2,  2,  2,  2,  2,  2,  2}),
 #else
 	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
 	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
 #endif
+	IRQ_GROUP(23, { 2,  2, -1, -1, -1, -1, -1,  2}),
+	IRQ_GROUP(24, { 2,  2,  2,  2,  2,  2, -1,  2}),
+	IRQ_GROUP(25, { 2,  2,  2,  2, -1, -1, -1, -1}),
+	IRQ_GROUP(26, { 2,  2,  2,  2,  2,  2,  2, -1}),
+	IRQ_GROUP(27, { 2,  2,  2,  2,  2,  2, -1, -1}),
+	IRQ_GROUP(28, { 2,  2,  2,  2,  2,  2, -1, -1}),
 };
 
 int chip_get_intc_group(int irq)
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index fbe0c1d295..65460009b7 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -9,6 +9,7 @@
 #define __CROS_EC_REGISTERS_H
 
 #include "common.h"
+#include "compile_time_macros.h"
 
 #define __ram_code __attribute__((section(".ram_code")))
 
@@ -79,6 +80,7 @@
 #define IT83XX_IRQ_RTCT_ALARM1    56
 #define IT83XX_IRQ_RTCT_ALARM2    57
 #define IT83XX_IRQ_EXT_TIMER2     58
+#define IT83XX_IRQ_DEFERRED_SPI   59
 #define IT83XX_IRQ_TMR_A0         60
 #define IT83XX_IRQ_TMR_A1         61
 #define IT83XX_IRQ_TMR_B0         62
@@ -197,6 +199,7 @@
 #define IT83XX_IRQ_USBPD0         165
 #define IT83XX_IRQ_USBPD1         166
 /* Group 21 */
+#if defined(CHIP_FAMILY_IT8320)
 #define IT83XX_IRQ_WKO40          168
 #define IT83XX_IRQ_WKO45          169
 #define IT83XX_IRQ_WKO46          170
@@ -210,6 +213,65 @@
 #define IT83XX_IRQ_WKO150         177
 
 #define IT83XX_IRQ_COUNT          178
+#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+/* Group 21 */
+#define IT83XX_IRQ_AUDIO_IF       170
+#define IT83XX_IRQ_SPI_SLAVE      171
+#define IT83XX_IRQ_DSP_ENGINE     172
+#define IT83XX_IRQ_NN_ENGINE      173
+#define IT83XX_IRQ_USBPD2         174
+#define IT83XX_IRQ_CRYPTO         175
+/* Group 22 */
+#define IT83XX_IRQ_WKO40          176
+#define IT83XX_IRQ_WKO45          177
+#define IT83XX_IRQ_WKO46          178
+#define IT83XX_IRQ_WKO144         179
+#define IT83XX_IRQ_WKO145         180
+#define IT83XX_IRQ_WKO146         181
+#define IT83XX_IRQ_WKO147         182
+#define IT83XX_IRQ_WKO148         183
+/* Group 23 */
+#define IT83XX_IRQ_WKO149         184
+#define IT83XX_IRQ_WKO150         185
+#define IT83XX_IRQ_SSPI1          191
+/* Group 24 */
+#define IT83XX_IRQ_XLPIN0         192
+#define IT83XX_IRQ_XLPIN1         193
+#define IT83XX_IRQ_XLPIN2         194
+#define IT83XX_IRQ_XLPIN3         195
+#define IT83XX_IRQ_XLPIN4         196
+#define IT83XX_IRQ_XLPIN5         197
+#define IT83XX_IRQ_WEEK_ALARM     199
+/* Group 25 */
+#define IT83XX_IRQ_GPO0           200
+#define IT83XX_IRQ_GPO1           201
+#define IT83XX_IRQ_GPO2           202
+#define IT83XX_IRQ_GPO3           203
+/* Group 26 */
+#define IT83XX_IRQ_GPP0           208
+#define IT83XX_IRQ_GPP1           209
+#define IT83XX_IRQ_GPP2           210
+#define IT83XX_IRQ_GPP3           211
+#define IT83XX_IRQ_GPP4           212
+#define IT83XX_IRQ_GPP5           213
+#define IT83XX_IRQ_GPP6           214
+/* Group 27 */
+#define IT83XX_IRQ_GPQ0           216
+#define IT83XX_IRQ_GPQ1           217
+#define IT83XX_IRQ_GPQ2           218
+#define IT83XX_IRQ_GPQ3           219
+#define IT83XX_IRQ_GPQ4           220
+#define IT83XX_IRQ_GPQ5           221
+/* Group 28 */
+#define IT83XX_IRQ_GPR0           224
+#define IT83XX_IRQ_GPR1           225
+#define IT83XX_IRQ_GPR2           226
+#define IT83XX_IRQ_GPR3           227
+#define IT83XX_IRQ_GPR4           228
+#define IT83XX_IRQ_GPR5           229
+
+#define IT83XX_IRQ_COUNT          230
+#endif /* !defined(CHIP_FAMILY_IT8320) */
 
 /* IRQ dispatching to CPU INT vectors */
 #define IT83XX_CPU_INT_IRQ_1       2
@@ -270,6 +332,7 @@
 #define IT83XX_CPU_INT_IRQ_56     10
 #define IT83XX_CPU_INT_IRQ_57     10
 #define IT83XX_CPU_INT_IRQ_58      3
+#define IT83XX_CPU_INT_IRQ_59     12
 #define IT83XX_CPU_INT_IRQ_60      3
 #define IT83XX_CPU_INT_IRQ_61      3
 #define IT83XX_CPU_INT_IRQ_62      3
@@ -377,14 +440,62 @@
 #define IT83XX_CPU_INT_IRQ_167    12
 #define IT83XX_CPU_INT_IRQ_168     2
 #define IT83XX_CPU_INT_IRQ_169     2
+#if defined(CHIP_FAMILY_IT8320)
 #define IT83XX_CPU_INT_IRQ_170     2
 #define IT83XX_CPU_INT_IRQ_171     2
 #define IT83XX_CPU_INT_IRQ_172     2
 #define IT83XX_CPU_INT_IRQ_173     2
 #define IT83XX_CPU_INT_IRQ_174     2
 #define IT83XX_CPU_INT_IRQ_175     2
+#elif defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+#define IT83XX_CPU_INT_IRQ_170    12
+#define IT83XX_CPU_INT_IRQ_171    12
+#define IT83XX_CPU_INT_IRQ_172    12
+#define IT83XX_CPU_INT_IRQ_173    12
+#define IT83XX_CPU_INT_IRQ_174    12
+#define IT83XX_CPU_INT_IRQ_175    12
+#endif
 #define IT83XX_CPU_INT_IRQ_176     2
 #define IT83XX_CPU_INT_IRQ_177     2
+#define IT83XX_CPU_INT_IRQ_178     2
+#define IT83XX_CPU_INT_IRQ_179     2
+#define IT83XX_CPU_INT_IRQ_180     2
+#define IT83XX_CPU_INT_IRQ_181     2
+#define IT83XX_CPU_INT_IRQ_182     2
+#define IT83XX_CPU_INT_IRQ_183     2
+#define IT83XX_CPU_INT_IRQ_184     2
+#define IT83XX_CPU_INT_IRQ_185     2
+#define IT83XX_CPU_INT_IRQ_191     2
+#define IT83XX_CPU_INT_IRQ_192     2
+#define IT83XX_CPU_INT_IRQ_193     2
+#define IT83XX_CPU_INT_IRQ_194     2
+#define IT83XX_CPU_INT_IRQ_195     2
+#define IT83XX_CPU_INT_IRQ_196     2
+#define IT83XX_CPU_INT_IRQ_197     2
+#define IT83XX_CPU_INT_IRQ_199     2
+#define IT83XX_CPU_INT_IRQ_200     2
+#define IT83XX_CPU_INT_IRQ_201     2
+#define IT83XX_CPU_INT_IRQ_202     2
+#define IT83XX_CPU_INT_IRQ_203     2
+#define IT83XX_CPU_INT_IRQ_208     2
+#define IT83XX_CPU_INT_IRQ_209     2
+#define IT83XX_CPU_INT_IRQ_210     2
+#define IT83XX_CPU_INT_IRQ_211     2
+#define IT83XX_CPU_INT_IRQ_212     2
+#define IT83XX_CPU_INT_IRQ_213     2
+#define IT83XX_CPU_INT_IRQ_214     2
+#define IT83XX_CPU_INT_IRQ_216     2
+#define IT83XX_CPU_INT_IRQ_217     2
+#define IT83XX_CPU_INT_IRQ_218     2
+#define IT83XX_CPU_INT_IRQ_219     2
+#define IT83XX_CPU_INT_IRQ_220     2
+#define IT83XX_CPU_INT_IRQ_221     2
+#define IT83XX_CPU_INT_IRQ_224     2
+#define IT83XX_CPU_INT_IRQ_225     2
+#define IT83XX_CPU_INT_IRQ_226     2
+#define IT83XX_CPU_INT_IRQ_227     2
+#define IT83XX_CPU_INT_IRQ_228     2
+#define IT83XX_CPU_INT_IRQ_229     2
 
 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
 #define CPU_INT_2_ALL_GPIOS      255
@@ -443,6 +554,12 @@
 #define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
 #define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
 #define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
+#define IT83XX_INTC_IER23   REG8(IT83XX_INTC_BASE+0x91)
+#define IT83XX_INTC_IER24   REG8(IT83XX_INTC_BASE+0x95)
+#define IT83XX_INTC_IER25   REG8(IT83XX_INTC_BASE+0x99)
+#define IT83XX_INTC_IER26   REG8(IT83XX_INTC_BASE+0x9d)
+#define IT83XX_INTC_IER27   REG8(IT83XX_INTC_BASE+0xa1)
+#define IT83XX_INTC_IER28   REG8(IT83XX_INTC_BASE+0xa5)
 
 #define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
 #define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
@@ -467,6 +584,12 @@
 #define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
 #define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
 #define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
+#define IT83XX_INTC_ISR23   REG8(IT83XX_INTC_BASE+0x90)
+#define IT83XX_INTC_ISR24   REG8(IT83XX_INTC_BASE+0x94)
+#define IT83XX_INTC_ISR25   REG8(IT83XX_INTC_BASE+0x98)
+#define IT83XX_INTC_ISR26   REG8(IT83XX_INTC_BASE+0x9c)
+#define IT83XX_INTC_ISR27   REG8(IT83XX_INTC_BASE+0xa0)
+#define IT83XX_INTC_ISR28   REG8(IT83XX_INTC_BASE+0xa4)
 
 #define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
 #define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
@@ -536,6 +659,7 @@
 /* --- GPIO --- */
 
 #define IT83XX_GPIO_BASE  0x00F01600
+#define IT83XX_GPIO2_BASE 0x00F03E00
 
 #define IT83XX_GPIO_GCR         REG8(IT83XX_GPIO_BASE+0x00)
 #define IT83XX_GPIO_GCR_LPC_RST_B7      0x1
@@ -645,11 +769,15 @@
 #define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
 #define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
 #define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
+#define IT83XX_GPIO_GCR30       REG8(IT83XX_GPIO_BASE+0xED)
+#define IT83XX_GPIO_GCR31       REG8(IT83XX_GPIO_BASE+0xD5)
+#define IT83XX_GPIO_GCR32       REG8(IT83XX_GPIO_BASE+0xD6)
 
-#define IT83XX_GPIO_DATA_BASE        (IT83XX_GPIO_BASE + 0x00)
-#define IT83XX_GPIO_OUTPUT_TYPE_BASE (IT83XX_GPIO_BASE + 0x70)
+#define IT83XX_VBATPC_BGPOPSCR  REG8(IT83XX_GPIO2_BASE+0xF0)
+#define IT83XX_VBATPC_XLPIER    REG8(IT83XX_GPIO2_BASE+0xF5)
 
 enum {
+	/* GPIO group index */
 	GPIO_A = 0x1,
 	GPIO_B = 0x2,
 	GPIO_C = 0x3,
@@ -663,23 +791,74 @@ enum {
 	GPIO_K = 0xb,
 	GPIO_L = 0xc,
 	GPIO_M = 0xd,
+#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	GPIO_O = 0xe,
+	GPIO_P = 0xf,
+	GPIO_Q = 0x10,
+	GPIO_R = 0x11,
+#endif
 	GPIO_PORT_COUNT,
 
 	/* NOTE: Support GPIO input only if KSO/KSI pins are used as GPIO. */
-	GPIO_KBS_OFF = 0x700,
 	/* KSI[7-0]  GPIO data mirror register. */
-	GPIO_KSI     = GPIO_KBS_OFF + 0x9,
+	GPIO_KSI,
 	/* KSO[15-8] GPIO data mirror register. */
-	GPIO_KSO_H   = GPIO_KBS_OFF + 0xc,
+	GPIO_KSO_H,
 	/* KSO[7-0]  GPIO data mirror register. */
-	GPIO_KSO_L   = GPIO_KBS_OFF + 0xf,
+	GPIO_KSO_L,
+	/* Compiler check COUNT and gpio_group_to_reg member cnt match or not */
+	COUNT,
+};
+
+struct gpio_reg_t {
+	/* GPIO port data register (bit mapping to pin) */
+	uint32_t reg_gpdr;
+	/* GPIO port output type register (bit mapping to pin) */
+	uint32_t reg_gpotr;
+	/* GPIO port control register (byte mapping to pin) */
+	uint32_t reg_gpcr;
 };
+
+/* GPIO group index convert to GPIO data/output type/ctrl group address */
+static const struct gpio_reg_t gpio_group_to_reg[] = {
+	/*               GPDR,       GPOTR,      GPCR      */
+	[GPIO_A]     = { 0x00F01601, 0x00F01671, 0x00F01610 },
+	[GPIO_B]     = { 0x00F01602, 0x00F01672, 0x00F01618 },
+	[GPIO_C]     = { 0x00F01603, 0x00F01673, 0x00F01620 },
+	[GPIO_D]     = { 0x00F01604, 0x00F01674, 0x00F01628 },
+	[GPIO_E]     = { 0x00F01605, 0x00F01675, 0x00F01630 },
+	[GPIO_F]     = { 0x00F01606, 0x00F01676, 0x00F01638 },
+	[GPIO_G]     = { 0x00F01607, 0x00F01677, 0x00F01640 },
+	[GPIO_H]     = { 0x00F01608, 0x00F01678, 0x00F01648 },
+	[GPIO_I]     = { 0x00F01609, 0x00F01679, 0x00F01650 },
+	[GPIO_J]     = { 0x00F0160a, 0x00F0167a, 0x00F01658 },
+	[GPIO_K]     = { 0x00F0160b, 0x00F0167b, 0x00F01690 },
+	[GPIO_L]     = { 0x00F0160c, 0x00F0167c, 0x00F01698 },
+	[GPIO_M]     = { 0x00F0160d, 0x00F0167d, 0x00F016a0 },
+#if defined(CHIP_FAMILY_IT8XXX1) || defined(CHIP_FAMILY_IT8XXX2)
+	[GPIO_O]     = { 0x00F03E01, 0x00F03E71, 0x00F03E10 },
+	[GPIO_P]     = { 0x00F03E02, 0x00F03E72, 0x00F03E18 },
+	[GPIO_Q]     = { 0x00F03E03, 0x00F03E73, 0x00F03E20 },
+	[GPIO_R]     = { 0x00F03E04, 0x00F03E74, 0x00F03E28 },
+#endif
+	[GPIO_KSI]   = { 0x00F01D09,         -1,         -1 },
+	[GPIO_KSO_H] = { 0x00F01D0C,         -1,         -1 },
+	[GPIO_KSO_L] = { 0x00F01D0F,         -1,         -1 },
+};
+BUILD_ASSERT(ARRAY_SIZE(gpio_group_to_reg) == (COUNT));
+
 #define DUMMY_GPIO_BANK GPIO_A
 
-#define IT83XX_GPIO_DATA(port)     REG8(IT83XX_GPIO_DATA_BASE + port)
-#define IT83XX_GPIO_GPOT(port)     REG8(IT83XX_GPIO_OUTPUT_TYPE_BASE + port)
-#define IT83XX_GPIO_CTRL(port_offset, pin_offset) \
-	REG8(IT83XX_GPIO_BASE + port_offset + pin_offset)
+#define IT83XX_GPIO_DATA(port)                 \
+	REG8(gpio_group_to_reg[port].reg_gpdr)
+#define IT83XX_GPIO_GPOT(port)                 \
+	REG8(gpio_group_to_reg[port].reg_gpotr)
+#define IT83XX_GPIO_CTRL(port, pin_offset)     \
+	REG8(gpio_group_to_reg[port].reg_gpcr + pin_offset)
+#define GPCR_PORT_PIN_MODE_INPUT          BIT(7)
+#define GPCR_PORT_PIN_MODE_OUTPUT         BIT(6)
+#define GPCR_PORT_PIN_MODE_PULLUP         BIT(2)
+#define GPCR_PORT_PIN_MODE_PULLDOWN       BIT(1)
 
 /* --- Clock and Power Management (ECPM) --- */