Cleanup: Add chip support pd physical port count configuration

  Add chip support pd physical port count configuration.

BUG=none
BRANCH=none
TEST=build all -j

Change-Id: Ic473e53af44b5360aad6d2db74cf09ce5a3fa3e8
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009537
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>

6 files changed, 9 insertions, 4 deletions

diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 0fd7335080..28827d11eb 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -495,7 +495,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 	 * Disable integrated pd modules in hibernate for
 	 * better power consumption.
 	 */
-	for (i = 0; i < USBPD_PORT_COUNT; i++)
+	for (i = 0; i < IT83XX_USBPD_PHY_PORT_COUNT; i++)
 		it83xx_disable_pd_module(i);
 #endif
 
diff --git a/chip/it83xx/config_chip_it8320.h b/chip/it83xx/config_chip_it8320.h
index 3bbb2060ea..9fedd8258a 100644
--- a/chip/it83xx/config_chip_it8320.h
+++ b/chip/it83xx/config_chip_it8320.h
@@ -40,6 +40,8 @@
  * of the control register (bit1 and bit5 at register IT83XX_USBPD_CCCSR).
  */
 #define IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
+/* Chip IT8320BX actually has TCPC physical port count */
+#define IT83XX_USBPD_PHY_PORT_COUNT    2
 /* For IT8320BX, we have to write 0xff to clear pending bit.*/
 #define IT83XX_ESPI_VWCTRL1_WRITE_FF_CLEAR
 /* For IT8320BX, we have to read observation register of external timer two
@@ -83,6 +85,8 @@
 #define IT83XX_INTC_PLUG_IN_SUPPORT
 /* Chip Dx transmit status bit of PD register is different from Bx. */
 #define IT83XX_PD_TX_ERROR_STATUS_BIT5
+/* Chip IT8320DX actually has TCPC physical port count */
+#define IT83XX_USBPD_PHY_PORT_COUNT    2
 #else
 #error "Unsupported chip variant!"
 #endif
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index b760adbc6b..22c62f4c01 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -57,6 +57,8 @@
 #define IT83XX_GPIO_INT_FLEXIBLE
 /* Enable detect type-c plug in interrupt. */
 #define IT83XX_INTC_PLUG_IN_SUPPORT
+/* Chip IT83202BX actually has TCPC physical port count. */
+#define IT83XX_USBPD_PHY_PORT_COUNT    3
 #else
 #error "Unsupported chip variant!"
 #endif
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index 24947cca59..c753e095e0 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -644,7 +644,7 @@ void gpio_pre_init(void)
 
 #ifndef CONFIG_USB_PD_TCPM_ITE83XX
 	/* To prevent cc pins leakage if we don't use pd module */
-	for (i = 0; i < USBPD_PORT_COUNT; i++) {
+	for (i = 0; i < IT83XX_USBPD_PHY_PORT_COUNT; i++) {
 		IT83XX_USBPD_CCGCR(i) = 0x1f;
 		/*
 		 * bit7 and bit3: Dis-connect CC with UP/RD/DET/TX/RX.
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index a6373ddc20..af76705274 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1547,7 +1547,6 @@ enum i2c_channels {
 enum usbpd_port {
 	USBPD_PORT_A,
 	USBPD_PORT_B,
-	USBPD_PORT_COUNT,
 };
 
 #define USB_VID_ITE 0x048d
diff --git a/driver/tcpm/it83xx.c b/driver/tcpm/it83xx.c
index dd18bc2f70..3cad1ef4a7 100644
--- a/driver/tcpm/it83xx.c
+++ b/driver/tcpm/it83xx.c
@@ -35,7 +35,7 @@ const struct usbpd_ctrl_t usbpd_ctrl_regs[] = {
 	{&IT83XX_GPIO_GPCRF4, &IT83XX_GPIO_GPCRF5, IT83XX_IRQ_USBPD0},
 	{&IT83XX_GPIO_GPCRH1, &IT83XX_GPIO_GPCRH2, IT83XX_IRQ_USBPD1},
 };
-BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == USBPD_PORT_COUNT);
+BUILD_ASSERT(ARRAY_SIZE(usbpd_ctrl_regs) == IT83XX_USBPD_PHY_PORT_COUNT);
 
 /*
  * This function disables integrated pd module and enables 5.1K resistor for