Revert "chell: Remove chell from master"

This reverts commit 2de33140216be7f95c33990317483d3c65ae641b.

Reason for revert: breaks chell postsubmit builder

Original change's description:
> chell: Remove chell from master
> 
> chell is out of space and we've removed a lot functions but it's still
> full.  Now it's time to delete it. "Cara mia addio..."
> 
> BUG=none
> BRANCH=None
> TEST=`make -j buildall`
> 
> Change-Id: I064d55356012000e51654a1aa247226b33a8f0ff
> Signed-off-by: Aseda Aboagye <aaboagye@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1953761
> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>

Bug: none
Change-Id: I7ecd836b6214a42d51c448650891c3a8e003a2c6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955163
Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
Commit-Queue: Dmitry Torokhov <dtor@chromium.org>
Tested-by: Dmitry Torokhov <dtor@chromium.org>

10 files changed, 1527 insertions, 0 deletions

diff --git a/board/chell/battery.c b/board/chell/battery.c
new file mode 100644
index 0000000000..1e5c59a978
--- /dev/null
+++ b/board/chell/battery.c
@@ -0,0 +1,81 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery.h"
+#include "battery_smart.h"
+#include "charge_state.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "util.h"
+
+/* Shutdown mode parameter to write to manufacturer access register */
+#define SB_SHUTDOWN_DATA	0x0010
+
+/* Battery info for proto */
+static const struct battery_info info = {
+	.voltage_max		= 13050,	/* mV */
+	.voltage_normal		= 11400,
+	.voltage_min		= 9000,
+	.precharge_current	= 392,		/* mA */
+	.start_charging_min_c	= 0,
+	.start_charging_max_c	= 60,
+	.charging_min_c		= 0,
+	.charging_max_c		= 60,
+	.discharging_min_c	= 0,
+	.discharging_max_c	= 60,
+};
+
+const struct battery_info *battery_get_info(void)
+{
+	return &info;
+}
+
+int board_cut_off_battery(void)
+{
+	int rv;
+
+	/* Ship mode command must be sent twice to take effect */
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	if (rv != EC_SUCCESS)
+		return EC_RES_ERROR;
+
+	rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
+	return rv ? EC_RES_ERROR : EC_RES_SUCCESS;
+}
+
+int charger_profile_override(struct charge_state_data *curr)
+{
+	const struct battery_info *batt_info;
+	/* battery temp in 0.1 deg C */
+	int bat_temp_c = curr->batt.temperature - 2731;
+
+	batt_info = battery_get_info();
+	/* Don't charge if outside of allowable temperature range */
+	if (bat_temp_c >= batt_info->charging_max_c * 10 ||
+	    bat_temp_c < batt_info->charging_min_c * 10) {
+		curr->requested_current = 0;
+		curr->requested_voltage = 0;
+		curr->batt.flags &= ~BATT_FLAG_WANT_CHARGE;
+		curr->state = ST_IDLE;
+	}
+	return 0;
+}
+
+/* Customs options controllable by host command. */
+#define PARAM_FASTCHARGE (CS_PARAM_CUSTOM_PROFILE_MIN + 0)
+
+enum ec_status charger_profile_override_get_param(uint32_t param,
+						  uint32_t *value)
+{
+	return EC_RES_INVALID_PARAM;
+}
+
+enum ec_status charger_profile_override_set_param(uint32_t param,
+						  uint32_t value)
+{
+	return EC_RES_INVALID_PARAM;
+}
diff --git a/board/chell/board.c b/board/chell/board.c
new file mode 100644
index 0000000000..7b56ca621a
--- /dev/null
+++ b/board/chell/board.c
@@ -0,0 +1,465 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Chell board-specific configuration */
+
+#include "adc_chip.h"
+#include "bd99992gw.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chipset.h"
+#include "console.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "pi3usb9281.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tcpci.h"
+#include "temp_sensor.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_charge.h"
+#include "usb_mux.h"
+#include "usb_mux/ps874x.h"
+#include "usb_pd.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+#define I2C_ADDR_BD99992_FLAGS 0x30
+
+/* Exchange status with PD MCU. */
+static void pd_mcu_interrupt(enum gpio_signal signal)
+{
+#ifdef HAS_TASK_PDCMD
+	/* Exchange status with PD MCU to determine interrupt cause */
+	host_command_pd_send_status(0);
+#endif
+}
+
+void vbus0_evt(enum gpio_signal signal)
+{
+	/* VBUS present GPIO is inverted */
+	usb_charger_vbus_change(0, !gpio_get_level(signal));
+	task_wake(TASK_ID_PD_C0);
+}
+
+void vbus1_evt(enum gpio_signal signal)
+{
+	/* VBUS present GPIO is inverted */
+	usb_charger_vbus_change(1, !gpio_get_level(signal));
+	task_wake(TASK_ID_PD_C1);
+}
+
+void usb0_evt(enum gpio_signal signal)
+{
+	task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
+}
+
+void usb1_evt(enum gpio_signal signal)
+{
+	task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
+}
+
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
+	[ADC_VBUS] = {"VBUS", 30000, 1024, 0, 1},
+	/* Adapter current output or battery discharging current */
+	[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
+	/* System current consumption */
+	[ADC_PSYS] = {"PSYS", 1, 1, 0, 4},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
+const struct pwm_t pwm_channels[] = {
+	/* Use alternate 100kHz clock source, keep active in low-power idle */
+	{2, PWM_CONFIG_ALT_CLOCK | PWM_CONFIG_DSLEEP},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct i2c_port_t i2c_ports[]  = {
+	{"pmic",     MEC1322_I2C0_0, 400,  GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
+	{"muxes",    MEC1322_I2C0_1, 400,  GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
+	{"pd_mcu",   MEC1322_I2C1,   500,  GPIO_I2C1_SCL,   GPIO_I2C1_SDA},
+	{"batt",     MEC1322_I2C3,   100,  GPIO_I2C3_SCL,   GPIO_I2C3_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC,
+			.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS,
+		},
+		.drv = &tcpci_tcpm_drv,
+	},
+	{
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC,
+			.addr_flags = CONFIG_TCPC_I2C_BASE_ADDR_FLAGS + 1,
+		},
+		.drv = &tcpci_tcpm_drv,
+
+	},
+};
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_AC_PRESENT,
+	GPIO_LID_OPEN,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+/*
+ * We have total 28 pins for keyboard connecter, {-1, -1} mean
+ * the N/A pin that don't consider it and reserve index 0 area
+ * that we don't have pin 0.
+ */
+const int keyboard_factory_scan_pins[][2] = {
+		{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1},
+		{12, 6}, {4, 3}, {4, 2}, {0, 2}, {14, 2},
+		{4, 0}, {0, 0}, {-1, -1}, {3, 2}, {10, 3},
+		{10, 0}, {12, 5}, {-1, -1}, {10, 2}, {-1, -1},
+		{0, 1}, {10, 4}, {-1, -1}, {-1, -1}, {0, 4},
+		{10, 7}, {10, 6}, {0, 3}, {0, 5},
+};
+
+const int keyboard_factory_scan_pins_used =
+			ARRAY_SIZE(keyboard_factory_scan_pins);
+#endif
+
+struct pi3usb9281_config pi3usb9281_chips[] = {
+	{
+		.i2c_port = I2C_PORT_USB_CHARGER_1,
+		.mux_lock = NULL,
+	},
+	{
+		.i2c_port = I2C_PORT_USB_CHARGER_2,
+		.mux_lock = NULL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
+	     CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT);
+
+static int ps874x_tune_mux(int port)
+{
+	/* Apply same USB EQ settings to both Type-C mux */
+	ps874x_tune_usb_eq(port,
+			   PS874X_USB_EQ_TX_6_5_DB,
+			   PS874X_USB_EQ_RX_14_3_DB);
+
+	return EC_SUCCESS;
+}
+
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	{
+		.port_addr = 0x1A,
+		.driver = &ps874x_usb_mux_driver,
+		.board_init = &ps874x_tune_mux,
+	},
+	{
+		.port_addr = 0x10,
+		.driver = &ps874x_usb_mux_driver,
+		.board_init = &ps874x_tune_mux,
+	}
+};
+
+/**
+ * Reset PD MCU
+ */
+void board_reset_pd_mcu(void)
+{
+	gpio_set_level(GPIO_PD_RST_L, 0);
+	usleep(100);
+	gpio_set_level(GPIO_PD_RST_L, 1);
+}
+
+const struct temp_sensor_t temp_sensors[] = {
+	{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0, 4},
+
+	/* These BD99992GW temp sensors are only readable in S0 */
+	{"Ambient", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+		BD99992GW_ADC_CHANNEL_SYSTHERM0, 4},
+	{"Charger", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+		BD99992GW_ADC_CHANNEL_SYSTHERM1, 4},
+	{"DRAM", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+		BD99992GW_ADC_CHANNEL_SYSTHERM2, 4},
+	{"Wifi", TEMP_SENSOR_TYPE_BOARD, bd99992gw_get_val,
+		BD99992GW_ADC_CHANNEL_SYSTHERM3, 4},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+static void board_pmic_init(void)
+{
+	/* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3e, 0x04);
+
+	/*
+	 * No need to re-init below settings since they are present on all MP
+	 * ROs and PMIC settings are sticky across sysjump
+	 */
+	if (system_jumped_to_this_image())
+		return;
+
+	/* Set CSDECAYEN / VCCIO decays to 0V at assertion of SLP_S0# */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x30, 0x4a);
+
+	/*
+	 * Set V100ACNT / V1.00A Control Register:
+	 * Nominal output = 1.0V.
+	 */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x37, 0x1a);
+
+	/*
+	 * Set V085ACNT / V0.85A Control Register:
+	 * Lower power mode = 0.7V.
+	 * Nominal output = 1.0V.
+	 */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x38, 0x7a);
+
+	/* VRMODECTRL - enable low-power mode for VCCIO and V0.85A */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x3b, 0x18);
+}
+DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_DEFAULT);
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable PD MCU interrupt */
+	gpio_enable_interrupt(GPIO_PD_MCU_INT);
+
+	/* Enable VBUS interrupt */
+	gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
+	gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
+
+	/* Enable pericom BC1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
+
+	/* Provide AC status to the PCH */
+	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
+
+	/* Proto board workarounds */
+	if (system_get_board_version() == 0) {
+		/* Disable interrupt for SLP_S0 */
+		gpio_set_flags(GPIO_PCH_SLP_S0_L,
+			       GPIO_INPUT | GPIO_PULL_DOWN);
+
+		/* Add internal pullup on PLATFORM_EC_PROCHOT */
+		gpio_set_flags(GPIO_PLATFORM_EC_PROCHOT,
+			       GPIO_INPUT | GPIO_PULL_UP);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+/**
+ * Buffer the AC present GPIO to the PCH.
+ */
+static void board_extpower(void)
+{
+	gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
+}
+DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
+
+/**
+ * Set active charge port -- only one port can be active at a time.
+ *
+ * @param charge_port   Charge port to enable.
+ *
+ * Returns EC_SUCCESS if charge port is accepted and made active,
+ * EC_ERROR_* otherwise.
+ */
+int board_set_active_charge_port(int charge_port)
+{
+	/* charge port is a realy physical port */
+	int is_real_port = (charge_port >= 0 &&
+			    charge_port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	/* check if we are source vbus on that port */
+	int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
+						       GPIO_USB_C1_5V_EN);
+
+	if (is_real_port && source) {
+		CPRINTS("Skip enable p%d", charge_port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTS("New chg p%d", charge_port);
+
+	if (charge_port == CHARGE_PORT_NONE) {
+		/* Disable both ports */
+		gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
+		gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
+	} else {
+		/* Make sure non-charging port is disabled */
+		gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
+					     GPIO_USB_C1_CHARGE_EN_L, 1);
+		/* Enable charging port */
+		gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
+					     GPIO_USB_C0_CHARGE_EN_L, 0);
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * Set the charge limit based upon desired maximum.
+ *
+ * @param port          Port number.
+ * @param supplier      Charge supplier type.
+ * @param charge_ma     Desired charge limit (mA).
+ * @param charge_mv     Negotiated charge voltage (mV).
+ */
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(MAX(charge_ma,
+				   CONFIG_CHARGER_INPUT_CURRENT), charge_mv);
+}
+
+/* Called on AP S5 -> S3 transition */
+static void board_chipset_startup(void)
+{
+	gpio_set_level(GPIO_USB1_ENABLE, 1);
+	gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void board_chipset_shutdown(void)
+{
+	gpio_set_level(GPIO_USB1_ENABLE, 0);
+	gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S0 transition */
+static void board_chipset_resume(void)
+{
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1);
+	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 1);
+	gpio_set_level(GPIO_PP1800_DX_DMIC_EN, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S3 transition */
+static void board_chipset_suspend(void)
+{
+	gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
+	gpio_set_level(GPIO_PP1800_DX_AUDIO_EN, 0);
+	gpio_set_level(GPIO_PP1800_DX_DMIC_EN, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	CPRINTS("Triggering PMIC shutdown.");
+	uart_flush_output();
+
+	/* Trigger PMIC shutdown. */
+	if (i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS, 0x49, 0x01)) {
+		/*
+		 * If we can't tell the PMIC to shutdown, instead reset
+		 * and don't start the AP. Hopefully we'll be able to
+		 * communicate with the PMIC next time.
+		 */
+		CPRINTS("PMIC i2c failed.");
+		system_reset(SYSTEM_RESET_LEAVE_AP_OFF);
+	}
+
+	/* Await shutdown. */
+	while (1)
+		;
+}
+
+/* Make the pmic re-sequence the power rails under these conditions. */
+#define PMIC_RESET_FLAGS \
+	(EC_RESET_FLAG_WATCHDOG | EC_RESET_FLAG_SOFT | EC_RESET_FLAG_HARD)
+static void board_handle_reboot(void)
+{
+	int flags;
+
+	if (system_jumped_to_this_image())
+		return;
+
+	/* Interrogate current reset flags from previous reboot. */
+	flags = system_get_reset_flags();
+
+	if (!(flags & PMIC_RESET_FLAGS))
+		return;
+
+	/* Preserve AP off request. */
+	if (flags & EC_RESET_FLAG_AP_OFF)
+		chip_save_reset_flags(EC_RESET_FLAG_AP_OFF);
+
+	ccprintf("Restarting system with PMIC.\n");
+	/* Flush console */
+	cflush();
+
+	/* Bring down all rails but RTC rail (including EC power). */
+	gpio_set_level(GPIO_PMIC_LDO_EN, 1);
+	while (1)
+		; /* wait here */
+}
+DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
+
+/*
+ * Various voltage rails will be enabled / disabled by the PMIC when
+ * GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
+ * by approximately 25ms in order to allow V1.00A to sufficiently discharge
+ * first.
+ *
+ * Therefore, after GPIO_PMIC_SLP_SUS_L goes high, ignore the state of
+ * the V12_EN pin: Keep V0.85A enabled.
+ *
+ * When GPIO_PMIC_SLP_SUS_L goes low, delay 25ms, and make V12_EN function
+ * as normal - this should result in V0.85A discharging immediately after the
+ * i2c write completes.
+ */
+void chipset_set_pmic_slp_sus_l(int level)
+{
+	static int previous_level;
+	int val;
+
+	gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
+
+	if (previous_level != level) {
+		/* Rising edge: Force V0.85A enable. Falling: Pin control. */
+		val = level ? 0x80 : 0;
+		if (!level)
+			msleep(25);
+
+		i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992_FLAGS,
+			   0x43, val);
+		previous_level = level;
+	}
+}
diff --git a/board/chell/board.h b/board/chell/board.h
new file mode 100644
index 0000000000..7e4a7aa4d7
--- /dev/null
+++ b/board/chell/board.h
@@ -0,0 +1,217 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Chell board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/*
+ * Allow dangerous commands.
+ * TODO: Remove this config before production.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+/* Optional features */
+#define CONFIG_ADC
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_BOARD_VERSION_GPIO
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGE_RAMP_HW
+
+#define CONFIG_CHARGER
+
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_ISL9237
+#define CONFIG_CHARGER_ILIM_PIN_DISABLED
+#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
+#define CONFIG_CHARGER_PROFILE_OVERRIDE
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+#undef CONFIG_CMD_BATTFAKE
+#define CONFIG_CMD_CHARGER_ADC_AMON_BMON
+
+#define CONFIG_CHIPSET_SKYLAKE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_CLOCK_CRYSTAL
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HOSTCMD_PD
+#define CONFIG_HOSTCMD_PD_PANIC
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_FACTORY_TEST
+#define CONFIG_LED_COMMON
+#define CONFIG_LID_SWITCH
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LTO
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define CONFIG_POWER_S0IX
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
+/* All data won't fit in data RAM.  So, moving boundary slightly. */
+#undef CONFIG_RO_SIZE
+#define CONFIG_RO_SIZE (104 * 1024)
+#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
+/* We're space constrained on Chell, so reduce the UART TX buffer size. */
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 512
+#define CONFIG_USB_CHARGER
+#define CONFIG_USB_MUX_PS8740
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_COMM_LOCKED
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_GPIO
+#define CONFIG_BC12_DETECT_PI3USB9281
+#define CONFIG_BC12_DETECT_PI3USB9281_CHIP_COUNT 2
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_VBOOT_HASH
+
+#define CONFIG_SPI_FLASH_PORT 1
+#define CONFIG_SPI_FLASH
+#define CONFIG_FLASH_SIZE 524288
+#define CONFIG_SPI_FLASH_W25X40
+
+#define CONFIG_TEMP_SENSOR
+#define CONFIG_TEMP_SENSOR_BD99992GW
+#define CONFIG_THERMISTOR_NCP15WB
+#define CONFIG_DPTF
+
+/*
+ * Enable 1 slot of secure temporary storage to support
+ * suspend/resume with read/write memory training.
+ */
+#define CONFIG_VSTORE
+#define CONFIG_VSTORE_SLOT_COUNT 1
+
+#define CONFIG_WATCHDOG_HELP
+
+#define CONFIG_WIRELESS
+#define CONFIG_WIRELESS_SUSPEND \
+	(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
+
+/* Wireless signals */
+#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
+#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_DX_WLAN_EN
+
+/* LED signals */
+#define GPIO_BAT_LED_RED GPIO_CHARGE_LED_1
+#define GPIO_BAT_LED_GREEN GPIO_CHARGE_LED_2
+
+/* I2C ports */
+#define I2C_PORT_PMIC MEC1322_I2C0_0
+#define I2C_PORT_USB_CHARGER_1 MEC1322_I2C0_1
+#define I2C_PORT_USB_MUX MEC1322_I2C0_1
+#define I2C_PORT_USB_CHARGER_2 MEC1322_I2C0_0
+#define I2C_PORT_PD_MCU MEC1322_I2C1
+#define I2C_PORT_TCPC MEC1322_I2C1
+#define I2C_PORT_BATTERY MEC1322_I2C3
+#define I2C_PORT_CHARGER MEC1322_I2C3
+
+/* Thermal sensors read through PMIC ADC interface */
+#define I2C_PORT_THERMAL I2C_PORT_PMIC
+
+/* Modules we want to exclude */
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_BATTFAKE
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_HASH
+#undef CONFIG_CMD_HCDEBUG
+#undef CONFIG_CMD_I2C_SCAN
+#undef CONFIG_CMD_MD
+#undef CONFIG_CMD_MMAPINFO
+#undef CONFIG_CMD_POWERINDEBUG
+#undef CONFIG_CMD_PWR_AVG
+#undef CONFIG_CMD_SLEEPMASK
+#undef CONFIG_CMD_SLEEPMASK_SET
+#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_TEMP_SENSOR
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_EC_CMD_PD_CHIP_INFO
+#undef CONFIG_CMD_I2C_XFER
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_VBUS,
+	ADC_AMON_BMON,
+	ADC_PSYS,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+enum pwm_channel {
+	PWM_CH_KBLIGHT,
+
+	/* Number of PWM channels */
+	PWM_CH_COUNT
+};
+
+enum temp_sensor_id {
+	TEMP_SENSOR_BATTERY,
+
+	/* These temp sensors are only readable in S0 */
+	TEMP_SENSOR_AMBIENT,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_DRAM,
+	TEMP_SENSOR_WIFI,
+
+	TEMP_SENSOR_COUNT
+};
+
+/* TODO: determine the following board specific type-C power constants */
+/*
+ * delay to turn on the power supply max is ~16ms.
+ * delay to turn off the power supply max is about ~180ms.
+ */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY  30000  /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
+
+/* delay to turn on/off vconn */
+#define PD_VCONN_SWAP_DELAY 5000 /* us */
+
+/* Define typical operating power and max power */
+#define PD_OPERATING_POWER_MW 15000
+#define PD_MAX_POWER_MW       45000
+#define PD_MAX_CURRENT_MA     3000
+
+/* Try to negotiate to 20V since i2c noise problems should be fixed. */
+#define PD_MAX_VOLTAGE_MV     20000
+
+#ifdef CONFIG_KEYBOARD_FACTORY_TEST
+extern const int keyboard_factory_scan_pins[][2];
+extern const int keyboard_factory_scan_pins_used;
+#endif
+
+/* Reset PD MCU */
+void board_reset_pd_mcu(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/chell/build.mk b/board/chell/build.mk
new file mode 100644
index 0000000000..3995654f1e
--- /dev/null
+++ b/board/chell/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+# the IC is SMSC MEC1322 / external SPI is 512KB / external clock is crystal
+CHIP:=mec1322
+CHIP_SPI_SIZE_KB:=512
+
+board-y=board.o led.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/board/chell/ec.tasklist b/board/chell/ec.tasklist
new file mode 100644
index 0000000000..2ae8c29075
--- /dev/null
+++ b/board/chell/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/chell/gpio.inc b/board/chell/gpio.inc
new file mode 100644
index 0000000000..4529d8df7c
--- /dev/null
+++ b/board/chell/gpio.inc
@@ -0,0 +1,181 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(LID_OPEN,          PIN(27), GPIO_INT_BOTH, lid_interrupt)
+GPIO_INT(AC_PRESENT,        PIN(30), GPIO_INT_BOTH, extpower_interrupt)
+GPIO_INT(WP_L,              PIN(33), GPIO_INT_BOTH, switch_interrupt)
+/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
+GPIO_INT(POWER_BUTTON_L,    PIN(35), GPIO_INT_BOTH, power_button_interrupt)
+#ifdef CONFIG_POWER_S0IX
+GPIO_INT(PCH_SLP_S0_L,      PIN(211), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+/* RSMRST from PMIC */
+GPIO_INT(RSMRST_L_PGOOD,    PIN(63),  GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S4_L,      PIN(200), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S3_L,      PIN(206), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_SUS_L,     PIN(12),  GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PMIC_INT_L,        PIN(50),  GPIO_INT_FALLING, power_signal_interrupt)
+GPIO_INT(PD_MCU_INT,        PIN(122), GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt)
+GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(152), GPIO_INT_BOTH, vbus0_evt)
+GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(123), GPIO_INT_BOTH, vbus1_evt)
+GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt)
+GPIO_INT(USB_C1_BC12_INT_L, PIN(145), GPIO_INT_FALLING, usb1_evt)
+GPIO_INT(PMIC_DPWROK,       PIN(133), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(UART0_RX,          PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
+
+/* PMIC */
+GPIO(PMIC_LDO_EN,           PIN(55),  GPIO_OUT_LOW)
+GPIO(PMIC_SLP_SUS_L,        PIN(201), GPIO_OUT_LOW)
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(I2C0_0_SCL,            PIN(15),  GPIO_INPUT)
+GPIO(I2C0_0_SDA,            PIN(16),  GPIO_INPUT)
+GPIO(I2C0_1_SCL,            PIN(134), GPIO_INPUT)
+GPIO(I2C0_1_SDA,            PIN(17),  GPIO_INPUT)
+GPIO(I2C1_SCL,              PIN(22),  GPIO_INPUT)
+GPIO(I2C1_SDA,              PIN(23),  GPIO_INPUT)
+GPIO(I2C2_SCL,              PIN(20),  GPIO_INPUT)
+GPIO(I2C2_SDA,              PIN(21),  GPIO_INPUT)
+GPIO(I2C3_SCL,              PIN(24),  GPIO_INPUT)
+GPIO(I2C3_SDA,              PIN(25),  GPIO_INPUT)
+
+/* PCH */
+GPIO(PCH_SCI_L,             PIN(26),  GPIO_ODR_HIGH)
+GPIO(PCH_SMI_L,             PIN(44),  GPIO_ODR_HIGH)
+GPIO(PCH_PWRBTN_L,          PIN(45),  GPIO_OUTPUT)
+GPIO(PCH_SEC_DISABLE_L,     PIN(65),  GPIO_OUT_HIGH)
+GPIO(PCH_WAKE_L,            PIN(66),  GPIO_ODR_HIGH)
+GPIO(PCH_ACOK,              PIN(110), GPIO_OUT_LOW)
+GPIO(PCH_RCIN_L,            PIN(135), GPIO_ODR_HIGH)
+GPIO(PCH_RSMRST_L,          PIN(143), GPIO_OUT_LOW)
+GPIO(PCH_RTCRST,            PIN(163), GPIO_OUT_LOW)
+GPIO(SYS_RESET_L,           PIN(121), GPIO_ODR_HIGH)
+GPIO(ENTERING_RW,           PIN(41),  GPIO_OUT_LOW)
+#ifndef CONFIG_POWER_S0IX
+GPIO(PCH_SLP_S0_L,          PIN(211), GPIO_INPUT)
+#endif
+
+/* Devices and power */
+GPIO(PP1800_DX_DMIC_EN,     PIN(11),  GPIO_OUT_LOW)
+GPIO(PP1800_DX_AUDIO_EN,    PIN(141), GPIO_OUT_LOW)
+GPIO(PP3300_DX_WLAN_EN,     PIN(203), GPIO_OUT_LOW)
+GPIO(WLAN_OFF_L,            PIN(132), GPIO_OUT_LOW)
+GPIO(TRACKPAD_INT_L,        PIN(127), GPIO_INPUT)
+GPIO(ENABLE_BACKLIGHT,      PIN(202), GPIO_OUT_LOW)
+GPIO(ENABLE_TOUCHPAD,       PIN(53),  GPIO_OUT_LOW)
+GPIO(BAT_PRESENT_L,         PIN(56),  GPIO_INPUT)
+GPIO(PLATFORM_EC_PROCHOT,   PIN(151), GPIO_INPUT)
+GPIO(CPU_PROCHOT,           PIN(52),  GPIO_OUT_LOW)
+
+/* USB PD and port power */
+GPIO(PD_RST_L,              PIN(130), GPIO_ODR_HIGH)
+GPIO(USB_PD_WAKE,           PIN(60),  GPIO_OUT_HIGH)
+GPIO(USB_C0_DP_HPD,         PIN(46),  GPIO_OUT_LOW)
+GPIO(USB_C1_DP_HPD,         PIN(51),  GPIO_OUT_LOW)
+GPIO(USB_C0_5V_EN,          PIN(154), GPIO_OUT_LOW)
+GPIO(USB_C1_5V_EN,          PIN(204), GPIO_OUT_LOW)
+GPIO(USB_C0_CHARGE_EN_L,    PIN(64),  GPIO_OUT_LOW)
+GPIO(USB_C1_CHARGE_EN_L,    PIN(210), GPIO_OUT_LOW)
+GPIO(USB1_ENABLE,           PIN(36),  GPIO_OUT_LOW)
+GPIO(USB2_OTG_ID,           PIN(13),  GPIO_ODR_LOW)
+GPIO(USB2_OTG_VBUSSENSE,    PIN(140), GPIO_OUT_LOW)
+
+#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
+#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
+#define GPIO_KB_OUTPUT_COL2 (GPIO_OUT_LOW)
+
+/* Board version */
+GPIO(BOARD_VERSION1,        PIN(10),  GPIO_INPUT)
+GPIO(BOARD_VERSION2,        PIN(7),   GPIO_INPUT)
+GPIO(BOARD_VERSION3,        PIN(6),   GPIO_INPUT)
+GPIO(KBD_KSO2,              PIN(101), GPIO_KB_OUTPUT_COL2)
+GPIO(PVT_CS0,               PIN(146), GPIO_ODR_HIGH)
+GPIO(KEYBOARD_BACKLIGHT,    PIN(34),  GPIO_OUT_LOW)
+
+/*
+ * TODO(crosbug.com/p/40848): These LEDs should be under control of the mec1322
+ * LED control unit. Remove these GPIO definitions once the LED control unit
+ * is functional.
+ */
+GPIO(CHARGE_LED_1,          PIN(155), GPIO_OUT_LOW)
+GPIO(CHARGE_LED_2,          PIN(156), GPIO_OUT_LOW)
+
+/* This pins are either NC, NC / pulled up, or connected to test points */
+GPIO(NC_031,                PIN(31),  GPIO_INPUT | GPIO_PULL_UP)
+GPIO(NC_047,                PIN(47),  GPIO_INPUT | GPIO_PULL_UP)
+GPIO(NC_067,                PIN(67),  GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FAN1_TTACH,         PIN(105), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FAN1_PWM,           PIN(136), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(ACCELGYRO3_INT_L,      PIN(147), GPIO_INPUT)
+GPIO(SHD_CS0_L,             PIN(150), GPIO_INPUT)
+GPIO(ACCELGYRO4_INT_L,      PIN(157), GPIO_INPUT)
+GPIO(TABLET_MODE_EC,        PIN(160), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(ACCEL1_INT_L,          PIN(161), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+
+/* GPIO162(UART_RX),  GPIO165(UART_TX) */
+ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
+
+/* KB pins */
+/* KB ROW - GPIO000-GPIO005 */
+ALTERNATE(PIN_MASK(0,  0x3f), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+/* KB ROW - GPIO100, GPIO102-GPIO104, GPIO106-GPIO107 */
+ALTERNATE(PIN_MASK(10, 0xdd), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
+/* KB COL - GPIO032 */
+ALTERNATE(PIN_MASK(3,  0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
+/* KB COL - GPIO040, GPIO42-GPIO43 */
+ALTERNATE(PIN_MASK(4,  0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
+/* KB COL - GPIO125-GPIO126 */
+ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
+/* KB COL - GPIO142, GPIO144 */
+ALTERNATE(PIN_MASK(14, 0x14), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
+/* Keyboard Backlight PWM - GPIO34 */
+ALTERNATE(PIN_MASK(3,  0x10), 1, MODULE_PWM, 0)
+
+/* LPC pins */
+/* LPC_CLK_RUN_L - GPIO014 */
+ALTERNATE(PIN_MASK(1,  0x10), 1, MODULE_LPC, 0)
+/* LAD[0:3] - GPIO111-GPIO114, SERIRQ - GPIO115, PCI_CLK - GPIO117 */
+ALTERNATE(PIN_MASK(11, 0xbe), 1, MODULE_LPC, 0)
+/* LRESET# - GPIO116 */
+ALTERNATE(PIN_MASK(11, 0x40), 1, MODULE_LPC, GPIO_INT_BOTH)
+/* LFRAME# - GPIO120 */
+ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
+
+/* SPI pins */
+/* MOSI - GPIO054 */
+ALTERNATE(PIN_MASK(5,  0x10), 1, MODULE_SPI, 0)
+/* MISO - GPIO164 */
+ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, GPIO_PULL_UP)
+/* PVT_SCLK - GPIO153 */
+ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)
+
+/* I2C pins */
+/* I2C0_0 CLK - GPIO015, I2C0_0 DAT - GPIO016, I2C0_1 DAT - GPIO017 */
+ALTERNATE(PIN_MASK(1,  0xe0), 2, MODULE_I2C, GPIO_ODR_HIGH)
+/* I2C{1,3} CLK / DAT - GPIO022-GPIO025*/
+ALTERNATE(PIN_MASK(2,  0x3c), 2, MODULE_I2C, GPIO_ODR_HIGH)
+/* I2C0_1 CLK - GPIO134 */
+ALTERNATE(PIN_MASK(13, 0x10), 2, MODULE_I2C, GPIO_ODR_HIGH)
+
+/* ADC pins */
+/* ADC1 - GPIO057 / PPVAR_BOOSTIN_SENSE */
+ALTERNATE(PIN_MASK(5,  0x80), 1, MODULE_ADC, GPIO_ANALOG)
+/* ADC3 - GPIO061 / IADP_ACMON_BMON. ADC4 - GPIO062 / PMON_PSYS */
+ALTERNATE(PIN_MASK(6,  0x06), 1, MODULE_ADC, GPIO_ANALOG)
+
+/* LED1 - GPIO155. LED2 - GPIO156 */
+/* ALTERNATE(PIN_MASK(15, 0x60), 2, MODULE_POWER_LED, 0) */
+
+/* VCC1_RST# - GPIO131 */
+ALTERNATE(PIN_MASK(13, 0x02), 1, MODULE_PMU, GPIO_ODR_HIGH)
+/* nRESET_OUT - GPIO121 */
+ALTERNATE(PIN_MASK(12, 0x02), 1, MODULE_PMU, GPIO_ODR_HIGH)
diff --git a/board/chell/led.c b/board/chell/led.c
new file mode 100644
index 0000000000..51808e9071
--- /dev/null
+++ b/board/chell/led.c
@@ -0,0 +1,145 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Power and battery LED control.
+ */
+
+#include "battery.h"
+#include "charge_state.h"
+#include "chipset.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "led_common.h"
+#include "util.h"
+
+#define BAT_LED_ON 1
+#define BAT_LED_OFF 0
+
+const enum ec_led_id supported_led_ids[] = {
+			EC_LED_ID_BATTERY_LED};
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+enum led_color {
+	LED_OFF = 0,
+	LED_AMBER,
+	LED_WHITE,
+	LED_COLOR_COUNT  /* Number of colors, not a color itself */
+};
+
+static int bat_led_set_color(enum led_color color)
+{
+	switch (color) {
+	case LED_OFF:
+		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
+		break;
+	case LED_AMBER:
+		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_ON);
+		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_OFF);
+		break;
+	case LED_WHITE:
+		gpio_set_level(GPIO_BAT_LED_RED, BAT_LED_OFF);
+		gpio_set_level(GPIO_BAT_LED_GREEN, BAT_LED_ON);
+		break;
+	default:
+		return EC_ERROR_UNKNOWN;
+	}
+	return EC_SUCCESS;
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_YELLOW] = 1;
+	brightness_range[EC_LED_COLOR_WHITE] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	switch (led_id) {
+	case EC_LED_ID_BATTERY_LED:
+		if (brightness[EC_LED_COLOR_WHITE] != 0)
+			bat_led_set_color(LED_WHITE);
+		else if (brightness[EC_LED_COLOR_YELLOW] != 0)
+			bat_led_set_color(LED_AMBER);
+		else
+			bat_led_set_color(LED_OFF);
+		break;
+	default:
+		break;
+	}
+
+	return EC_SUCCESS;
+}
+
+static void board_led_set_battery(void)
+{
+	static int battery_ticks;
+	uint32_t chflags = charge_get_flags();
+	static int power_ticks;
+	static int previous_state_suspend;
+
+	battery_ticks++;
+	power_ticks++;
+
+	if (chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) {
+		/*
+		 * Reset ticks if entering suspend so LED turns white
+		 * as soon as possible.
+		 */
+		if (!previous_state_suspend)
+			power_ticks = 0;
+
+		if (charge_get_state() == PWR_STATE_CHARGE)
+			/* Always indicate when charging, even in suspend. */
+			bat_led_set_color(LED_AMBER);
+		else
+			/* Blink once every one second. */
+			bat_led_set_color((power_ticks & 0x4) ?
+					  LED_WHITE : LED_OFF);
+
+		previous_state_suspend = 1;
+		return;
+	}
+	previous_state_suspend = 0;
+
+	switch (charge_get_state()) {
+	case PWR_STATE_CHARGE:
+		bat_led_set_color(LED_AMBER);
+		break;
+	case PWR_STATE_DISCHARGE:
+		if (charge_get_percent() < 12)
+			bat_led_set_color(
+				(battery_ticks & 0x4) ? LED_WHITE : LED_OFF);
+		else
+			bat_led_set_color(LED_OFF);
+		break;
+	case PWR_STATE_ERROR:
+		bat_led_set_color((battery_ticks & 0x2) ? LED_WHITE : LED_OFF);
+		break;
+	case PWR_STATE_CHARGE_NEAR_FULL:
+		bat_led_set_color(LED_WHITE);
+		break;
+	case PWR_STATE_IDLE: /* External power connected in IDLE */
+		if (chflags & CHARGE_FLAG_FORCE_IDLE)
+			bat_led_set_color(
+				(battery_ticks & 0x4) ? LED_AMBER : LED_OFF);
+		else
+			bat_led_set_color(LED_WHITE);
+		break;
+	default:
+		/* Other states don't alter LED behavior */
+		break;
+	}
+}
+
+/* Called by hook task every TICK */
+static void led_tick(void)
+{
+	if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
+		board_led_set_battery();
+}
+DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);
diff --git a/board/chell/lfw/gpio.inc b/board/chell/lfw/gpio.inc
new file mode 100644
index 0000000000..ab49347562
--- /dev/null
+++ b/board/chell/lfw/gpio.inc
@@ -0,0 +1,22 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Minimal set of GPIOs needed for LFW loader
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* SPI PVT chip select */
+GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
+
+/* Alternate functions GPIO definition */
+/* UART */
+ALTERNATE(PIN_MASK(16, 0x24),   1,      MODULE_UART,            0)
+/* SPI pins */
+ALTERNATE(PIN_MASK(5,  0x10),   1,      MODULE_SPI,             0)
+ALTERNATE(PIN_MASK(16, 0x10),   1,      MODULE_SPI,             0)
+ALTERNATE(PIN_MASK(15, 0x08),   1,      MODULE_SPI,             0)
diff --git a/board/chell/usb_pd_policy.c b/board/chell/usb_pd_policy.c
new file mode 100644
index 0000000000..3a2a6b2afc
--- /dev/null
+++ b/board/chell/usb_pd_policy.c
@@ -0,0 +1,378 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "atomic.h"
+#include "charge_manager.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "host_command.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
+			 PDO_FIXED_COMM_CAP)
+
+/* TODO: fill in correct source and sink capabilities */
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
+		PDO_BATT(4750, 21000, 15000),
+		PDO_VAR(4750, 21000, 3000),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+int pd_is_valid_input_voltage(int mv)
+{
+	return 1;
+}
+
+void pd_transition_voltage(int idx)
+{
+	/* No-operation: we are always 5V */
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
+			      GPIO_USB_C0_CHARGE_EN_L, 1);
+	/* Provide VBUS */
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
+			      GPIO_USB_C0_5V_EN, 1);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	gpio_set_level(port ? GPIO_USB_C1_5V_EN :
+			      GPIO_USB_C0_5V_EN, 0);
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
+				      GPIO_USB_C0_VBUS_WAKE_L);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_check_power_swap(int port)
+{
+	/*
+	 * Allow power swap as long as we are acting as a dual role device,
+	 * otherwise assume our role is fixed (not in S0 or console command
+	 * to fix our role).
+	 */
+	return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0;
+}
+
+int pd_check_data_swap(int port, int data_role)
+{
+	/* Allow data swap if we are a UFP, otherwise don't allow */
+	return (data_role == PD_ROLE_UFP) ? 1 : 0;
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* in G3, do not allow vconn swap since pp5000_A rail is off */
+	return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
+}
+
+void pd_execute_data_swap(int port, int data_role)
+{
+	/* Do nothing */
+}
+
+void pd_check_pr_role(int port, int pr_role, int flags)
+{
+	/*
+	 * If partner is dual-role power and dualrole toggling is on, consider
+	 * if a power swap is necessary.
+	 */
+	if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
+	    pd_get_dual_role(port) == PD_DRP_TOGGLE_ON) {
+		/*
+		 * If we are a sink and partner is not externally powered, then
+		 * swap to become a source. If we are source and partner is
+		 * externally powered, swap to become a sink.
+		 */
+		int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
+
+		if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
+		     (partner_extpower && pr_role == PD_ROLE_SOURCE))
+			pd_request_power_swap(port);
+	}
+}
+
+void pd_check_dr_role(int port, int dr_role, int flags)
+{
+	/* If UFP, try to switch to DFP */
+	if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
+		pd_request_data_swap(port);
+}
+/* ----------------- Vendor Defined Messages ------------------ */
+const struct svdm_response svdm_rsp = {
+	.identity = NULL,
+	.svids = NULL,
+	.modes = NULL,
+};
+
+int pd_custom_vdm(int port, int cnt, uint32_t *payload,
+		  uint32_t **rpayload)
+{
+	int cmd = PD_VDO_CMD(payload[0]);
+	uint16_t dev_id = 0;
+	int is_rw;
+
+	/* make sure we have some payload */
+	if (cnt == 0)
+		return 0;
+
+	switch (cmd) {
+	case VDO_CMD_VERSION:
+		/* guarantee last byte of payload is null character */
+		*(payload + cnt - 1) = 0;
+		CPRINTF("version: %s\n", (char *)(payload+1));
+		break;
+	case VDO_CMD_READ_INFO:
+	case VDO_CMD_SEND_INFO:
+		/* copy hash */
+		if (cnt == 7) {
+			dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
+			is_rw = VDO_INFO_IS_RW(payload[6]);
+
+			CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
+				HW_DEV_ID_MAJ(dev_id),
+				HW_DEV_ID_MIN(dev_id),
+				VDO_INFO_SW_DBG_VER(payload[6]),
+				is_rw);
+		} else if (cnt == 6) {
+			/* really old devices don't have last byte */
+			pd_dev_store_rw_hash(port, dev_id, payload + 1,
+					     SYSTEM_IMAGE_UNKNOWN);
+		}
+		break;
+	case VDO_CMD_CURRENT:
+		CPRINTF("Current: %dmA\n", payload[1]);
+		break;
+	case VDO_CMD_FLIP:
+		usb_mux_flip(port);
+		break;
+#ifdef CONFIG_USB_PD_LOGGING
+	case VDO_CMD_GET_LOG:
+		pd_log_recv_vdm(port, cnt, payload);
+		break;
+#endif /* CONFIG_USB_PD_LOGGING */
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_PD_ALT_MODE_DFP
+static int dp_flags[CONFIG_USB_PD_PORT_MAX_COUNT];
+/* DP Status VDM as returned by UFP */
+static uint32_t dp_status[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+static void svdm_safe_dp_mode(int port)
+{
+	/* make DP interface safe until configure */
+	dp_flags[port] = 0;
+	dp_status[port] = 0;
+	usb_mux_set(port, TYPEC_MUX_NONE,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port));
+}
+
+static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
+{
+	/* Only enter mode if device is DFP_D capable */
+	if (mode_caps & MODE_DP_SNK) {
+		svdm_safe_dp_mode(port);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int svdm_dp_status(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_STATUS | VDO_OPOS(opos));
+	payload[1] = VDO_DP_STATUS(0, /* HPD IRQ  ... not applicable */
+				   0, /* HPD level ... not applicable */
+				   0, /* exit DP? ... no */
+				   0, /* usb mode? ... no */
+				   0, /* multi-function ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)),
+				   0, /* power low? ... no */
+				   (!!(dp_flags[port] & DP_FLAGS_DP_ON)));
+	return 2;
+};
+
+static int svdm_dp_config(int port, uint32_t *payload)
+{
+	int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
+	int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
+	int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
+
+	if (!pin_mode)
+		return 0;
+
+	usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
+		    USB_SWITCH_CONNECT, pd_get_polarity(port));
+
+	payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
+			 CMD_DP_CONFIG | VDO_OPOS(opos));
+	payload[1] = VDO_DP_CFG(pin_mode,      /* pin mode */
+				1,             /* DPv1.3 signaling */
+				2);            /* UFP connected */
+	return 2;
+};
+
+/*
+ * timestamp of the next possible toggle to ensure the 2-ms spacing
+ * between IRQ_HPD.
+ */
+static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_MAX_COUNT];
+
+#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
+static void svdm_dp_post_config(int port)
+{
+	dp_flags[port] |= DP_FLAGS_DP_ON;
+	if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
+		return;
+
+	gpio_set_level(PORT_TO_HPD(port), 1);
+
+	/* set the minimum time delay (2ms) for the next HPD IRQ */
+	hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+}
+
+static int svdm_dp_attention(int port, uint32_t *payload)
+{
+	int cur_lvl;
+	int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
+	int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
+	enum gpio_signal hpd = PORT_TO_HPD(port);
+
+	cur_lvl = gpio_get_level(hpd);
+	dp_status[port] = payload[1];
+
+	/* Its initial DP status message prior to config */
+	if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
+		if (lvl)
+			dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
+		return 1;
+	}
+
+	if (irq & cur_lvl) {
+		uint64_t now = get_time().val;
+		/* wait for the minimum spacing between IRQ_HPD if needed */
+		if (now < hpd_deadline[port])
+			usleep(hpd_deadline[port] - now);
+
+		/* generate IRQ_HPD pulse */
+		gpio_set_level(hpd, 0);
+		usleep(HPD_DSTREAM_DEBOUNCE_IRQ);
+		gpio_set_level(hpd, 1);
+
+		/* set the minimum time delay (2ms) for the next HPD IRQ */
+		hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	} else if (irq & !cur_lvl) {
+		CPRINTF("ERR:HPD:IRQ&LOW\n");
+		return 0; /* nak */
+	} else {
+		gpio_set_level(hpd, lvl);
+		/* set the minimum time delay (2ms) for the next HPD IRQ */
+		hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL;
+	}
+	/* ack */
+	return 1;
+}
+
+static void svdm_exit_dp_mode(int port)
+{
+	svdm_safe_dp_mode(port);
+	gpio_set_level(PORT_TO_HPD(port), 0);
+}
+
+static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
+{
+	/* Always enter GFU mode */
+	return 0;
+}
+
+static void svdm_exit_gfu_mode(int port)
+{
+}
+
+static int svdm_gfu_status(int port, uint32_t *payload)
+{
+	/*
+	 * This is called after enter mode is successful, send unstructured
+	 * VDM to read info.
+	 */
+	pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
+	return 0;
+}
+
+static int svdm_gfu_config(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+static int svdm_gfu_attention(int port, uint32_t *payload)
+{
+	return 0;
+}
+
+const struct svdm_amode_fx supported_modes[] = {
+	{
+		.svid = USB_SID_DISPLAYPORT,
+		.enter = &svdm_enter_dp_mode,
+		.status = &svdm_dp_status,
+		.config = &svdm_dp_config,
+		.post_config = &svdm_dp_post_config,
+		.attention = &svdm_dp_attention,
+		.exit = &svdm_exit_dp_mode,
+	},
+	{
+		.svid = USB_VID_GOOGLE,
+		.enter = &svdm_enter_gfu_mode,
+		.status = &svdm_gfu_status,
+		.config = &svdm_gfu_config,
+		.attention = &svdm_gfu_attention,
+		.exit = &svdm_exit_gfu_mode,
+	}
+};
+const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
+#endif /* CONFIG_USB_PD_ALT_MODE_DFP */
+
diff --git a/board/chell_pd b/board/chell_pd
new file mode 120000
index 0000000000..eb83ce01b0
--- /dev/null
+++ b/board/chell_pd
@@ -0,0 +1 @@
+glados_pd/
\ No newline at end of file