ish: chip enablement of ish5.4 on tgl rvp platform

Chip level enablement of ish5.4 on tgl rvp platform.

BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp

Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>

14 files changed, 344 insertions, 45 deletions

diff --git a/chip/ish/build.mk b/chip/ish/build.mk
index 34eace379e..bce9322184 100644
--- a/chip/ish/build.mk
+++ b/chip/ish/build.mk
@@ -18,6 +18,7 @@ endif
 
 # Required chip modules
 chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o ish_persistent_data.o
+chip-$(CHIP_VARIANT_ISH5P4)+=reset_prep_wr.o
 chip-$(CONFIG_I2C)+=i2c.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 chip-$(CONFIG_HOSTCMD_HECI)+=host_command_heci.o
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index 148341db47..b4dea95767 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -35,7 +35,11 @@
 /*                               Memory Layout                               */
 /*****************************************************************************/
 
+#ifdef CHIP_VARIANT_ISH5P4
+#define CONFIG_RAM_BASE		0xFF200000
+#else
 #define CONFIG_RAM_BASE		0xFF000000
+#endif
 #define CONFIG_RAM_SIZE		0x000A0000
 #define CONFIG_RAM_BANK_SIZE		0x00008000
 
@@ -115,4 +119,14 @@
 #define GPIO_PIN(index) 0, (1 << (index))
 #define GPIO_PIN_MASK(m) .port = 0, .mask = (m)
 
+#ifdef CHIP_VARIANT_ISH5P4
+/* Use combined ISR for ipc communication between host and ISH */
+#define CONFIG_ISH_HOST2ISH_COMBINED_ISR
+/* Use Synopsys Designware uart */
+#define CONFIG_ISH_DW_UART
+#else
+/* Need to clear ISH fabric error */
+#define CONFIG_ISH_CLEAR_FABRIC_ERRORS
+#endif
+
 #endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/ish/config_flash_layout.h b/chip/ish/config_flash_layout.h
index b470702972..0430baf3eb 100644
--- a/chip/ish/config_flash_layout.h
+++ b/chip/ish/config_flash_layout.h
@@ -12,7 +12,11 @@
 #undef  CONFIG_FLASH_PSTATE
 #undef CONFIG_SPI_FLASH
 
+#ifdef CHIP_VARIANT_ISH5P4
+#define CONFIG_ISH_BOOT_START		0xFF200000
+#else
 #define CONFIG_ISH_BOOT_START		0xFF000000
+#endif
 
 /*****************************************************************************/
 /* The following macros are not applicable for ISH, however the build fails if
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h
index 7a2a420c82..06738fafb1 100644
--- a/chip/ish/hpet.h
+++ b/chip/ish/hpet.h
@@ -17,6 +17,7 @@
 /* HPET_GENERAL_CONFIG settings  */
 #define HPET_GENERAL_CONFIG		REG32(ISH_HPET_BASE + 0x10)
 #define HPET_ENABLE_CNF		BIT(0)
+#define HPET_LEGACY_RT_CNF	BIT(1)
 
 /* Interrupt status acknowledge register */
 #define HPET_INTR_CLEAR		REG32(ISH_HPET_BASE + 0x20)
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index 314af12693..1259dae7f4 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -258,7 +258,7 @@ int __hw_clock_source_init64(uint64_t start_t)
 	HPET_TIMER_CONF_CAP(1) |= timer1_config;
 
 	/* Enable HPET */
-	HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
+	HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF);
 
 	/* Return IRQ value for OS event timer */
 	return ISH_HPET_TIMER1_IRQ;
diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c
index d8dbd6a003..7e297a20eb 100644
--- a/chip/ish/i2c.c
+++ b/chip/ish/i2c.c
@@ -51,9 +51,16 @@ static uint16_t default_hcnt_scl_hs[] = { 160, 300, 160, 166, 175, 150, 162 };
 static uint16_t default_lcnt_scl_hs[] = { 320, 340, 320, 325, 325, 300, 297 };
 
 
+#ifdef CHIP_VARIANT_ISH5P4
+/* Change to I2C_FREQ_100 in real silicon platform */
+static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
+	I2C_FREQ_100, I2C_FREQ_100, I2C_FREQ_100
+};
+#else
 static uint8_t bus_freq[ISH_I2C_PORT_COUNT] = {
 	I2C_FREQ_120, I2C_FREQ_120, I2C_FREQ_120
 };
+#endif
 
 static struct i2c_context i2c_ctxs[ISH_I2C_PORT_COUNT] = {
 	{
diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c
index cce3298f01..5271aa3a91 100644
--- a/chip/ish/ipc_heci.c
+++ b/chip/ish/ipc_heci.c
@@ -459,7 +459,9 @@ static void ipc_host2ish_isr(void)
 	if ((pisr & IPC_PISR_HOST2ISH_BIT) && (pimr & IPC_PIMR_HOST2ISH_BIT))
 		handle_msg_recv_interrupt(IPC_PEER_ID_HOST);
 }
+#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR
 DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_isr);
+#endif
 
 static void ipc_host2ish_busy_clear_isr(void)
 {
@@ -470,7 +472,18 @@ static void ipc_host2ish_busy_clear_isr(void)
 	    (pimr & IPC_PIMR_ISH2HOST_CLR_BIT))
 		handle_busy_clear_interrupt(IPC_PEER_ID_HOST);
 }
+#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR
 DECLARE_IRQ(ISH_IPC_ISH2HOST_CLR_IRQ, ipc_host2ish_busy_clear_isr);
+#endif
+
+static __maybe_unused void ipc_host2ish_combined_isr(void)
+{
+	ipc_host2ish_isr();
+	ipc_host2ish_busy_clear_isr();
+}
+#ifdef CONFIG_ISH_HOST2ISH_COMBINED_ISR
+DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_combined_isr);
+#endif
 
 int ipc_write_timestamp(const ipc_handle_t handle, const void *buf,
 			const size_t buf_size, uint32_t *timestamp)
@@ -558,7 +571,8 @@ ipc_handle_t ipc_open(const enum ipc_peer_id peer_id,
 
 	if (ctx->initialized == 0) {
 		task_enable_irq(ctx->irq_in);
-		task_enable_irq(ctx->irq_clr);
+		if (!IS_ENABLED(CONFIG_ISH_HOST2ISH_COMBINED_ISR))
+			task_enable_irq(ctx->irq_clr);
 
 		ipc_enable_pimr_db_interrupt(ctx);
 		ipc_enable_pimr_clearing_interrupt(ctx);
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index f9c4f1a272..d4ac2ea47a 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -32,6 +32,23 @@ enum ish_i2c_port {
 /* In ISH, the devices are mapped to pre-defined addresses in the 32-bit
  * linear address space.
  */
+#ifdef CHIP_VARIANT_ISH5P4
+#define ISH_I2C0_BASE     0x00000000
+#define ISH_I2C1_BASE     0x00002000
+#define ISH_I2C2_BASE     0x00004000
+#define ISH_UART_BASE     0x08100000
+#define ISH_GPIO_BASE     0x00100000
+#define ISH_PMU_BASE      0x04200000
+#define ISH_OCP_BASE      0xFFFFFFFF
+#define ISH_MISC_BASE     0xFFFFFFFF
+#define ISH_DMA_BASE      0x10100000
+#define ISH_CCU_BASE      0x04300000
+#define ISH_IPC_BASE      0x04100000
+#define ISH_WDT_BASE      0x04900000
+#define ISH_IOAPIC_BASE   0xFEC00000
+#define ISH_HPET_BASE     0x04700000
+#define ISH_LAPIC_BASE    0xFEE00000
+#else
 #define ISH_I2C0_BASE     0x00100000
 #define ISH_I2C1_BASE     0x00102000
 #define ISH_I2C2_BASE     0x00105000
@@ -47,8 +64,28 @@ enum ish_i2c_port {
 #define ISH_IOAPIC_BASE   0xFEC00000
 #define ISH_HPET_BASE     0xFED00000
 #define ISH_LAPIC_BASE    0xFEE00000
+#endif
 
 /* HW interrupt pins mapped to IOAPIC, from I/O sources */
+#ifdef CHIP_VARIANT_ISH5P4
+#define ISH_I2C0_IRQ               15
+#define ISH_I2C1_IRQ               16
+#define ISH_FABRIC_IRQ             12
+#define ISH_I2C2_IRQ               17
+#define ISH_WDT_IRQ                26
+#define ISH_GPIO_IRQ               13
+#define ISH_HPET_TIMER1_IRQ        14
+#define ISH_IPC_HOST2ISH_IRQ       0
+#define ISH_PMU_WAKEUP_IRQ         10
+#define ISH_D3_RISE_IRQ            9
+#define ISH_D3_FALL_IRQ            9
+#define ISH_BME_RISE_IRQ           9
+#define ISH_BME_FALL_IRQ           9
+#define ISH_IPC_ISH2HOST_CLR_IRQ   0
+#define ISH_UART0_IRQ              23
+#define ISH_UART1_IRQ              24
+#define ISH_RESET_PREP_IRQ         6
+#else
 #define ISH_I2C0_IRQ               0
 #define ISH_I2C1_IRQ               1
 #define ISH_FABRIC_IRQ             5
@@ -66,6 +103,7 @@ enum ish_i2c_port {
 #define ISH_UART0_IRQ              34
 #define ISH_UART1_IRQ              35
 #define ISH_RESET_PREP_IRQ         62
+#endif
 
 /* Interrupt vectors 0-31 are architecture reserved.
  * Vectors 32-255 are user-defined.
@@ -281,7 +319,12 @@ enum ish_i2c_port {
 					 FABRIC_M_ERR_BIT)
 
 /* CSME Registers */
-#define ISH_RST_REG			REG32(ISH_IPC_BASE + 0x44)
+#ifdef CHIP_VARIANT_ISH5P4
+#define SEC_OFFSET			0x10000
+#else
+#define SEC_OFFSET			0x0
+#endif
+#define ISH_RST_REG			REG32(ISH_IPC_BASE + SEC_OFFSET + 0x44)
 
 /* IOAPIC registers */
 #define IOAPIC_IDX			REG32(ISH_IOAPIC_BASE + 0x0)
diff --git a/chip/ish/reset_prep_wr.c b/chip/ish/reset_prep_wr.c
new file mode 100644
index 0000000000..c192fb3723
--- /dev/null
+++ b/chip/ish/reset_prep_wr.c
@@ -0,0 +1,40 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Workaround for ISH5.4 reset prep handling before full PM is enabled */
+#include "common.h"
+#include "hooks.h"
+#include "interrupts.h"
+#include "registers.h"
+#include "system.h"
+#include "task.h"
+
+/*
+ * IRQ fires when we receive a RESET_PREP message from AP. This happens at S0
+ * entry.
+ */
+static void reset_prep_wr_isr(void)
+{
+	system_reset(SYSTEM_RESET_HARD);
+}
+DECLARE_IRQ(ISH_RESET_PREP_IRQ, reset_prep_wr_isr);
+
+void reset_prep_init(void)
+{
+	/* Clear reset bit */
+	ISH_RST_REG = 0;
+
+	/* Clear reset history register from previous boot. */
+	CCU_RST_HST = CCU_RST_HST;
+	/* Unmask reset prep avail interrupt mask */
+	PMU_RST_PREP = 0;
+	/* Clear TCG Enable, no trunk level clock gating*/
+	CCU_TCG_ENABLE = 0;
+	/* Clear BCG Enable, no block level clock gating*/
+	CCU_BCG_ENABLE = 0;
+
+	task_enable_irq(ISH_RESET_PREP_IRQ);
+}
+DECLARE_HOOK(HOOK_INIT, reset_prep_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/ish/system.c b/chip/ish/system.c
index 2d4a55bd3b..280bf57fa4 100644
--- a/chip/ish/system.c
+++ b/chip/ish/system.c
@@ -35,7 +35,8 @@ int system_is_reboot_warm(void)
 void system_pre_init(void)
 {
 	ish_fwst_set_fw_status(FWSTS_FW_IS_RUNNING);
-	task_enable_irq(ISH_FABRIC_IRQ);
+	if (IS_ENABLED(CONFIG_ISH_CLEAR_FABRIC_ERRORS))
+		task_enable_irq(ISH_FABRIC_IRQ);
 	ish_pm_init();
 	ish_persistent_data_init();
 }
@@ -174,7 +175,7 @@ void system_set_image_copy(enum system_image_copy_t copy)
 {
 }
 
-static void fabric_isr(void)
+static __maybe_unused void fabric_isr(void)
 {
 	/**
 	 * clear fabric error status, otherwise it will wakeup ISH immediately
@@ -184,5 +185,6 @@ static void fabric_isr(void)
 	if (FABRIC_AGENT_STATUS & FABRIC_MIA_STATUS_BIT_ERR)
 		FABRIC_AGENT_STATUS = FABRIC_AGENT_STATUS;
 }
-
+#ifdef CONFIG_ISH_CLEAR_FABRIC_ERRORS
 DECLARE_IRQ(ISH_FABRIC_IRQ, fabric_isr);
+#endif
diff --git a/chip/ish/uart.c b/chip/ish/uart.c
index 63709e86c7..93df2c6504 100644
--- a/chip/ish/uart.c
+++ b/chip/ish/uart.c
@@ -5,6 +5,7 @@
 
 /* UART module for ISH */
 #include "common.h"
+#include "math_util.h"
 #include "console.h"
 #include "uart_defs.h"
 #include "atomic.h"
@@ -149,18 +150,25 @@ static void uart_hw_init(enum UART_PORT id)
 	uint8_t mcr = 0;
 	uint8_t fcr = 0;
 	struct uart_ctx *ctx = &uart_ctx[id];
+	uint8_t fraction;
 
 	/* Calculate baud rate divisor */
 	divisor = (ctx->input_freq / ctx->baud_rate) >> 4;
-
-	MUL(ctx->id) = (divisor * ctx->baud_rate);
-	DIV(ctx->id) = (ctx->input_freq / 16);
-	PS(ctx->id) = 16;
+	if (IS_ENABLED(CONFIG_ISH_DW_UART)) {
+		/* calculate the fractional part */
+		fraction = ceil_for(ctx->input_freq, ctx->baud_rate) - (divisor << 4);
+	} else {
+		MUL(ctx->id) = (divisor * ctx->baud_rate);
+		DIV(ctx->id) = (ctx->input_freq / 16);
+		PS(ctx->id) = 16;
+	}
 
 	/* Set the DLAB to access the baud rate divisor registers */
 	LCR(ctx->id) = LCR_DLAB;
 	DLL(ctx->id) = (divisor & 0xff);
 	DLH(ctx->id) = ((divisor >> 8) & 0xff);
+	if (IS_ENABLED(CONFIG_ISH_DW_UART))
+		DLF(ctx->id) = fraction;
 
 	/* 8 data bits, 1 stop bit, no parity, clear DLAB */
 	LCR(ctx->id) = LCR_8BIT_CHR;
@@ -169,19 +177,24 @@ static void uart_hw_init(enum UART_PORT id)
 		mcr = MCR_AUTO_FLOW_EN;
 
 	/* needs to be set regardless of flow control */
-	mcr |= MCR_INTR_ENABLE;
+	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
+		mcr |= MCR_INTR_ENABLE;
 
 	mcr |= (MCR_RTS | MCR_DTR);
 	MCR(ctx->id) = mcr;
 
-	fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
+	if (IS_ENABLED(CONFIG_ISH_DW_UART))
+		fcr = FCR_TET_EMPTY | FCR_RT_1CHAR;
+	else
+		fcr = FCR_FIFO_SIZE_64 | FCR_ITL_FIFO_64_BYTES_1;
 
 	/* configure FIFOs */
 	FCR(ctx->id) = (fcr | FCR_FIFO_ENABLE
 			| FCR_RESET_RX | FCR_RESET_TX);
 
-	/* enable UART unit */
-	ABR(ctx->id) = ABR_UUE;
+	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
+		/* enable UART unit */
+		ABR(ctx->id) = ABR_UUE;
 
 	/* clear the port */
 	RBR(ctx->id);
@@ -197,13 +210,15 @@ static void uart_stop_hw(enum UART_PORT id)
 	int i;
 	uint32_t fifo_len;
 
-	/* Manually clearing the fifo from possible noise.
-	 * Entering D0i3 when fifo is not cleared may result in a hang.
-	 */
-	fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
+	if (!IS_ENABLED(CONFIG_ISH_DW_UART)) {
+		/* Manually clearing the fifo from possible noise.
+	 	 * Entering D0i3 when fifo is not cleared may result in a hang.
+	 	 */
+		fifo_len = (FOR(id) & FOR_OCCUPANCY_MASK) >> FOR_OCCUPANCY_OFFS;
 
-	for (i = 0; i < fifo_len; i++)
-		(void)RBR(id);
+		for (i = 0; i < fifo_len; i++)
+			(void)RBR(id);
+	}
 
 	/* No interrupts are enabled */
 	IER(id) = 0;
@@ -212,8 +227,9 @@ static void uart_stop_hw(enum UART_PORT id)
 	/* Clear and disable FIFOs */
 	FCR(id) = (FCR_RESET_RX | FCR_RESET_TX);
 
-	/* Disable uart unit */
-	ABR(id) = 0;
+	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
+		/* Disable uart unit */
+		ABR(id) = 0;
 }
 
 static int uart_client_init(enum UART_PORT id, uint32_t baud_rate_id, int flags)
@@ -245,11 +261,12 @@ static void uart_drv_init(void)
 	for (i = 0; i < UART_DEVICES; i++)
 		uart_stop_hw(i);
 
-	/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
-	 * to allow PMU to clock gate ISH
-	 */
-	HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
-			| GIEN_UART1_EN | GIEN_PWR_MGMT);
+	if (!IS_ENABLED(CONFIG_ISH_DW_UART))
+		/* Enable HSU global interrupts (DMA/U0/U1) and set PMEN bit
+	 	 * to allow PMU to clock gate ISH
+	 	 */
+		HSU_REG_GIEN = (GIEN_DMA_EN | GIEN_UART0_EN
+				| GIEN_UART1_EN | GIEN_PWR_MGMT);
 
 	task_enable_irq(ISH_DEBUG_UART_IRQ);
 }
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index ed37c47d13..b573ef7710 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -13,18 +13,20 @@
 
 #define UART_ERROR		-1
 #define UART_BUSY		-2
-#define HSU_BASE		ISH_UART_BASE
+#ifdef CHIP_VARIANT_ISH5P4
+#define UART0_OFFS		(0x00)
+#define UART1_OFFS		(0x2000)
+#define UART2_OFFS		(0x4000)
+#else
 #define UART0_OFFS		(0x80)
-#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
-#define UART0_SIZE		(0x80)
-
 #define UART1_OFFS		(0x100)
-#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
-#define UART1_SIZE		(0x80)
-
 #define UART2_OFFS		(0x180)
+#endif
+
+#define HSU_BASE		ISH_UART_BASE
+#define UART0_BASE		(ISH_UART_BASE + UART0_OFFS)
+#define UART1_BASE		(ISH_UART_BASE + UART1_OFFS)
 #define UART2_BASE		(ISH_UART_BASE + UART2_OFFS)
-#define UART2_SIZE		(0x80)
 
 #define UART_REG(size, name, n)					\
 	REG##size(uart_ctx[n].base +					\
@@ -33,22 +35,140 @@
 /* Register accesses */
 #define LSR(n)			UART_REG(8, LSR, n)
 #define THR(n)			UART_REG(8, THR, n)
-#define FOR(n)			UART_REG(32, FOR, n)
 #define RBR(n)			UART_REG(8, RBR, n)
 #define DLL(n)			UART_REG(8, DLL, n)
 #define DLH(n)			UART_REG(8, DLH, n)
-#define DLD(n)			UART_REG(8, DLD, n)
 #define IER(n)			UART_REG(8, IER, n)
 #define IIR(n)			UART_REG(8, IIR, n)
 #define FCR(n)			UART_REG(8, FCR, n)
 #define LCR(n)			UART_REG(8, LCR, n)
 #define MCR(n)			UART_REG(8, MCR, n)
 #define MSR(n)			UART_REG(8, MSR, n)
+#define DLF(n)			UART_REG(8, DLF, n)
+#define FOR(n)			UART_REG(32, FOR, n)
 #define ABR(n)			UART_REG(32, ABR, n)
 #define PS(n)			UART_REG(32, PS, n)
 #define MUL(n)			UART_REG(32, MUL, n)
 #define DIV(n)			UART_REG(32, DIV, n)
 
+#ifdef CONFIG_ISH_DW_UART
+/*
+ * RBR: Receive Buffer register     (BLAB bit = 0)
+ */
+#define UART_OFFSET_RBR		(0x00)
+
+/*
+ * THR: Transmit Holding register   (BLAB bit = 0)
+ */
+#define UART_OFFSET_THR		(0x00)
+
+/*
+ * DLL: Divisor Latch Reg. low byte  (BLAB bit = 1)
+ * baud rate = (serial clock freq) / (16 * divisor)
+ */
+#define UART_OFFSET_DLL		(0x00)
+
+/*
+ * DLH: Divisor Latch Reg. high byte (BLAB bit = 1)
+ */
+#define UART_OFFSET_DLH		(0x04)
+
+/*
+ * IER: Interrupt Enable register   (BLAB bit = 0)
+ */
+#define UART_OFFSET_IER		(0x04)
+
+#define IER_RECV		(0x01)  /* Receive Data Available */
+#define IER_TDRQ		(0x02)  /* Transmit Holding Register Empty */
+#define IER_LINE_STAT		(0x04)  /* Receiver Line Status */
+#define IER_MODEM		(0x08)  /* Modem Status */
+#define IER_PTIME		(0x80)  /* Programmable THRE Interrupt Mode Enable */
+
+/*
+ * IIR: Interrupt ID register
+ */
+#define UART_OFFSET_IIR		(0x08)
+
+#define IIR_MODEM		(0x00)  /* Prio: 4 */
+#define IIR_NO_INTR		(0x01)
+#define IIR_THRE		(0x02)  /* Prio: 3 */
+#define IIR_RECV_DATA		(0x04)  /* Prio: 2 */
+#define IIR_LINE_STAT		(0x06)  /* Prio: 1 */
+#define IIR_BUSY		(0x07)  /* Prio: 5 */
+#define IIR_TIME_OUT		(0x0C)  /* Prio: 2 */
+#define IIR_SOURCE		(0x0F)
+
+
+/*
+ * FCR: FIFO Control register (FIFO_MODE != NONE)
+ */
+#define UART_OFFSET_FCR		(0x08)
+
+#define FIFO_SIZE		64
+#define FCR_FIFO_ENABLE		(0x01)
+#define FCR_RESET_RX		(0x02)
+#define FCR_RESET_TX		(0x04)
+#define FCR_DMA_MODE		(0x08)
+
+/*
+ * LCR: Line Control register
+ */
+#define UART_OFFSET_LCR		(0x0c)
+
+#define LCR_5BIT_CHR		(0x00)
+#define LCR_6BIT_CHR		(0x01)
+#define LCR_7BIT_CHR		(0x02)
+#define LCR_8BIT_CHR		(0x03)
+#define LCR_BIT_CHR_MASK	(0x03)
+
+#define LCR_STOP		BIT(2)  /* 0: 1 stop bit, 1: 1.5/2 */
+#define LCR_PEN			BIT(3)  /* Parity Enable */
+#define LCR_EPS			BIT(4)  /* Even Parity Select */
+#define LCR_SP			BIT(5)  /* Stick Parity */
+#define LCR_BC			BIT(6)  /* Break Control */
+#define LCR_DLAB		BIT(7)  /* Divisor Latch Access */
+
+/*
+ * MCR: Modem Control register
+ */
+#define UART_OFFSET_MCR		(0x10)
+#define MCR_DTR			(0x1)     /* Data terminal ready */
+#define MCR_RTS			(0x2)     /* Request to send */
+#define MCR_LOOP		(0x10)    /* LoopBack bit*/
+
+#define MCR_INTR_ENABLE		(0x08)    /* User-designated OUT2 */
+#define MCR_AUTO_FLOW_EN	(0x20)
+
+/*
+ * LSR: Line Status register
+ */
+#define UART_OFFSET_LSR		(0x14)
+
+#define LSR_DR			(0x01)         /* Data Ready */
+#define LSR_OE			(0x02)         /* Overrun error */
+#define LSR_PE			(0x04)         /* Parity error */
+#define LSR_FE			(0x08)         /* Framing error */
+#define LSR_BI			(0x10)         /* Breaking interrupt */
+#define LSR_TDRQ		(0x20)       /* Transmit Holding Register Empty */
+#define LSR_TEMT		(0x40)       /* Transmitter empty */
+
+/*
+ * MSR: Modem Status register
+ */
+#define UART_OFFSET_MSR		(0x18)
+
+#define MSR_CTS			BIT(4) /* Clear To Send signal */
+
+/*
+ * TFL: Transmit FIFO Level
+ */
+#define UART_OFFSET_TFL		(0x80)
+
+/*
+ * RFL: Receive FIFO Level
+ */
+#define UART_OFFSET_RFL		(0x84)
+#else
 /* RBR: Receive Buffer register     (BLAB bit = 0)  */
 #define UART_OFFSET_RBR	(0)
 /* THR: Transmit Holding register   (BLAB bit = 0)  */
@@ -56,10 +176,6 @@
 /* IER: Interrupt Enable register   (BLAB bit = 0)  */
 #define UART_OFFSET_IER	(1)
 
-#define FCR_FIFO_SIZE_16	(0x00)
-#define FCR_FIFO_SIZE_64	(0x20)
-#define FCR_ITL_FIFO_64_BYTES_1 (0x00)
-
 /* FCR: FIFO Control register */
 #define UART_OFFSET_FCR	(2)
 #define FCR_FIFO_ENABLE	BIT(0)
@@ -112,9 +228,12 @@
 
 /* DLH: Divisor Latch Reg. high byte (BLAB bit = 1) */
 #define UART_OFFSET_DLH	(1)
+#endif
 
-/* DLH: Divisor Latch Fractional. (BLAB bit = 1) */
-#define UART_OFFSET_DLD	(2)
+/*
+ * DLF: Divisor Latch Fraction Register
+ */
+#define UART_OFFSET_DLF		(0xC0)
 
 /* FOR: Fifo O Register (ISH only) */
 #define UART_OFFSET_FOR	(0x20)
@@ -132,6 +251,22 @@
 #define UART_OFFSET_MUL	(0x34)
 #define UART_OFFSET_DIV	(0x38)
 
+#define FCR_FIFO_SIZE_16	(0x00)
+#define FCR_FIFO_SIZE_64	(0x20)
+#define FCR_ITL_FIFO_64_BYTES_1	(0x00)
+
+/* tx empty trigger(TET) */
+#define FCR_TET_EMPTY		(0x00)
+#define FCR_TET_2CHAR		(0x10)
+#define FCR_TET_QTR_FULL	(0x20)
+#define FCR_TET_HALF_FULL	(0x30)
+
+/* receive trigger(RT) */
+#define FCR_RT_1CHAR		(0x00)
+#define FCR_RT_QTR_FULL		(0x40)
+#define FCR_RT_HALF_FULL	(0x80)
+#define FCR_RT_2LESS_FULL	(0xc0)
+
 /* G_IEN: Global Interrupt Enable  (ISH only) */
 #define HSU_REG_GIEN		REG32(HSU_BASE + 0x0)
 #define HSU_REG_GIST		REG32(HSU_BASE + 0x4)
@@ -185,7 +320,10 @@
 /* KHZ, MHZ */
 #define KHZ(x)				((x) * 1000)
 #define MHZ(x)				(KHZ(x) * 1000)
-#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
+#if defined(CHIP_VARIANT_ISH5P4)
+/* Change to 100MHZ in real silicon platform */
+#define UART_ISH_INPUT_FREQ		MHZ(100)
+#elif defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
 #define UART_ISH_INPUT_FREQ		MHZ(120)
 #elif defined(CHIP_FAMILY_ISH4)
 #define UART_ISH_INPUT_FREQ		MHZ(100)
diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c
index 58db2bee27..714fde239e 100644
--- a/core/minute-ia/interrupts.c
+++ b/core/minute-ia/interrupts.c
@@ -145,11 +145,13 @@ static const irq_desc_t system_irqs[] = {
 	LEVEL_INTR(ISH_WDT_IRQ, ISH_WDT_VEC),
 	LEVEL_INTR(ISH_GPIO_IRQ, ISH_GPIO_VEC),
 	LEVEL_INTR(ISH_IPC_HOST2ISH_IRQ, ISH_IPC_VEC),
+#ifndef CONFIG_ISH_HOST2ISH_COMBINED_ISR
 	LEVEL_INTR(ISH_IPC_ISH2HOST_CLR_IRQ, ISH_IPC_ISH2HOST_CLR_VEC),
+#endif
 	LEVEL_INTR(ISH_HPET_TIMER1_IRQ, ISH_HPET_TIMER1_VEC),
 	LEVEL_INTR(ISH_DEBUG_UART_IRQ, ISH_DEBUG_UART_VEC),
 	LEVEL_INTR(ISH_FABRIC_IRQ, ISH_FABRIC_VEC),
-#ifdef CONFIG_ISH_PM_RESET_PREP
+#if defined(CONFIG_ISH_PM_RESET_PREP) || defined(CHIP_VARIANT_ISH5P4)
 	LEVEL_INTR(ISH_RESET_PREP_IRQ, ISH_RESET_PREP_VEC),
 #endif
 #ifdef CONFIG_ISH_PM_D0I1
diff --git a/include/config.h b/include/config.h
index 3a2c197a89..64b3ca064c 100644
--- a/include/config.h
+++ b/include/config.h
@@ -4339,6 +4339,22 @@
 #undef CONFIG_ISH_PM_RESET_PREP
 
 /*
+ * Define the following if combined ISR is required for ipc communication
+ * between host and ISH.
+ */
+#undef CONFIG_ISH_HOST2ISH_COMBINED_ISR
+
+/*
+ * Define the following if there is need to clear ISH fabric error.
+ */
+#undef CONFIG_ISH_CLEAR_FABRIC_ERRORS
+
+/*
+ * Define the following if the version of ISH uses Synopsys Designware uart.
+ */
+#undef CONFIG_ISH_DW_UART
+
+/*
  * On Intel devices EC's USB-C port numbers may not be physically equal to
  * AP's USB3 & USB2 port number. Because there can be MAX 15 USB2 ports on
  * PCH and MAX 15 USB3 ports on SOC, based on the complexity of the physical