diff options
| author | Yilun Lin <yllin@google.com> | 2018-12-12 19:48:40 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-23 14:46:08 -0800 |
| commit | eabd415de887b2a2a75e73bf4d6df49ded03c917 (patch) | |
| tree | c7859acf7618941a9551208cf1961bde83582d43 | |
| parent | 216ab1e1d8d74bc722d3e322b2460802e93a5df9 (diff) | |
| download | chrome-ec-eabd415de887b2a2a75e73bf4d6df49ded03c917.tar.gz | |
mt_scp: Support SCP reset stepping stone function.
SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m
resetting, it would load 0x0 to SP(r13) and load 0x04 to PC(r15).
Stepping stones copy these two very special values from CONFIG_RAM_BASE,
CONFIG_RAM_BASE + 0x04 to 0x0, 0x4 resepctively.
TEST=make BOARD=kukui_scp -j, and see the value from 0x0, 0x4 in
kukui_scp/RW/ec.RW.flat are the same as 0x800, 0x804 respectively.
TEST=Puts ec.RW.bin on kukui and see that SCP boots.
BUG=b:120825336
BRANCH=None
Change-Id: I71670d5d4b5ba3aaad17c264a2a3bc3076703a9c
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1373950
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | chip/mt_scp/build.mk | 2 | ||||
| -rw-r--r-- | chip/mt_scp/config_chip.h | 4 | ||||
| -rw-r--r-- | chip/mt_scp/memory_regions.inc | 1 | ||||
| -rw-r--r-- | chip/mt_scp/stepping_stone.c | 22 |
4 files changed, 28 insertions, 1 deletions
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk index eb261fbd90..5729de35a7 100644 --- a/chip/mt_scp/build.mk +++ b/chip/mt_scp/build.mk @@ -10,7 +10,7 @@ CORE:=cortex-m CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 # Required chip modules -chip-y=clock.o gpio.o system.o uart.o +chip-y=clock.o gpio.o stepping_stone.o system.o uart.o # Optional chip modules chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h index fb303fe815..2f982246b2 100644 --- a/chip/mt_scp/config_chip.h +++ b/chip/mt_scp/config_chip.h @@ -27,6 +27,9 @@ /* RW only, no flash * +-------------------- 0x0 + * | ptr to stack_top 0x0 + * | ptr to reset func 0x04 + * |-------------------- 0x08 * | free shared space with AP * +-------------------- 0x005B0 * | IPI shared buffer with AP (288 + 8) * 2 @@ -53,6 +56,7 @@ #define CONFIG_RW_STORAGE_OFF 0 #define CONFIG_PROGRAM_MEMORY_BASE 0 #define CONFIG_MAPPED_STORAGE_BASE 0 +#define CONFIG_CHIP_MEMORY_REGIONS /* Unsupported features/commands */ #undef CONFIG_CMD_FLASHINFO diff --git a/chip/mt_scp/memory_regions.inc b/chip/mt_scp/memory_regions.inc new file mode 100644 index 0000000000..e87df4c51d --- /dev/null +++ b/chip/mt_scp/memory_regions.inc @@ -0,0 +1 @@ +REGION_LOAD(stepping_stone, rwx, 0x00000, 0x8) diff --git a/chip/mt_scp/stepping_stone.c b/chip/mt_scp/stepping_stone.c new file mode 100644 index 0000000000..240f2ea2b1 --- /dev/null +++ b/chip/mt_scp/stepping_stone.c @@ -0,0 +1,22 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * mt_scp Stepping Stone functions on CPU reset. + * + * SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m resetting, + * it would load 0x0 to SP(r13) and load 0x04 to PC(r15). Stepping stones copy + * these two very special values from CONFIG_RAM_BASE, CONFIG_RAM_BASE + 0x04 + * to 0x0, 0x4 resepctively. + */ + +#include "common.h" +#include "link_defs.h" + +extern void *stack_end; +extern void reset(void); + +__SECTION_KEEP(stepping_stone) const void *ss_header[2] = { + &stack_end, + &reset +}; |