Code cleanup: Remove cold reset logic

Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j
     Manually tested on GLKRVP, apreset EC command can reset AP.

Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>

19 files changed, 66 insertions, 143 deletions

diff --git a/board/host/chipset.c b/board/host/chipset.c
index 678d5a97e0..62e7151e06 100644
--- a/board/host/chipset.c
+++ b/board/host/chipset.c
@@ -16,7 +16,7 @@ static int chipset_state = CHIPSET_STATE_SOFT_OFF;
 static int power_on_req;
 static int power_off_req;
 
-test_mockable void chipset_reset(int cold_reset)
+test_mockable void chipset_reset(void)
 {
 	fprintf(stderr, "Chipset reset!\n");
 }
diff --git a/board/kevin/board.c b/board/kevin/board.c
index 1ec3e6bf1e..71bc55243b 100644
--- a/board/kevin/board.c
+++ b/board/kevin/board.c
@@ -68,7 +68,7 @@ static void overtemp_interrupt(enum gpio_signal signal)
 static void warm_reset_request_interrupt(enum gpio_signal signal)
 {
 	CPRINTS("AP wants warm reset");
-	chipset_reset(0);
+	chipset_reset();
 }
 
 #include "gpio_list.h"
diff --git a/board/oak/board.c b/board/oak/board.c
index d949194907..a9f05c4e86 100644
--- a/board/oak/board.c
+++ b/board/oak/board.c
@@ -426,7 +426,7 @@ static void check_ap_reset_second(void)
 		return;
 
 	if (warm_reset)
-		chipset_reset(0); /* Warm reset AP */
+		chipset_reset(); /* Warm reset AP */
 
 	last = warm_reset;
 }
diff --git a/board/rainier/board.c b/board/rainier/board.c
index c173b2f427..e0831301ce 100644
--- a/board/rainier/board.c
+++ b/board/rainier/board.c
@@ -61,7 +61,7 @@ static void overtemp_interrupt(enum gpio_signal signal)
 static void warm_reset_request_interrupt(enum gpio_signal signal)
 {
 	CPRINTS("AP wants warm reset");
-	chipset_reset(0);
+	chipset_reset();
 }
 
 #include "gpio_list.h"
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c
index cac9647a44..804d3ef208 100644
--- a/board/samus/power_sequence.c
+++ b/board/samus/power_sequence.c
@@ -111,41 +111,22 @@ static void chipset_reset_rtc(void)
 	udelay(10 * MSEC);
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_PWROK, 1);
+	CPRINTS("%s", __func__);
 
-	} else {
-		/*
-		 * Send a RCIN# pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.
-		 */
+	/*
+	 * Send a RCIN# pulse to the PCH.  This just causes it to
+	 * assert INIT# to the CPU without dropping power or asserting
+	 * PLTRST# to reset the rest of the system.
+	 */
 
-		/*
-		 * Pulse must be at least 16 PCI clocks long = 500 ns.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		udelay(10);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Pulse must be at least 16 PCI clocks long = 500 ns.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	udelay(10);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)
diff --git a/board/scarlet/board.c b/board/scarlet/board.c
index 21b2424ea1..fb40b6d0cf 100644
--- a/board/scarlet/board.c
+++ b/board/scarlet/board.c
@@ -63,7 +63,7 @@ static void overtemp_interrupt(enum gpio_signal signal)
 static void warm_reset_request_interrupt(enum gpio_signal signal)
 {
 	CPRINTS("AP wants warm reset");
-	chipset_reset(0);
+	chipset_reset();
 }
 
 #include "gpio_list.h"
diff --git a/common/ap_hang_detect.c b/common/ap_hang_detect.c
index b5098e15b2..45e735e526 100644
--- a/common/ap_hang_detect.c
+++ b/common/ap_hang_detect.c
@@ -41,7 +41,7 @@ static void hang_detect_deferred(void)
 	if (timeout_will_reboot) {
 		CPRINTS("hang detect triggering warm reboot");
 		host_set_single_event(EC_HOST_EVENT_HANG_REBOOT);
-		chipset_reset(0);
+		chipset_reset();
 		active = 0;
 		return;
 	}
diff --git a/common/button.c b/common/button.c
index 5a48c8842e..6190f414bb 100644
--- a/common/button.c
+++ b/common/button.c
@@ -416,7 +416,7 @@ static void debug_mode_handle(void)
 			host_send_sysrq('x');
 			CPRINTS("DEBUG MODE: sysrq-x sent");
 		} else {
-			chipset_reset(0);
+			chipset_reset();
 			CPRINTS("DEBUG MODE: Warm reset triggered");
 		}
 		recovery_button_pressed = 0;
@@ -531,7 +531,7 @@ static void debug_mode_transition(enum debug_state next_state)
 		break;
 	case STATE_WARM_RESET_EXEC:
 		/* Warm reset the host and transition to STATE_NONE. */
-		chipset_reset(0);
+		chipset_reset();
 		CPRINTS("DEBUG MODE: Warm reset triggered");
 		curr_debug_state = STATE_DEBUG_NONE;
 		break;
diff --git a/common/chipset.c b/common/chipset.c
index 1d236fdc14..7a2101624a 100644
--- a/common/chipset.c
+++ b/common/chipset.c
@@ -20,20 +20,13 @@
 #ifdef CONFIG_CMD_POWER_AP
 static int command_apreset(int argc, char **argv)
 {
-	int is_cold = 1;
-
-	if (argc > 1 && !strcasecmp(argv[1], "cold"))
-		is_cold = 1;
-	else if (argc > 1 && !strcasecmp(argv[1], "warm"))
-		is_cold = 0;
-
 	/* Force the chipset to reset */
-	ccprintf("Issuing AP %s reset...\n", is_cold ? "cold" : "warm");
-	chipset_reset(is_cold);
+	ccprintf("Issuing AP reset...\n");
+	chipset_reset();
 	return EC_SUCCESS;
 }
 DECLARE_CONSOLE_COMMAND(apreset, command_apreset,
-			"[warm | cold]",
+			NULL,
 			"Issue AP reset");
 
 static int command_apshutdown(int argc, char **argv)
diff --git a/common/keyboard_8042.c b/common/keyboard_8042.c
index 3e1836a518..b18be07649 100644
--- a/common/keyboard_8042.c
+++ b/common/keyboard_8042.c
@@ -729,7 +729,7 @@ static int handle_keyboard_command(uint8_t command, uint8_t *output)
 		break;
 
 	case I8042_SYSTEM_RESET:
-		chipset_reset(0);
+		chipset_reset();
 		break;
 
 	default:
diff --git a/common/keyboard_scan.c b/common/keyboard_scan.c
index 34474917b3..e63c164100 100644
--- a/common/keyboard_scan.c
+++ b/common/keyboard_scan.c
@@ -358,7 +358,7 @@ static int check_runtime_keys(const uint8_t *state)
 		/* R = reboot */
 		CPRINTS("KB warm reboot");
 		keyboard_clear_buffer();
-		chipset_reset(0);
+		chipset_reset();
 		return 1;
 	} else if (state[KEYBOARD_COL_KEY_H] == KEYBOARD_MASK_KEY_H) {
 		/* H = hibernate */
diff --git a/include/chipset.h b/include/chipset.h
index c48eb733b8..775428ed9f 100644
--- a/include/chipset.h
+++ b/include/chipset.h
@@ -74,11 +74,8 @@ void chipset_force_shutdown(void);
 
 /**
  * Reset the CPU and/or chipset.
- *
- * @param cold_reset	If !=0, force a cold reset of the CPU and chipset;
- *			if 0, just pulse the reset line to the CPU.
  */
-void chipset_reset(int cold_reset);
+void chipset_reset(void);
 
 /**
  * Interrupt handler to power GPIO inputs.
@@ -101,7 +98,7 @@ static inline int chipset_in_state(int state_mask)
 static inline void chipset_exit_hard_off(void) { }
 static inline void chipset_throttle_cpu(int throttle) { }
 static inline void chipset_force_shutdown(void) { }
-static inline void chipset_reset(int cold_reset) { }
+static inline void chipset_reset(void) { }
 static inline void power_interrupt(enum gpio_signal signal) { }
 static inline void chipset_handle_espi_reset_assert(void) { }
 static inline void chipset_handle_reboot(void) { }
diff --git a/power/braswell.c b/power/braswell.c
index bfdf3dec39..0b91040cbc 100644
--- a/power/braswell.c
+++ b/power/braswell.c
@@ -68,38 +68,19 @@ void chipset_force_shutdown(void)
 	forcing_shutdown = 1;
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
-	if (cold_reset) {
-		/*
-		 * Drop and restore PWROK.  This causes the PCH to reboot,
-		 * regardless of its after-G3 setting.  This type of reboot
-		 * causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
-		 * we actually drop power to the rest of the system (hence, a
-		 * "cold" reboot).
-		 */
-
-		/* Ignore if PWROK is already low */
-		if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0)
-			return;
-
-		/* PWROK must deassert for at least 3 RTC clocks = 91 us */
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
-		udelay(100);
-		gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
+	CPRINTS("%s", __func__);
 
-	} else {
-		/*
-		 * Send a reset pulse to the PCH.  This just causes it to
-		 * assert INIT# to the CPU without dropping power or asserting
-		 * PLTRST# to reset the rest of the system.  The PCH uses a 16
-		 * ms debounce time, so assert the signal for twice that.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Send a reset pulse to the PCH.  This just causes it to
+	 * assert INIT# to the CPU without dropping power or asserting
+	 * PLTRST# to reset the rest of the system.  The PCH uses a 16
+	 * ms debounce time, so assert the signal for twice that.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 73cac45613..bc58d26711 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -510,7 +510,7 @@ void power_chipset_handle_host_sleep_event(enum host_sleep_event state)
 
 #endif
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
 	/*
 	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
diff --git a/power/mediatek.c b/power/mediatek.c
index 7ac9143803..e5bfe37e66 100644
--- a/power/mediatek.c
+++ b/power/mediatek.c
@@ -418,7 +418,7 @@ enum power_state power_chipset_init(void)
 		 * The warm reset triggers AP into the recovery mode (
 		 * flash SPI from USB).
 		 */
-		chipset_reset(0);
+		chipset_reset();
 
 		init_power_state = POWER_G3;
 	} else {
@@ -638,23 +638,13 @@ static void power_on(void)
 	CPRINTS("AP running ...");
 }
 
-void chipset_reset(int is_cold)
+void chipset_reset(void)
 {
-	if (is_cold) {
-		CPRINTS("EC triggered cold reboot");
-		set_system_power(0);
-		usleep(PMIC_COLD_RESET_L_HOLD_TIME);
-		/* Press the PMIC power button */
-		set_pmic_pwron(1);
-		hook_call_deferred(&release_pmic_pwron_deferred_data,
-				   PMIC_PWRON_PRESS_TIME);
-	} else {
-		CPRINTS("EC triggered warm reboot");
-		set_warm_reset(1);
-		usleep(PMIC_WARM_RESET_H_HOLD_TIME);
-		/* deassert the reset signals */
-		set_warm_reset(0);
-	}
+	CPRINTS("EC triggered warm reboot");
+	set_warm_reset(1);
+	usleep(PMIC_WARM_RESET_H_HOLD_TIME);
+	/* deassert the reset signals */
+	set_warm_reset(0);
 }
 
 enum power_state power_handle_state(enum power_state state)
diff --git a/power/rk3399.c b/power/rk3399.c
index 51211d0c69..2c8a5e9e96 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -220,14 +220,13 @@ void chipset_force_shutdown(void)
 }
 
 #define SYS_RST_HOLD_US (1 * MSEC)
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
 #ifdef CONFIG_CMD_RTC
 	/* Print out the RTC to help correlate resets in logs. */
 	print_system_rtc(CC_CHIPSET);
 #endif
-	/* TODO: handle cold_reset */
-	CPRINTS("%s(%d)", __func__, cold_reset);
+	CPRINTS("%s", __func__);
 
 	/* Pulse SYS_RST */
 	gpio_set_level(GPIO_SYS_RST_L, 0);
diff --git a/power/rockchip.c b/power/rockchip.c
index eb33d3e91e..22ec8eff5b 100644
--- a/power/rockchip.c
+++ b/power/rockchip.c
@@ -223,7 +223,7 @@ enum power_state power_chipset_init(void)
 		 * The warm reset triggers AP into the RK recovery mode (
 		 * flash SPI from USB).
 		 */
-		chipset_reset(0);
+		chipset_reset();
 
 		init_power_state = POWER_G3;
 	} else {
@@ -380,23 +380,14 @@ static void power_off(void)
 	CPRINTS("power shutdown complete");
 }
 
-void chipset_reset(int is_cold)
+void chipset_reset(void)
 {
-	if (is_cold) {
-		CPRINTS("EC triggered cold reboot");
-		power_off();
-		/* After POWER_GOOD is dropped off,
-		 * the system will be on again
-		 */
-		power_request = POWER_REQ_ON;
-	} else {
-		CPRINTS("EC triggered warm reboot");
-		CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
-				PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
-		set_pmic_warm_reset(1);
-		usleep(PMIC_WARM_RESET_L_HOLD_TIME);
-		set_pmic_warm_reset(0);
-	}
+	CPRINTS("EC triggered warm reboot");
+	CPRINTS("assert GPIO_PMIC_WARM_RESET_L for %d ms",
+			PMIC_WARM_RESET_L_HOLD_TIME / MSEC);
+	set_pmic_warm_reset(1);
+	usleep(PMIC_WARM_RESET_L_HOLD_TIME);
+	set_pmic_warm_reset(0);
 }
 
 enum power_state power_handle_state(enum power_state state)
diff --git a/power/stoney.c b/power/stoney.c
index 936ae21a65..a3c6467dd7 100644
--- a/power/stoney.c
+++ b/power/stoney.c
@@ -52,30 +52,21 @@ static void chipset_force_g3(void)
 #endif
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
-	CPRINTS("%s(%d)", __func__, cold_reset);
+	CPRINTS("%s", __func__);
 
 	if (chipset_in_state(CHIPSET_STATE_ANY_OFF)) {
 		CPRINTS("Can't reset: SOC is off");
 		return;
 	}
 
-	if (cold_reset) {
-		/*
-		 * Perform chipset_force_shutdown and mark forcing_coldreset.
-		 * Once in S5G3 state, check forcing_coldreset to power up.
-		 */
-		forcing_coldreset = 1;
-		chipset_force_shutdown();
-	} else {
-		/*
-		 * Send a pulse to SYS_RST to trigger a warm reset.
-		 */
-		gpio_set_level(GPIO_PCH_RCIN_L, 0);
-		usleep(32 * MSEC);
-		gpio_set_level(GPIO_PCH_RCIN_L, 1);
-	}
+	/*
+	 * Send a pulse to SYS_RST to trigger a warm reset.
+	 */
+	gpio_set_level(GPIO_PCH_RCIN_L, 0);
+	usleep(32 * MSEC);
+	gpio_set_level(GPIO_PCH_RCIN_L, 1);
 }
 
 void chipset_throttle_cpu(int throttle)
diff --git a/test/kb_scan.c b/test/kb_scan.c
index b9dd661224..75ee1932ed 100644
--- a/test/kb_scan.c
+++ b/test/kb_scan.c
@@ -80,7 +80,7 @@ void system_hibernate(uint32_t s, uint32_t us)
 	hibernated = 1;
 }
 
-void chipset_reset(int cold_reset)
+void chipset_reset(void)
 {
 	reset_called = 1;
 }