diff options
| author | Wai-Hong Tam <waihong@google.com> | 2018-10-24 09:58:12 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-31 12:42:23 -0700 |
| commit | 0e5ddce1cc88812c380ad748be30302aa4bdaad4 (patch) | |
| tree | de0f43a2aeec00257710ba276f0e4b41f9185f8a | |
| parent | 2d9fe8c8912baf237c7eff6964cc68cf8554669c (diff) | |
| download | chrome-ec-0e5ddce1cc88812c380ad748be30302aa4bdaad4.tar.gz | |
cheza: Remove the unnecessary GPIO_SEL_1P8V flags
The GPIOs which are powered by VHIF/VSPI are already operating at 1.8V.
Don't need to configure them.
Powered by VHIF:
GPIO54: POWER_GOOD
GPIO53: SHI_CS_L
GPIO57: AP_SUSPEND_L
Powered by VSPI:
GPIOA0: USB_C0_PD_INT_ODL
GPIOA2: EC_INT_L
BRANCH=none
BUG=b:118336977
TEST=Verified AP power-on and power-off sequence, host command, port-0
plug and unplug for PD communication.
Change-Id: I6369a6d8d343e4d8d5c33fef0f971e5cb09622ec
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1298366
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
| -rw-r--r-- | board/cheza/gpio.inc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/cheza/gpio.inc b/board/cheza/gpio.inc index 3ba7840340..2270f25231 100644 --- a/board/cheza/gpio.inc +++ b/board/cheza/gpio.inc @@ -9,7 +9,7 @@ * Note: Those with interrupt handlers must be declared first. */ /* USB-C interrupts */ -GPIO_INT(USB_C0_PD_INT_ODL, PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, tcpc_alert_event) /* Interrupt from port-0 TCPC */ +GPIO_INT(USB_C0_PD_INT_ODL, PIN(A, 0), GPIO_INT_FALLING, tcpc_alert_event) /* Interrupt from port-0 TCPC */ GPIO_INT(USB_C1_PD_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event) /* Interrupt from port-1 TCPC */ GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt) /* Interrupt from port-0 PPC */ GPIO_INT(USB_C0_BC12_INT_L, PIN(6, 1), GPIO_INT_FALLING, usb0_evt) /* Interrupt from port-0 BC1.2 */ @@ -36,9 +36,9 @@ GPIO_INT(PMIC_FAULT_L, PIN(7, 6), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_sign * for not only signalling power_signal_interrupt but also handling the logic * of WARM_RESET_L which is pulled-up by the same rail of POWER_GOOD. */ -GPIO_INT(POWER_GOOD, PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL_1P8V, chipset_warm_reset_interrupt) /* SRC_PP1800_S4A from PMIC */ +GPIO_INT(POWER_GOOD, PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_warm_reset_interrupt) /* SRC_PP1800_S4A from PMIC */ GPIO_INT(WARM_RESET_L, PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt) /* AP warm reset */ -GPIO_INT(SHI_CS_L, PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN | GPIO_SEL_1P8V, shi_cs_event) /* AP_EC_SPI_CS_L */ +GPIO_INT(SHI_CS_L, PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event) /* AP_EC_SPI_CS_L */ GPIO_INT(CC_LID_BASE_ADC, PIN(4, 5), GPIO_INT_BOTH, base_detect_interrupt) /* Base detection */ /* @@ -60,8 +60,8 @@ GPIO(PROCHOT_L, PIN(3, 4), GPIO_INPUT) /* PMIC/AP 1.8V */ GPIO(PM845_RESIN_L, PIN(3, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* PMIC reset trigger */ GPIO(PMIC_KPD_PWR_ODL, PIN(D, 6), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* PMIC power button */ -GPIO(EC_INT_L, PIN(A, 2), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* Interrupt line between AP and EC */ -GPIO(AP_SUSPEND_L, PIN(5, 7), GPIO_INPUT | GPIO_SEL_1P8V) /* Suspend signal from AP */ +GPIO(EC_INT_L, PIN(A, 2), GPIO_ODR_HIGH) /* Interrupt line between AP and EC */ +GPIO(AP_SUSPEND_L, PIN(5, 7), GPIO_INPUT) /* Suspend signal from AP */ /* Power enables */ GPIO(SWITCHCAP_ON_L, PIN(D, 5), GPIO_OUT_LOW) /* Enable switch cap. XXX: It's active-high */ |