cheza: Reenable EC hibernate

This CL requires hardware rework or a new hardware revision, which
 * blocks the current drop to VCC1_RST pin;
 * makes the lid open and power button signals pulled-up by the EC
   standby rail.

BRANCH=none
BUG=b:79348203
TEST=Typed "hibernate" command on EC console and checked waking EC
up using the 4 wake sources:
 * dut-control lid_open:no sleep:0.2 lid_open:yes
 * Unplug and plug the AC charger
 * dut-control pwr_button:press sleep:0.2 pwr_button:release
 * dut-control cold_reset:on sleep:0.2 cold_reset:off

Change-Id: Iccc33e3df621da319d422942eda1ec9f01a4fd67
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1123157
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>

3 files changed, 28 insertions, 5 deletions

diff --git a/board/cheza/board.c b/board/cheza/board.c
index b2b323eefd..173b97fb85 100644
--- a/board/cheza/board.c
+++ b/board/cheza/board.c
@@ -115,6 +115,15 @@ static void ppc_interrupt(enum gpio_signal signal)
 	sn5s330_interrupt(0);
 }
 
+/* Wake-up pins for hibernate */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+	GPIO_EC_RST_ODL,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
 /* ADC channels */
 const struct adc_t adc_channels[] = {
 	/* Base detection */
diff --git a/board/cheza/board.h b/board/cheza/board.h
index c483528b8a..ce83a439b6 100644
--- a/board/cheza/board.h
+++ b/board/cheza/board.h
@@ -149,8 +149,8 @@
 #define CONFIG_POWER_COMMON
 #define CONFIG_POWER_PP5000_CONTROL
 
-/* TODO(b/79348203): Enable EC hibernate */
-#undef CONFIG_HIBERNATE
+/* NPCX Features */
+#define CONFIG_HIBERNATE_PSL
 
 /* I2C Ports */
 #define I2C_PORT_BATTERY I2C_PORT_POWER
diff --git a/board/cheza/gpio.inc b/board/cheza/gpio.inc
index 863ee9d91e..49dbfdc008 100644
--- a/board/cheza/gpio.inc
+++ b/board/cheza/gpio.inc
@@ -20,12 +20,12 @@ GPIO_INT(USB_C0_CABLE_DET,     PIN(3, 7), GPIO_INT_RISING, anx74xx_cable_det_int
 GPIO_INT(ACCEL_GYRO_INT_L,     PIN(D, 3), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt)  /* Accelerometer/gyro interrupt */
 
 /* System interrupts */
-GPIO_INT(AC_PRESENT,        PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD */
+GPIO_INT(AC_PRESENT,        PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* ACOK_OD */
 GPIO_INT(POWER_BUTTON_L,    PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt)  /* EC_PWR_BTN_ODL */
 GPIO_INT(VOLUME_DOWN_L,     PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLDN_BTN_ODL */
 GPIO_INT(VOLUME_UP_L,       PIN(F, 2), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)  /* EC_VOLUP_BTN_ODL */
 GPIO_INT(WP_L,              PIN(A, 1), GPIO_INT_BOTH, switch_interrupt)  /* EC_WP_ODL */
-GPIO_INT(LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH, lid_interrupt)  /* LID_OPEN_EC */
+GPIO_INT(LID_OPEN,          PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt)  /* LID_OPEN_EC */
 GPIO_INT(AP_RST_REQ,        PIN(C, 2), GPIO_INT_RISING | GPIO_PULL_DOWN | GPIO_SEL_1P8V, chipset_reset_request_interrupt)  /* Reset request from AP */
 /* AP_RST_L and PS_HOLD are used for PMIC and AP negotiation. Don't change their states. */
 GPIO_INT(AP_RST_L,          PIN(C, 1), GPIO_INT_BOTH | GPIO_SEL_1P8V, power_signal_interrupt)
@@ -36,7 +36,17 @@ GPIO_INT(POWER_GOOD,        PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN | GPIO_SEL
 GPIO_INT(SHI_CS_L,          PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN | GPIO_SEL_1P8V, shi_cs_event)  /* AP_EC_SPI_CS_L */
 GPIO_INT(CC_LID_BASE_ADC,   PIN(4, 5), GPIO_INT_BOTH, base_detect_interrupt)  /* Base detection */
 
-GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INPUT)     /* Wake source: EC reset */
+/*
+ * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does
+ * not need to be an interrupt for normal EC operations. Thus, configure it as
+ * GPIO_INT_BOTH with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that
+ * PSL common code can configure PSL_IN correctly.
+ *
+ * Use the rising edge to wake EC up. If we chose the falling edge, it would
+ * still wake EC up, but EC is in an intermediate state until the signal goes
+ * back to high.
+ */
+GPIO(EC_RST_ODL,            PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)  /* Wake source: EC reset */
 GPIO(ENTERING_RW,           PIN(E, 1), GPIO_OUT_LOW)   /* EC_ENTERING_RW: Indicate when EC is entering RW code */
 GPIO(CCD_MODE_ODL,          PIN(E, 3), GPIO_INPUT)     /* Case Closed Debug Mode */
 GPIO(BATT_PRES_ODL,         PIN(E, 5), GPIO_INPUT)     /* EC_BATT_PRES_ODL: Battery Present */
@@ -151,3 +161,7 @@ ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0)             /* ADC1 (GPIO44), ADC
 ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */
 ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */
 ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)             /* PWM5 (GPIOB7) */
+ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN1 (GPIOD2) - LID_OPEN_EC */
+ALTERNATE(PIN_MASK(0, 0x01), 1, MODULE_PMU, 0)             /* PSL_IN2 (GPIO00) - ACOK_OD */
+ALTERNATE(PIN_MASK(0, 0x02), 1, MODULE_PMU, 0)             /* PSL_IN3 (GPIO01) - EC_PWR_BTN_ODL */
+ALTERNATE(PIN_MASK(0, 0x04), 1, MODULE_PMU, 0)             /* PSL_IN4 (GPIO02) - EC_RST_ODL */