stm32: fix power configuration for STM32H7

When entering STOP mode on STM32H743, the MCU was freezing forever if we
had power-cycle the MCU since the last time we entered the STM
Bootloader mode (but not when we had just flashed and reset it through
the reset pin).

This seems to be an interesting side-effect of the power configuration
locking.
The STM32H7 Reference Manual says the following about the PWR_CR3
register:
"[it is] reset only by POR only, not reset by wakeup from Standby mode
and RESET pad
...
The lower byte of this register is written once after POR and shall
be written before changing VOS level or ck_sys clock frequency."

Indeed, the system would fail waking from STOP mode if we don't do this
write (and when not doing a POR, the bootloader mode was doing it and
locking the register for us).

So keep the default configuration with the LDO enabled and lock the
register by writing SCUEN to 0.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=poppy
BUG=b:75105319
TEST=On Nocturne, power-cycle the full board and verify that the FPMCU
can come in and out of stop mode properly.

Change-Id: I822d74598b65c852b25e40ccb66a09a3e099dd2d
Reviewed-on: https://chromium-review.googlesource.com/1119922
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>

2 files changed, 20 insertions, 0 deletions

diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c
index e99ce03517..48915aca09 100644
--- a/chip/stm32/clock-stm32h7.c
+++ b/chip/stm32/clock-stm32h7.c
@@ -384,6 +384,18 @@ void clock_init(void)
 	STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE;
 
 	/*
+	 * Lock (SCUEN=0) power configuration with the LDO enabled.
+	 *
+	 * The STM32H7 Reference Manual says:
+	 * The lower byte of this register is written once after POR and shall
+	 * be written before changing VOS level or ck_sys clock frequency.
+	 *
+	 * The interesting side-effect of this that while the LDO is enabled by
+	 * default at startup, if we enter STOP mode without locking it the MCU
+	 * seems to freeze forever.
+	 */
+	STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN;
+	/*
 	 * Ensure the SPI is always clocked at the same frequency
 	 * by putting it on the fixed 64-Mhz HSI clock.
 	 * per_ck is clocked directly by the HSI (as per the default settings).
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index b7d62af766..37a49da00a 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -875,6 +875,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
 #ifdef CHIP_FAMILY_STM32H7
 #define STM32_PWR_CR2               REG32(STM32_PWR_BASE + 0x08)
 #define STM32_PWR_CR3               REG32(STM32_PWR_BASE + 0x0C)
+#define STM32_PWR_CR3_BYPASS        (1 <<  0)
+#define STM32_PWR_CR3_LDOEN         (1 <<  1)
+#define STM32_PWR_CR3_SCUEN         (1 <<  2)
+#define STM32_PWR_CR3_VBE           (1 <<  8)
+#define STM32_PWR_CR3_VBRS          (1 <<  9)
+#define STM32_PWR_CR3_USB33DEN      (1 << 24)
+#define STM32_PWR_CR3_USBREGEN      (1 << 25)
+#define STM32_PWR_CR3_USB33RDY      (1 << 26)
 #define STM32_PWR_CPUCR             REG32(STM32_PWR_BASE + 0x10)
 #define STM32_PWR_CPUCR_PDDS_D1     (1 << 0)
 #define STM32_PWR_CPUCR_PDDS_D2     (1 << 1)