diff options
| author | Furquan Shaikh <furquan@google.com> | 2018-07-05 13:41:21 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-10 00:58:57 -0700 |
| commit | 9ed36f03825946dbe4edbf40851d64f5da10f1fe (patch) | |
| tree | 90a8e348a5cd2e14b67e7ab79224eabacac20cdc | |
| parent | 0ceecc93aa1a52f69625eebfb729d77713b0a898 (diff) | |
| download | chrome-ec-9ed36f03825946dbe4edbf40851d64f5da10f1fe.tar.gz | |
phaser: Enable PSL
This change enables PSL for phaser board by:
1. Selecting CONFIG_HIBERNATE_PSL
2. Configuring alternate functions for PSL_IN pins to allow wakeup
from PSL hibernate
BUG=b:109759558
BRANCH=None
TEST=None
Change-Id: I5747d4b0408e76eb234ccd6160ea7df36a765e7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1127454
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | board/phaser/board.h | 3 | ||||
| -rw-r--r-- | board/phaser/gpio.inc | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/board/phaser/board.h b/board/phaser/board.h index 0bd698f40e..62b282460f 100644 --- a/board/phaser/board.h +++ b/board/phaser/board.h @@ -13,6 +13,9 @@ #define VARIANT_OCTOPUS_CHARGER_ISL9238 #include "baseboard.h" +/* Enable PSL hibernate mode. */ +#define CONFIG_HIBERNATE_PSL + #define CONFIG_VOLUME_BUTTONS #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL diff --git a/board/phaser/gpio.inc b/board/phaser/gpio.inc index d371f3ef52..4353b5fcc8 100644 --- a/board/phaser/gpio.inc +++ b/board/phaser/gpio.inc @@ -145,3 +145,8 @@ ALTERNATE(PIN_MASK(F, 0x0C), 0, MODULE_I2C, 0) /* I2C4 */ ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 - 1.8V */ ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3: KB_BL_PWM */ + +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 = LID_OPEN */ +ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD, + GPIO01 = MECH_PWR_BTN_ODL */ |