lpc/espi: convert ec chip code to use granular option

Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.

BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)

Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>

31 files changed, 62 insertions, 62 deletions

diff --git a/board/mchpevb1/gpio.inc b/board/mchpevb1/gpio.inc
index 2b4fa4b8fb..360f09e037 100644
--- a/board/mchpevb1/gpio.inc
+++ b/board/mchpevb1/gpio.inc
@@ -24,7 +24,7 @@
 
 #define GPIO_BOTH_EDGES_PU (GPIO_INT_BOTH | GPIO_PULL_UP)
 
-/* Only needed if CONFIG_ESPI is not set, using LPC interface to PCH */
+/* Only needed if CONFIG_HOSTCMD_ESPI is not set, using LPC interface to PCH */
 #ifndef CONFIG_ESPI_PLTRST_IS_VWIRE
 GPIO_INT(PCH_PLTRST_L, PIN(064), GPIO_BOTH_EDGES_PU, lpcrst_interrupt)
 #endif
diff --git a/board/wheatley/board.h b/board/wheatley/board.h
index caa3838a3d..ffd4e98f97 100644
--- a/board/wheatley/board.h
+++ b/board/wheatley/board.h
@@ -150,7 +150,7 @@
 #undef CONFIG_CMD_PWR_AVG
 
 /* Features of eSPI */
-#undef CONFIG_ESPI       /* Use eSPI protocol for host interface of x86 CPU */
+#undef CONFIG_HOSTCMD_ESPI
 #undef CONFIG_ESPI_VW_SIGNALS /* Use VW signals instead of GPIOs */
 
 #ifndef __ASSEMBLER__
diff --git a/chip/ish/build.mk b/chip/ish/build.mk
index a2f015f270..467cbb2f67 100644
--- a/chip/ish/build.mk
+++ b/chip/ish/build.mk
@@ -19,7 +19,7 @@ endif
 # Required chip modules
 chip-y+=clock.o gpio.o system.o hwtimer.o uart.o flash.o
 chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_LPC)+=ipc.o
+chip-$(CONFIG_HOSTCMD_LPC)+=ipc.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 
 # location of the scripts and keys used to pack the SPI flash image
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index ee31ccca05..422e49936f 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
+/* Copyright 2016 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -70,7 +70,7 @@
 /* Optional features present on this chip */
 
 /* Note: ISH does not use the LPC bus but the protocol. */
-#define CONFIG_LPC
+#define CONFIG_HOSTCMD_LPC
 
 /* GPIO - to be implemented */
 #define GPIO_PIN(index) (index)
diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk
index 391f78b575..2d664669f7 100644
--- a/chip/it83xx/build.mk
+++ b/chip/it83xx/build.mk
@@ -19,8 +19,8 @@ chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_FPU)+=it83xx_fpu.o
 chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_ADC)+=adc.o
-chip-$(CONFIG_LPC)+=lpc.o ec2i.o
-chip-$(CONFIG_ESPI)+=espi.o
+chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o
+chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
 chip-$(CONFIG_SPI)+=spi.o
 chip-$(CONFIG_PECI)+=peci.o
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 3be8c989da..a5c2840367 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -193,7 +193,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		ext_timer_ms(LOW_POWER_EXT_TIMER, EXT_PSR_32P768K_HZ,
 				1, 1, 5, 1, 0);
 		task_clear_pending_irq(et_ctrl_regs[LOW_POWER_EXT_TIMER].irq);
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 		/*
 		 * Workaround for (b:70537592):
 		 * We have to set chip select pin as input mode in order to
@@ -203,7 +203,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 #endif
 		/* Update PLL settings. */
 		clock_pll_changed();
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 		/* (b:70537592) Change back to ESPI CS# function. */
 		IT83XX_GPIO_GPCRM5 &= ~0xc0;
 #endif
@@ -259,7 +259,7 @@ void clock_init(void)
 
 	clock_module_disable();
 
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_X86
 	IT83XX_WUC_WUESR4 = (1 << 2);
 	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
 	/* bit2, wake-up enable for LPC access */
@@ -450,7 +450,7 @@ void clock_sleep_mode_wakeup_isr(void)
 		clock_event_timer_clock_change(EXT_PSR_8M_HZ, 0xffffffff);
 		task_clear_pending_irq(et_ctrl_regs[EVENT_EXT_TIMER].irq);
 		process_timers(0);
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_X86
 		/* disable lpc access wui */
 		task_disable_irq(IT83XX_IRQ_WKINTAD);
 		IT83XX_WUC_WUESR4 = (1 << 2);
@@ -490,7 +490,7 @@ void __idle(void)
 			/* reset low power mode hw timer */
 			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1);
 			sleep_mode_t0 = get_time();
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_X86
 			/* enable lpc access wui */
 			task_enable_irq(IT83XX_IRQ_WKINTAD);
 #endif
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index c58060d4fa..c56a974ba1 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -102,7 +102,7 @@
 /* Optional features present on this chip */
 #define CHIP_FAMILY_IT83XX
 #define CONFIG_ADC
-#define CONFIG_LPC
+#define CONFIG_HOSTCMD_X86
 #define CONFIG_SWITCH
 
 /* Chip needs to do custom pre-init */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index e9b87fb7ad..134d5b3472 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -523,7 +523,7 @@ static void __gpio_irq(void)
 	}
 #endif
 
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_X86
 	if (irq == IT83XX_IRQ_WKINTAD)
 		return;
 #endif
diff --git a/chip/it83xx/intc.c b/chip/it83xx/intc.c
index 2becd74b60..2d1f06b2db 100644
--- a/chip/it83xx/intc.c
+++ b/chip/it83xx/intc.c
@@ -47,7 +47,7 @@ void intc_cpu_int_group_5(void)
 	int intc_group_5 = intc_get_ec_int();
 
 	switch (intc_group_5) {
-#if defined(CONFIG_LPC) && defined(HAS_TASK_KEYPROTO)
+#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
 	case IT83XX_IRQ_KBC_OUT:
 		lpc_kbc_obe_interrupt();
 		break;
@@ -68,7 +68,7 @@ void intc_cpu_int_group_4(void)
 	int intc_group_4 = intc_get_ec_int();
 
 	switch (intc_group_4) {
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_X86
 	case IT83XX_IRQ_PMC_IN:
 		pm1_ibf_interrupt();
 		break;
@@ -106,7 +106,7 @@ void intc_cpu_int_group_12(void)
 		peci_interrupt();
 		break;
 #endif
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	case IT83XX_IRQ_ESPI:
 		espi_interrupt();
 		break;
diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h
index 268930eee5..b24d17fd2b 100644
--- a/chip/it83xx/intc.h
+++ b/chip/it83xx/intc.h
@@ -25,7 +25,7 @@ void espi_interrupt(void);
 void espi_vw_interrupt(void);
 void espi_init(void);
 
-#if defined(CONFIG_LPC) && defined(HAS_TASK_KEYPROTO)
+#if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO)
 void lpc_kbc_ibf_interrupt(void);
 void lpc_kbc_obe_interrupt(void);
 #endif
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 61110498b3..cd65e3b326 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -136,7 +136,7 @@ static void keyboard_irq_assert(void)
  */
 static void lpc_generate_smi(void)
 {
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	espi_vw_set_wire(VW_SMI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SMI_L, 1);
@@ -149,7 +149,7 @@ static void lpc_generate_smi(void)
 
 static void lpc_generate_sci(void)
 {
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	espi_vw_set_wire(VW_SCI_L, 0);
 	udelay(65);
 	espi_vw_set_wire(VW_SCI_L, 1);
@@ -700,7 +700,7 @@ static void lpc_init(void)
 	task_clear_pending_irq(IT83XX_IRQ_PMC3_IN);
 	task_enable_irq(IT83XX_IRQ_PMC3_IN);
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	espi_init();
 #endif
 	/* Sufficiently initialized */
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
index 8adde58abd..a9982efced 100644
--- a/chip/lm4/build.mk
+++ b/chip/lm4/build.mk
@@ -20,7 +20,7 @@ chip-$(CONFIG_EEPROM)+=eeprom.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_LPC)+=lpc.o
+chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
 chip-$(CONFIG_PECI)+=peci.o
 # pwm functions are implemented with the fan functions
 chip-$(CONFIG_PWM)+=pwm.o fan.o
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index 64dfb99dc6..9d3c53ded2 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -93,7 +93,7 @@
 /* Optional features present on this chip */
 #define CONFIG_ADC
 #define CONFIG_HOSTCMD_ALIGNED
-#define CONFIG_LPC
+#define CONFIG_HOSTCMD_LPC
 #define CONFIG_PECI
 #define CONFIG_SWITCH
 #define CONFIG_MPU
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
index 21fdf70ec9..6ef9f67834 100644
--- a/chip/lm4/uart.c
+++ b/chip/lm4/uart.c
@@ -123,7 +123,7 @@ void uart_host_interrupt(void)
 	/* Clear transmit and receive interrupt status */
 	LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;
 
-#ifdef CONFIG_LPC
+#ifdef CONFIG_HOSTCMD_LPC
 	/*
 	 * If we have space in our FIFO and a character is pending in LPC,
 	 * handle that character.
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk
index 797ba975e6..c3883a0e6f 100644
--- a/chip/mchp/build.mk
+++ b/chip/mchp/build.mk
@@ -32,12 +32,12 @@ endif
 chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_DMA)+=dma.o
-chip-$(CONFIG_ESPI)+=espi.o
+chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
 chip-$(CONFIG_MEC_GPIO_EC_CMDS)+=gpio_cmds.o
-chip-$(CONFIG_LPC)+=lpc.o
+chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
 chip-$(CONFIG_MCHP_GPSPI)+=gpspi.o
 chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_SPI)+=spi.o qmspi.o
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c
index d0df0240f9..123e26e851 100644
--- a/chip/mchp/clock.c
+++ b/chip/mchp/clock.c
@@ -358,7 +358,7 @@ static void prepare_for_deep_sleep(void)
 #endif
 
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
@@ -446,7 +446,7 @@ static void resume_from_deep_sleep(void)
 	 */
 	MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0);
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	#ifdef CONFIG_POWER_S0IX
 	MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
 	MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI;
diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h
index f69ed386d0..31a895a6d8 100644
--- a/chip/mchp/config_chip.h
+++ b/chip/mchp/config_chip.h
@@ -121,7 +121,7 @@
 /* Optional features present on this chip */
 #define CONFIG_ADC
 #define CONFIG_DMA
-#define CONFIG_LPC
+#define CONFIG_HOSTCMD_X86
 #define CONFIG_SPI
 #define CONFIG_SWITCH
 
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index ac47b042f6..3027cfac9a 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -85,7 +85,7 @@ static void lpc_generate_smi(void)
 {
 	/* CPRINTS("LPC Pulse SMI"); */
 	trace0(0, LPC, 0, "LPC Pulse SMI");
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	/* eSPI: pulse SMI# Virtual Wire low */
 	espi_vw_pulse_wire(VW_SMI_L, 0);
 #else
@@ -104,7 +104,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
 #else
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	espi_vw_pulse_wire(VW_SCI_L, 0);
 #else
 	MCHP_ACPI_PM_STS |= 1;
@@ -127,7 +127,7 @@ static void lpc_update_wake(host_event_t wake_events)
 	 */
 	wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	espi_vw_set_wire(VW_WAKE_L, !wake_events);
 #else
 	/* Signal is asserted low when wake events is non-zero */
@@ -308,7 +308,7 @@ void lpc_mem_mapped_init(void)
  * For eSPI PLATFORM_RESET# virtual wire is used as LRESET#
  *
  */
-#ifndef CONFIG_ESPI
+#ifndef CONFIG_HOSTCMD_ESPI
 static void setup_lpc(void)
 {
 	gpio_config_module(MODULE_LPC, 1);
@@ -425,7 +425,7 @@ static void lpc_init(void)
 
 	MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0);
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 
 	espi_init();
 
@@ -490,7 +490,7 @@ void lpc_set_init_done(int val)
  */
 void lpcrst_interrupt(enum gpio_signal signal)
 {
-#ifndef CONFIG_ESPI
+#ifndef CONFIG_HOSTCMD_ESPI
 	/* Initialize LPC module when LRESET# is deasserted */
 	if (!lpc_get_pltrst_asserted()) {
 		setup_lpc();
@@ -813,7 +813,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask)
 
 int lpc_get_pltrst_asserted(void)
 {
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	/*
 	 * eSPI PLTRST# a VWire or side-band signal
 	 * Controlled by CONFIG_ESPI_PLTRST_IS_VWIRE
diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h
index 1961919931..8d4caa3a7c 100644
--- a/chip/mchp/lpc_chip.h
+++ b/chip/mchp/lpc_chip.h
@@ -8,7 +8,7 @@
 #ifndef __CROS_EC_LPC_CHIP_H
 #define __CROS_EC_LPC_CHIP_H
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 
 #include "espi.h"
 
diff --git a/chip/mchp/system.c b/chip/mchp/system.c
index 24aafdbf1e..fa844a2304 100644
--- a/chip/mchp/system.c
+++ b/chip/mchp/system.c
@@ -151,7 +151,7 @@ void system_pre_init(void)
 	MCHP_EC_AHB_ERR = 0;	/* write any value to clear */
 	MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18;
 #endif
 
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
index 14726e9705..30ab8d7622 100644
--- a/chip/mec1322/build.mk
+++ b/chip/mec1322/build.mk
@@ -22,7 +22,7 @@ chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_LPC)+=lpc.o
+chip-$(CONFIG_HOSTCMD_LPC)+=lpc.o
 chip-$(CONFIG_PWM)+=pwm.o
 chip-$(CONFIG_WATCHDOG)+=watchdog.o
 chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index d06c1e78d3..206e444038 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -103,7 +103,7 @@
 #define CONFIG_MPU
 #endif
 #define CONFIG_DMA
-#define CONFIG_LPC
+#define CONFIG_HOSTCMD_LPC
 #define CONFIG_SPI
 #define CONFIG_SWITCH
 
diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk
index 215edf58fb..e4783439a3 100644
--- a/chip/npcx/build.mk
+++ b/chip/npcx/build.mk
@@ -25,8 +25,8 @@ chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o
 chip-$(CONFIG_I2C)+=i2c.o i2c-$(CHIP_FAMILY).o
-chip-$(CONFIG_LPC)+=lpc.o
-chip-$(CONFIG_ESPI)+=espi.o
+chip-$(CONFIG_HOSTCMD_X86)+=lpc.o
+chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o
 chip-$(CONFIG_PECI)+=peci.o
 chip-$(CONFIG_HOSTCMD_SPS)+=shi.o
 chip-$(CONFIG_CEC)+=cec.o
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index e2f071fea8..a146436034 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -382,7 +382,7 @@ void __idle(void)
 			 * CSAE bit is set. Please notice this symptom only
 			 * occurs at npcx5.
 			 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
 			/* Enable Host access wakeup */
 			SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index c0fd7cc35f..df8e1733d9 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -501,7 +501,7 @@ void _irq_func(void)					\
 /* If we need to handle the other type interrupts except GPIO, add code here */
 void __gpio_wk0efgh_interrupt(void)
 {
-#if defined(CONFIG_LPC) || defined(CONFIG_ESPI)
+#ifdef CONFIG_HOSTCMD_X86
 	/* Pending bit 7 or 6 or 5? */
 	if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 6) &&
 	    IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) {
@@ -510,7 +510,7 @@ void __gpio_wk0efgh_interrupt(void)
 		/* Clear pending bit of WUI */
 		SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 	}
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) &&
 		 IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5))
 		espi_espirst_handler();
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index e097402a99..2d4391583e 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -52,7 +52,7 @@
  * For eSPI - it is 200 us.
  * For LPC - it is 5 us.
  */
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 #define LPC_HOST_TRANSACTION_TIMEOUT_US 200
 #else
 #define LPC_HOST_TRANSACTION_TIMEOUT_US 5
@@ -102,7 +102,7 @@ static void lpc_task_enable_irq(void)
 #endif
 	task_enable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_enable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	task_enable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_enable_irq(NPCX_IRQ_WKINTA_2);
@@ -121,7 +121,7 @@ static void lpc_task_disable_irq(void)
 #endif
 	task_disable_irq(NPCX_IRQ_PM_CHAN_IBF);
 	task_disable_irq(NPCX_IRQ_PORT80);
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	task_disable_irq(NPCX_IRQ_ESPI);
 	/* Virtual Wire: SLP_S3/4/5, SUS_STAT, PLTRST, OOB_RST_WARN */
 	task_disable_irq(NPCX_IRQ_WKINTA_2);
@@ -153,7 +153,7 @@ static void lpc_generate_smi(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(GPIO_PCH_SMI_L, 1);
-#elif defined(CONFIG_ESPI)
+#elif defined(CONFIG_HOSTCMD_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -199,7 +199,7 @@ static void lpc_generate_sci(void)
 	udelay(65);
 	/* Set signal high, now that we've generated the edge */
 	gpio_set_level(CONFIG_SCI_GPIO, 1);
-#elif defined(CONFIG_ESPI)
+#elif defined(CONFIG_HOSTCMD_ESPI)
 	/*
 	 * Don't use SET_BIT/CLEAR_BIT macro to toggle SMIB/SCIB to generate
 	 * virtual wire. Use NPCX_VW_SMI/NPCX_VW_SCI macro instead.
@@ -812,7 +812,7 @@ int lpc_get_pltrst_asserted(void)
 	return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT);
 }
 
-#ifndef CONFIG_ESPI
+#ifndef CONFIG_HOSTCMD_ESPI
 /* Initialize host settings by interrupt */
 void lpc_lreset_pltrst_handler(void)
 {
@@ -855,7 +855,7 @@ static void lpc_init(void)
 	/* Enable clock for LPC peripheral */
 	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
 			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	/* Initialize eSPI IP */
 	espi_init();
 #else
@@ -870,7 +870,7 @@ static void lpc_init(void)
 	/* Clear Host Access Hold state */
 	NPCX_SMC_CTL = 0xC0;
 
-#ifndef CONFIG_ESPI
+#ifndef CONFIG_HOSTCMD_ESPI
 	/*
 	 * Set alternative pin from GPIO to CLKRUN no matter SERIRQ is under
 	 * continuous or quiet mode.
@@ -883,7 +883,7 @@ static void lpc_init(void)
 	 * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW
 	 * automatically by toggling them, too. It's unnecessary to set pin mux.
 	 */
-#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_ESPI)
+#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_HOSTCMD_ESPI)
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL);
 	SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL);
 #endif
@@ -962,7 +962,7 @@ static void lpc_init(void)
 	 * Init PORT80
 	 * Enable Port80, Enable Port80 function & Interrupt & Read auto
 	 */
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 	NPCX_DP80CTL = 0x2b;
 #else
 	NPCX_DP80CTL = 0x29;
@@ -1012,7 +1012,7 @@ static void lpc_init(void)
 	/* initial IO port address via SIB-write modules */
 	host_register_init();
 #else
-#ifndef CONFIG_ESPI
+#ifndef CONFIG_HOSTCMD_ESPI
 	/*
 	 * Initialize LRESET# interrupt only in case of LPC. For eSPI, there is
 	 * no dedicated GPIO pin for LRESET/PLTRST. PLTRST is indicated as a VW
diff --git a/chip/npcx/lpc_chip.h b/chip/npcx/lpc_chip.h
index 5a7cf2e6fb..c2f80158af 100644
--- a/chip/npcx/lpc_chip.h
+++ b/chip/npcx/lpc_chip.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -11,7 +11,7 @@
 /* For host registers initialization via SIB module */
 void host_register_init(void);
 
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 /* eSPI Initialization functions */
 void espi_init(void);
 /* eSPI reset assert/de-assert interrupt */
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 5abf8d408d..c3cace0fb9 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -691,7 +691,7 @@ void system_pre_init(void)
 	pwdwn6 = 0x70 |
 		(1 << NPCX_PWDWN_CTL6_ITIM6_PD) |
 		(1 << NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
-#if !defined(CONFIG_ESPI)
+#if !defined(CONFIG_HOSTCMD_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_6) = pwdwn6;
diff --git a/common/build.mk b/common/build.mk
index d64288b5ff..a6f2fd2d1c 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -49,7 +49,7 @@ common-$(CONFIG_DEVICE_STATE)+=device_state.o
 common-$(CONFIG_DPTF)+=dptf.o
 common-$(CONFIG_EC_EC_COMM_MASTER)+=ec_ec_comm_master.o
 common-$(CONFIG_EC_EC_COMM_SLAVE)+=ec_ec_comm_slave.o
-common-$(CONFIG_ESPI)+=espi.o
+common-$(CONFIG_HOSTCMD_ESPI)+=espi.o
 common-$(CONFIG_EXTENSION_COMMAND)+=extension.o
 common-$(CONFIG_EXTPOWER_GPIO)+=extpower_gpio.o
 common-$(CONFIG_FANS)+=fan.o pwm.o
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c
index 75e54f6633..4d47041e8a 100644
--- a/core/cortex-m/task.c
+++ b/core/cortex-m/task.c
@@ -75,7 +75,7 @@ void __idle(void)
 		 * CSAE bit is set. Please notice this symptom only
 		 * occurs at npcx5.
 		 */
-#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_ESPI)
+#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI)
 		/* Enable Host access wakeup */
 		SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
 #endif
diff --git a/core/nds32/init.S b/core/nds32/init.S
index d13eeb3a57..4db057dd91 100644
--- a/core/nds32/init.S
+++ b/core/nds32/init.S
@@ -87,7 +87,7 @@ vector irq_15,   15	/* HW 15 */
 .global eflash_sig
 eflash_sig:
 .byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
-#ifdef CONFIG_ESPI
+#ifdef CONFIG_HOSTCMD_ESPI
 .byte 0xA4 /* eSPI */
 #else
 .byte 0xA5 /* LPC */