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authorscott worley <scott.worley@microchip.corp-partner.google.com>2018-05-10 11:46:12 -0400
committerchrome-bot <chrome-bot@chromium.org>2018-05-22 21:57:06 -0700
commita63b30e6de09a51ea8f2fec3ba1bd033052a5f6b (patch)
treeda88ef37528719a4377cc8d3111a20606a939cf8
parent67ed6ee3e79400996e276c87eeb32765f6d124e2 (diff)
downloadchrome-ec-a63b30e6de09a51ea8f2fec3ba1bd033052a5f6b.tar.gz
ec_chip_mchp: Lower UART interrupt priority.
Reduce UART interrupt priority to not interfere with critical interrupts. WDT highest, GPIO & other HW, UART, Port80(lowest). BRANCH=none BUG= TEST=Build boards based on chip mchp. CQ-DEPEND=CL:1053576 Change-Id: I293132fce46cc460d1cf51abacf4b6a494c8c4a3 Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1053873 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--chip/mchp/uart.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/chip/mchp/uart.c b/chip/mchp/uart.c
index c38ab33aea..adeea5a31c 100644
--- a/chip/mchp/uart.c
+++ b/chip/mchp/uart.c
@@ -113,7 +113,8 @@ void uart_enable_interrupt(void)
}
/**
- * Interrupt handler for UART
+ * Interrupt handler for UART.
+ * Lower priority below other critical ISR's.
*/
void uart_ec_interrupt(void)
{
@@ -122,7 +123,7 @@ void uart_ec_interrupt(void)
/* Trace statement to provide time marker for UART output? */
uart_process_output();
}
-DECLARE_IRQ(MCHP_IRQ_UART0, uart_ec_interrupt, 1);
+DECLARE_IRQ(MCHP_IRQ_UART0, uart_ec_interrupt, 2);
void uart_init(void)
{