diff options
| author | Shamile Khan <shamile.khan@intel.com> | 2017-10-25 12:53:13 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-01-16 21:26:27 -0800 |
| commit | 0348eb1059cd4fa43b8426013314f76ac201bd7a (patch) | |
| tree | 824bc8359a252fbb962a4b4a05b9fd08f266b04a | |
| parent | 51e9e69f386366256807e6f4ccdd258821cdcfe0 (diff) | |
| download | chrome-ec-0348eb1059cd4fa43b8426013314f76ac201bd7a.tar.gz | |
glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMI
BUG=None
BRANCH=None
TEST=GLKRVP can boot to OS when a coreboot image with eSPI
enabled is flashed.
Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/818196
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/glkrvp/board.h | 2 | ||||
| -rw-r--r-- | board/glkrvp/gpio.inc | 6 | ||||
| -rw-r--r-- | power/apollolake.c | 4 |
3 files changed, 9 insertions, 3 deletions
diff --git a/board/glkrvp/board.h b/board/glkrvp/board.h index abc6766ee2..6e9954a998 100644 --- a/board/glkrvp/board.h +++ b/board/glkrvp/board.h @@ -74,6 +74,7 @@ #define CONFIG_USB_MUX_PS8743 /* SoC / PCH */ +#define CONFIG_ESPI #define CONFIG_LPC #define CONFIG_CHIPSET_APOLLOLAKE #define CONFIG_CHIPSET_RESET_HOOK @@ -82,7 +83,6 @@ #define CONFIG_POWER_COMMON #define CONFIG_POWER_S0IX #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE -#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L /* EC */ #define CONFIG_BOARD_VERSION diff --git a/board/glkrvp/gpio.inc b/board/glkrvp/gpio.inc index e9fbf713f9..0c8425d026 100644 --- a/board/glkrvp/gpio.inc +++ b/board/glkrvp/gpio.inc @@ -25,8 +25,6 @@ GPIO_INT(USB_C1_PD_INT_ODL, PIN(6, 3), GPIO_INT_FALLING, tcpc_alert_event) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(3, 4), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLDN_BTN_ODL, PIN(3, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO(PCH_SMI_L, PIN(C, 6), GPIO_ODR_HIGH) /* EC_SMI_ODL */ -GPIO(PCH_SCI_L, PIN(7, 6), GPIO_ODR_HIGH) /* EC_SCI_ODL */ GPIO(PCH_PWRBTN_L, PIN(7, 5), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ GPIO(PCH_WAKE_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_SYS_PWROK, PIN(3, 5), GPIO_OUT_LOW) /* EC_PCH_PWROK */ @@ -115,6 +113,10 @@ GPIO(NC_66, PIN(6, 6), GPIO_INPUT) GPIO(NC_B6, PIN(B, 6), GPIO_INPUT) +/* SMI/SCI pins unused for eSPI */ +GPIO(NC_C6, PIN(C, 6), GPIO_INPUT | GPIO_PULL_UP) +GPIO(NC_76, PIN(7, 6), GPIO_INPUT | GPIO_PULL_UP) + /* eSPI: VHIF Unused pins 1.8V & Interruptable */ GPIO(NC_46, PIN(4, 6), GPIO_INPUT) GPIO(NC_47, PIN(4, 7), GPIO_INPUT) diff --git a/power/apollolake.c b/power/apollolake.c index c3ca7f55f5..feecd24f8e 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -42,6 +42,10 @@ enum power_state chipset_force_g3(void) return POWER_G3; } +void chipset_handle_espi_reset_assert(void) +{ +} + void chipset_reset(int cold_reset) { CPRINTS("%s(%d)", __func__, cold_reset); |