nautilus/poppy/soraka: Add support for dumping PMIC fault registers

If during PMIC initialization, it is identified that there was a VR
fault, then dump fault registers 0x16 and 0x17 to EC console. This
information is very useful during debugging sudden power losses in
field and so it is printed out to EC console.

Additionally, add panic reason with these register values as panic
data so that OS can provide this information in cros ec
panicinfo. This helps in retaining the information even if EC console
logs overflow.

BUG=b:65732924,b:69334392
BRANCH=None
TEST=Verified that on the failing Lux system, PMIC VR fault is
reported:"PMIC VRFAULT: PWRSTAT1=0x00 PWRSTAT2=0x01".

Also, verified that pmic fault register info is reported correctly in
panicinfo:
cat /sys/kernel/debug/cros_ec/panicinfo > /tmp/panicinfo
hexdump -n 1 -s 0x14 -e '"0x""%02X""\n"' /tmp/panicinfo
0x00
hexdump -n 1 -s 0x15 -e '"0x""%02X""\n"' /tmp/panicinfo
0x01

Change-Id: Ic6096887cd66046d11a5eb1d942b635b3e48a236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674033
Reviewed-by: Shawn N <shawnn@chromium.org>

4 files changed, 106 insertions, 0 deletions

diff --git a/board/nautilus/board.c b/board/nautilus/board.c
index 76f158327d..95cb9fe7be 100644
--- a/board/nautilus/board.c
+++ b/board/nautilus/board.c
@@ -259,6 +259,50 @@ const struct temp_sensor_t temp_sensors[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
 
+/*
+ * Check if PMIC fault registers indicate VR fault. If yes, print out fault
+ * register info to console. Additionally, set panic reason so that the OS can
+ * check for fault register info by looking at offset 0x14(PWRSTAT1) and
+ * 0x15(PWRSTAT2) in cros ec panicinfo.
+ */
+static void board_report_pmic_fault(const char *str)
+{
+	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
+	uint32_t info;
+
+	/* RESETIRQ1 -- Bit 4: VRFAULT */
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, &vrfault)
+	    != EC_SUCCESS)
+		return;
+
+	if (!(vrfault & (1 << 4)))
+		return;
+
+	/* VRFAULT has occurred, print VRFAULT status bits. */
+
+	/* PWRSTAT1 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, &pwrstat1);
+
+	/* PWRSTAT2 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, &pwrstat2);
+
+	CPRINTS("PMIC VRFAULT: %s", str);
+	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
+		pwrstat2);
+
+	/* Clear all faults -- Write 1 to clear. */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
+
+	/*
+	 * Status of the fault registers can be checked in the OS by looking at
+	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
+	 */
+	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
+	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
+}
+
 static void board_pmic_disable_slp_s0_vr_decay(void)
 {
 	/*
@@ -347,6 +391,8 @@ void power_board_handle_host_sleep_event(enum host_sleep_event state)
 
 static void board_pmic_init(void)
 {
+	board_report_pmic_fault("SYSJUMP");
+
 	if (system_jumped_to_this_image())
 		return;
 
@@ -658,6 +704,12 @@ void lid_angle_peripheral_enable(int enable)
 }
 #endif
 
+static void board_chipset_reset(void)
+{
+	board_report_pmic_fault("CHIPSET RESET");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
+
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
 {
diff --git a/board/nautilus/board.h b/board/nautilus/board.h
index d4e8bd153e..57bbeeb3df 100644
--- a/board/nautilus/board.h
+++ b/board/nautilus/board.h
@@ -32,6 +32,7 @@
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
+#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_UART_HOST 0
diff --git a/board/poppy/board.c b/board/poppy/board.c
index 09327c9801..7e2e5a9366 100644
--- a/board/poppy/board.c
+++ b/board/poppy/board.c
@@ -540,6 +540,50 @@ const struct button_config *recovery_buttons[] = {
 };
 const int recovery_buttons_count = ARRAY_SIZE(recovery_buttons);
 
+/*
+ * Check if PMIC fault registers indicate VR fault. If yes, print out fault
+ * register info to console. Additionally, set panic reason so that the OS can
+ * check for fault register info by looking at offset 0x14(PWRSTAT1) and
+ * 0x15(PWRSTAT2) in cros ec panicinfo.
+ */
+static void board_report_pmic_fault(const char *str)
+{
+	int vrfault, pwrstat1 = 0, pwrstat2 = 0;
+	uint32_t info;
+
+	/* RESETIRQ1 -- Bit 4: VRFAULT */
+	if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, &vrfault)
+	    != EC_SUCCESS)
+		return;
+
+	if (!(vrfault & (1 << 4)))
+		return;
+
+	/* VRFAULT has occurred, print VRFAULT status bits. */
+
+	/* PWRSTAT1 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, &pwrstat1);
+
+	/* PWRSTAT2 */
+	i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, &pwrstat2);
+
+	CPRINTS("PMIC VRFAULT: %s", str);
+	CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1,
+		pwrstat2);
+
+	/* Clear all faults -- Write 1 to clear. */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4));
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1);
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2);
+
+	/*
+	 * Status of the fault registers can be checked in the OS by looking at
+	 * offset 0x14(PWRSTAT1) and 0x15(PWRSTAT2) in cros ec panicinfo.
+	 */
+	info = ((pwrstat2 & 0xFF) << 8) | (pwrstat1 & 0xFF);
+	panic_set_reason(PANIC_SW_PMIC_FAULT, info, 0);
+}
+
 static void board_pmic_disable_slp_s0_vr_decay(void)
 {
 	/*
@@ -628,6 +672,8 @@ void power_board_handle_host_sleep_event(enum host_sleep_event state)
 
 static void board_pmic_init(void)
 {
+	board_report_pmic_fault("SYSJUMP");
+
 	if (system_jumped_to_this_image())
 		return;
 
@@ -1052,6 +1098,12 @@ static void board_sensor_init(void)
 DECLARE_HOOK(HOOK_INIT, board_sensor_init, HOOK_PRIO_DEFAULT);
 #endif
 
+static void board_chipset_reset(void)
+{
+	board_report_pmic_fault("CHIPSET RESET");
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESET, board_chipset_reset, HOOK_PRIO_DEFAULT);
+
 /* Called on AP S3 -> S0 transition */
 static void board_chipset_resume(void)
 {
diff --git a/board/poppy/board.h b/board/poppy/board.h
index 95050f8700..eea4a75c02 100644
--- a/board/poppy/board.h
+++ b/board/poppy/board.h
@@ -31,6 +31,7 @@
 #define CONFIG_LOW_POWER_IDLE
 #define CONFIG_LTO
 #define CONFIG_CHIP_PANIC_BACKUP
+#define CONFIG_SOFTWARE_PANIC
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25X40
 #define CONFIG_UART_HOST 0