coil: i2cs -> i2cp

Rename i2cs functionas and variables to i2cp. Change some basic
comments.

I will rework the i2cp comments to stop using controller when referring
to the i2cp, because it's kind of confusing now that master has been
renamed to controller.

BUG=b:175244613
TEST=make buildall -j

Change-Id: I9574e77ab42427ca90d5b8a6421793f52e519f67
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611761
Reviewed-by: Namyoon Woo <namyoon@chromium.org>

8 files changed, 106 insertions, 106 deletions

diff --git a/board/cr50/board.c b/board/cr50/board.c
index d9720956de..0dd9e5ef5d 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -1577,7 +1577,7 @@ static void init_board_properties(void)
 }
 DECLARE_HOOK(HOOK_INIT, init_board_properties, HOOK_PRIO_FIRST);
 
-void i2cs_set_pinmux(void)
+void i2cp_set_pinmux(void)
 {
 	/* Connect I2CS SDA/SCL output to A1/A9 pads */
 	GWRITE(PINMUX, DIOA1_SEL, GC_PINMUX_I2CS0_SDA_SEL);
@@ -1806,17 +1806,17 @@ void board_start_ite_sync(void)
 	hook_call_deferred(&deferred_ite_sync_reset_data, 10 * MSEC);
 }
 
-void board_unwedge_i2cs(void)
+void board_unwedge_i2cp(void)
 {
 	/*
-	 * Create connection between i2cs_scl and the 'unwedge_scl' GPIO, and
-	 * generate the i2c stop sequence which will reset the i2cs FSM.
+	 * Create connection between i2cp_scl and the 'unwedge_scl' GPIO, and
+	 * generate the i2c stop sequence which will reset the i2cp FSM.
 	 *
-	 * First, disconnect the external pin from the i2cs_scl input.
+	 * First, disconnect the external pin from the i2cp_scl input.
 	 */
 	GWRITE(PINMUX, DIOA9_SEL, 0);
 
-	/* Connect the 'unwedge' GPIO to the i2cs_scl input. */
+	/* Connect the 'unwedge' GPIO to the i2cp_scl input. */
 	GWRITE(PINMUX, GPIO1_GPIO5_SEL, GC_PINMUX_I2CS0_SCL_SEL);
 
 	/* Generate a 'stop' condition. */
@@ -1830,7 +1830,7 @@ void board_unwedge_i2cs(void)
 	/* Disconnect the 'unwedge' mode SCL. */
 	GWRITE(PINMUX, GPIO1_GPIO5_SEL, 0);
 
-	/* Restore external pin connection to the i2cs_scl. */
+	/* Restore external pin connection to the i2cp_scl. */
 	GWRITE(PINMUX, DIOA9_SEL, GC_PINMUX_I2CS0_SCL_SEL);
 }
 
diff --git a/board/cr50/board.h b/board/cr50/board.h
index 69e2a5d1a7..bf54ba7c9f 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -426,10 +426,10 @@ void board_start_ite_sync(void);
 
 /*
  * Board specific function (needs information about pinmux settings) which
- * allows to take the i2cs controller out of the 'wedged' state where the
+ * allows to take the i2cp controller out of the 'wedged' state where the
  * master stopped i2c access mid transaction and the slave is holding SDA low,
  */
-void board_unwedge_i2cs(void);
+void board_unwedge_i2cp(void);
 
 int board_in_prod_mode(void);
 
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
index e527f7815b..0efac639aa 100644
--- a/board/cr50/gpio.inc
+++ b/board/cr50/gpio.inc
@@ -116,7 +116,7 @@ GPIO_INT(DETECT_TPM_RST_L_ASSERTED, PIN(1, 4),  GPIO_INT_FALLING,
  * Also, it works to detect an I2C transaction during extended INT_AP_L
  * assertion.
  */
-GPIO_INT(MONITOR_I2CS_SDA, PIN(1, 6), GPIO_INT_LOW, i2cs_sda_isr)
+GPIO_INT(MONITOR_I2CS_SDA, PIN(1, 6), GPIO_INT_LOW, i2cp_sda_isr)
 
 /*
  * These GPIOs are to enable or disable EC-CR50 communication.
@@ -294,7 +294,7 @@ PINMUX(GPIO(DETECT_SERVO),      B5, DIO_INPUT)
  * A1 is also used as a strapping option GPIO input which is configured
  * above. If a board is configured (via the strapping pins) to support the I2CS
  * interface, then the connection of A1 and A9 to/from the I2C0_SDA and I2C0_SCL
- * lines is done in the function i2cs_set_pinmux() which lives in board.c.
+ * lines is done in the function i2cp_set_pinmux() which lives in board.c.
  *
  * PINMUX(FUNC(I2C0_SCL),        A9, DIO_INPUT)
  * PINMUX(FUNC(I2C0_SDA),        A1, DIO_INPUT)
diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c
index 9aa73d18cb..72a569bd99 100644
--- a/chip/g/i2cs.c
+++ b/chip/g/i2cs.c
@@ -4,7 +4,7 @@
  */
 
 /*
- * This is a driver for the I2C Slave controller (i2cs) of the g chip.
+ * This is a driver for the I2C peripheral (i2cp) of the g chip.
  *
  * The controller is has two register files, 64 bytes each, one for storing
  * data received from the master, and one for storing data to be transmitted
@@ -84,7 +84,7 @@
 static wr_complete_handler_f write_complete_handler_;
 
 /* A buffer to normalize the received data to pass it to the user. */
-static uint8_t i2cs_buffer[REGISTER_FILE_SIZE];
+static uint8_t i2cp_buffer[REGISTER_FILE_SIZE];
 
 /*
  * Pointer where the CPU stopped retrieving the write data sent by the master
@@ -101,10 +101,10 @@ static uint16_t last_read_pointer;
 /*
  * Keep track number of times the "hosed slave" condition was encountered.
  */
-static uint16_t i2cs_read_recovery_count;
-static uint16_t i2cs_sda_low_count;
+static uint16_t i2cp_read_recovery_count;
+static uint16_t i2cp_sda_low_count;
 
-static void check_i2cs_state(void)
+static void check_i2cp_state(void)
 {
 	if (gpio_get_level(GPIO_MONITOR_I2CS_SDA))
 		return;
@@ -113,36 +113,36 @@ static void check_i2cs_state(void)
 	 * The bus might be stuck;
 	 * Generate a stop sequence to unwedge.
 	 */
-	board_unwedge_i2cs();
+	board_unwedge_i2cp();
 }
 
-static void i2cs_init(void)
+static void i2cp_init(void)
 {
 
 	/* First decide if i2c is even needed for this platform. */
-	/* if (i2cs is not needed) return; */
+	/* if (i2cp is not needed) return; */
 	if (!board_tpm_uses_i2c())
 		return;
 
 	pmu_clock_en(PERIPH_I2CP);
 
-	memset(i2cs_buffer, 0, sizeof(i2cs_buffer));
+	memset(i2cp_buffer, 0, sizeof(i2cp_buffer));
 
-	i2cs_set_pinmux();
+	i2cp_set_pinmux();
 
-	check_i2cs_state();
+	check_i2cp_state();
 
 	/* Reset read and write pointers. */
 	last_write_pointer = 0;
 	last_read_pointer = 0;
-	i2cs_sda_low_count = 0;
+	i2cp_sda_low_count = 0;
 	GWRITE(I2CS, READ_PTR, 0);
 	GWRITE(I2CS, WRITE_PTR, 0);
 
 	/* Just in case we were wedged and the master starts with a read. */
 	*GREG32_ADDR(I2CS, READ_BUFFER0) = ~0;
 
-	/* Enable I2CS interrupt */
+	/* Enable I2CP interrupt */
 	GWRITE_FIELD(I2CS, INT_ENABLE, INTR_WRITE_COMPLETE, 1);
 
 	/* Slave address is hardcoded to 0x50. */
@@ -160,7 +160,7 @@ DECLARE_DEFERRED(poll_read_state);
  */
 #define READ_STATUS_CHECK_INTERVAL (700 * MSEC)
 
-/* Number of times SDA must be low between i2c writes before the i2cs controller
+/* Number of times SDA must be low between i2c writes before the i2cp controller
  * is restarted.
  *
  * Three was chosen because we can have two i2c transactions in between write
@@ -168,19 +168,19 @@ DECLARE_DEFERRED(poll_read_state);
  *
  * Consider the following timeline:
  * 1) START <i2c_addr|W> <reg> STOP
- * 2) Write complete handler runs (i2cs_sda_low_count = 0)
- * 3) START <i2c_addr|R> <data>+ STOP (i2cs_sda_low_count++)
- * 4) START <i2c_addr|W> <reg> <data>+ STOP (i2cs_sda_low_count++)
+ * 2) Write complete handler runs (i2cp_sda_low_count = 0)
+ * 3) START <i2c_addr|R> <data>+ STOP (i2cp_sda_low_count++)
+ * 4) START <i2c_addr|W> <reg> <data>+ STOP (i2cp_sda_low_count++)
  * 5) Write complete handler runs
  *
  * If the poller happened to run during time 3 and time 4 while SDA was low,
- * i2cs_sda_low_count would = 2. This is not considered an error case. If we
+ * i2cp_sda_low_count would = 2. This is not considered an error case. If we
  * were to see a third low value before time 5, we can assume the bus is stuck,
  * or the master performed multiple reads between writes (which is not
  * expected).
  *
  * If we were to enable the read complete interrupt and use it to clear
- * i2cs_sda_low_count we could get away with a threshold of two. This would also
+ * i2cp_sda_low_count we could get away with a threshold of two. This would also
  * support multiple reads after a write.
  *
  * We could in theory use the FIFO read/write pointers to determine if the bus
@@ -196,13 +196,13 @@ DECLARE_DEFERRED(poll_read_state);
 #define READ_STATUS_CHECK_THRESHOLD 3
 
 /*
- * Restart the i2cs controller if the controller gets stuck transmitting a 0 on
+ * Restart the i2cp controller if the controller gets stuck transmitting a 0 on
  * SDA.
  *
- * This can happen anytime the i2cs controller has control of SDA and the master
+ * This can happen anytime the i2cp controller has control of SDA and the master
  * happens to fail and stops clocking.
  *
- * For example when the i2cs controller is:
+ * For example when the i2cp controller is:
  * 1) Transmitting an ACK for the slave address byte.
  * 2) Transmitting an ACK for a write transaction.
  * 3) Transmitting byte data for a read transaction.
@@ -230,14 +230,14 @@ static void poll_read_state(void)
 		 * stopped clocking while SDA is high, or we have polled in the
 		 * middle of a transaction where SDA happens to be high.
 		 */
-		i2cs_sda_low_count = 0;
+		i2cp_sda_low_count = 0;
 	} else {
 		/*
 		 * The master has stopped clocking while the slave is holding
 		 * SDA low, or we have polled in the middle of a transaction
 		 * where SDA happens to be low.
 		 */
-		i2cs_sda_low_count++;
+		i2cp_sda_low_count++;
 
 		/*
 		 * SDA line has been stuck low without any write transactions
@@ -245,15 +245,15 @@ static void poll_read_state(void)
 		 * Reinitialize the i2c interface (which will also restart this
 		 * polling function).
 		 */
-		if (i2cs_sda_low_count == READ_STATUS_CHECK_THRESHOLD) {
-			i2cs_sda_low_count = 0;
-			i2cs_read_recovery_count++;
-			CPRINTF("I2CS bus is stuck");
+		if (i2cp_sda_low_count == READ_STATUS_CHECK_THRESHOLD) {
+			i2cp_sda_low_count = 0;
+			i2cp_read_recovery_count++;
+			CPRINTF("I2CP bus is stuck");
 			/*
-			 * i2cs_register_write_complete_handler will call
+			 * i2cp_register_write_complete_handler will call
 			 * hook_call_deferred.
 			 */
-			i2cs_register_write_complete_handler(
+			i2cp_register_write_complete_handler(
 				write_complete_handler_);
 
 #ifdef CONFIG_FLASH_LOG
@@ -267,7 +267,7 @@ static void poll_read_state(void)
 }
 
 /* Process the 'end of a write cycle' interrupt. */
-void __attribute__((used)) _i2cs_write_complete_int(void)
+void __attribute__((used)) _i2cp_write_complete_int(void)
 {
 	/* Reset the IRQ condition. */
 	GWRITE_FIELD(I2CS, INT_STATE, INTR_WRITE_COMPLETE, 1);
@@ -308,7 +308,7 @@ void __attribute__((used)) _i2cs_write_complete_int(void)
 						  (last_write_pointer >> 2));
 
 			/* Save the next byte in the adaptation buffer. */
-			i2cs_buffer[bytes_processed] =
+			i2cp_buffer[bytes_processed] =
 				word_in_value >> (8 * (last_write_pointer & 3));
 
 			/* The pointer wraps at the register file size. */
@@ -318,24 +318,24 @@ void __attribute__((used)) _i2cs_write_complete_int(void)
 		}
 
 		/* Invoke the callback to process the message. */
-		write_complete_handler_(i2cs_buffer, bytes_processed);
+		write_complete_handler_(i2cp_buffer, bytes_processed);
 	}
 
 	/* The transaction is complete so the slave has released SDA. */
-	i2cs_sda_low_count = 0;
+	i2cp_sda_low_count = 0;
 
 	/*
 	 * Could be the end of a TPM trasaction. Set sleep to be reenabled in 1
 	 * second. If this is not the end of a TPM response, then sleep will be
-	 * disabled again in the next I2CS interrupt.
+	 * disabled again in the next I2CP interrupt.
 	 */
 	delay_sleep_by(1 * SECOND);
 	enable_sleep(SLEEP_MASK_I2C_PERIPH);
 }
 DECLARE_IRQ(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT,
-	    _i2cs_write_complete_int, 1);
+	    _i2cp_write_complete_int, 1);
 
-void i2cs_post_read_data(uint8_t byte_to_read)
+void i2cp_post_read_data(uint8_t byte_to_read)
 {
 	volatile uint32_t *value_addr;
 	uint32_t word_out_value;
@@ -356,7 +356,7 @@ void i2cs_post_read_data(uint8_t byte_to_read)
 	last_read_pointer = (last_read_pointer + 1) & REGISTER_FILE_MASK;
 }
 
-void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len)
+void i2cp_post_read_fill_fifo(uint8_t *buffer, size_t len)
 {
 	volatile uint32_t *value_addr;
 	uint32_t word_out_value;
@@ -417,14 +417,14 @@ void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len)
 	}
 }
 
-int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler)
+int i2cp_register_write_complete_handler(wr_complete_handler_f wc_handler)
 {
 	task_disable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT);
 
 	if (!wc_handler)
 		return 0;
 
-	i2cs_init();
+	i2cp_init();
 	write_complete_handler_ = wc_handler;
 	task_enable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT);
 
@@ -437,7 +437,7 @@ int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler)
 	return 0;
 }
 
-size_t i2cs_zero_read_fifo_buffer_depth(void)
+size_t i2cp_zero_read_fifo_buffer_depth(void)
 {
 	uint32_t hw_read_pointer;
 	size_t depth;
@@ -463,7 +463,7 @@ size_t i2cs_zero_read_fifo_buffer_depth(void)
 	return depth;
 }
 
-void i2cs_get_status(struct i2cs_status *status)
+void i2cp_get_status(struct i2cp_status *status)
 {
-	status->read_recovery_count = i2cs_read_recovery_count;
+	status->read_recovery_count = i2cp_read_recovery_count;
 }
diff --git a/chip/g/i2cs.h b/chip/g/i2cs.h
index 8fbc28187f..a3ca8641a6 100644
--- a/chip/g/i2cs.h
+++ b/chip/g/i2cs.h
@@ -13,22 +13,22 @@
  * two parameters: the address of the buffer containing received data and
  * number of bytes in the buffer.
  */
-typedef void (*wr_complete_handler_f)(void *i2cs_data, size_t i2cs_data_size);
+typedef void (*wr_complete_handler_f)(void *i2cp_data, size_t i2cp_data_size);
 
 /* Register the write complete interrupt handler. */
-int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler);
+int i2cp_register_write_complete_handler(wr_complete_handler_f wc_handler);
 
 /*
  * Post a byte for the master to read. Blend the byte into the appropriate
  * 4byte register of the master read register file.
  */
-void i2cs_post_read_data(uint8_t byte_to_read);
+void i2cp_post_read_data(uint8_t byte_to_read);
 
 /*
  * Configure the pinmux registers required to connect the I2CS interface. This
  * function is board specific and so it exists in the associated board.c file.
  */
-void i2cs_set_pinmux(void);
+void i2cp_set_pinmux(void);
 
 /*
  * Ensure no bytes are currently buffered in the I2CS READ fifo. This
@@ -38,7 +38,7 @@ void i2cs_set_pinmux(void);
  *
  * @returns: the number of bytes buffered when the function is called
  */
-size_t i2cs_zero_read_fifo_buffer_depth(void);
+size_t i2cp_zero_read_fifo_buffer_depth(void);
 
 /*
  * Write buffer of data into the I2CS HW read fifo. The function will operate a
@@ -48,7 +48,7 @@ size_t i2cs_zero_read_fifo_buffer_depth(void);
  * function diminish as the buffer size gets smaller and therefore not intended
  * to be used for <= 4 byte buffers.
  */
-void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len);
+void i2cp_post_read_fill_fifo(uint8_t *buffer, size_t len);
 
 /*
  * Provide upper layers with information with the I2CS interface
@@ -56,9 +56,9 @@ void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len);
  * counter of "hosed" i2c interface occurences, where i2c clocking stopped
  * while slave was transmitting a zero.
  */
-struct i2cs_status {
+struct i2cp_status {
 	uint16_t read_recovery_count;
 };
-void i2cs_get_status(struct i2cs_status *status);
+void i2cp_get_status(struct i2cp_status *status);
 
 #endif /* ! __CHIP_G_I2CS_H */
diff --git a/common/i2cs_tpm.c b/common/i2cs_tpm.c
index 27ee944c3c..0d5b8e7e00 100644
--- a/common/i2cs_tpm.c
+++ b/common/i2cs_tpm.c
@@ -13,9 +13,9 @@
 #include "tpm_registers.h"
 
 /*
- * This implements adaptaition layer between i2cs (i2c slave) port and TPM.
+ * This implements adaptaition layer between i2cp (i2c periph) port and TPM.
  *
- * The adaptation layer is stateless, it processes the i2cs "write complete"
+ * The adaptation layer is stateless, it processes the i2cp "write complete"
  * interrupts on the interrupt context.
  *
  * Each "write complete" interrupt is associated with some data receved from
@@ -80,10 +80,10 @@ static const struct i2c_tpm_reg_map i2c_to_tpm[] = {
 	{0x1c, 4, 0xfe0}, /* TPM_BOARD_CFG */
 };
 
-/* Used to track number of times i2cs hw read fifo was adjusted */
-static uint32_t i2cs_fifo_adjust_count;
+/* Used to track number of times i2cp hw read fifo was adjusted */
+static uint32_t i2cp_fifo_adjust_count;
 /* Used to track number of write mismatch errors */
-static uint32_t i2cs_write_error_count;
+static uint32_t i2cp_write_error_count;
 
 static bool int_ap_extension_enabled_;
 
@@ -102,15 +102,15 @@ static void process_read_access(uint16_t reg_size,
 		tpm_register_get(tpm_reg, reg_value, reg_size);
 		/*
 		 * For 1 or 4 byte register reads there should not be any data
-		 * buffered in the i2cs hw read fifo. This function will check
+		 * buffered in the i2cp hw read fifo. This function will check
 		 * the current fifo queue depth and if non-zero, will adjust the
 		 * fw pointer to force it to 0.
 		 */
-		if (i2cs_zero_read_fifo_buffer_depth())
+		if (i2cp_zero_read_fifo_buffer_depth())
 			/* Count each instance that fifo was adjusted */
-			i2cs_fifo_adjust_count++;
+			i2cp_fifo_adjust_count++;
 		for (i = 0; i < reg_size; i++)
-			i2cs_post_read_data(reg_value[i]);
+			i2cp_post_read_data(reg_value[i]);
 		return;
 	}
 
@@ -130,11 +130,11 @@ static void process_read_access(uint16_t reg_size,
 	data -= 1;
 	tpm_register_get(tpm_reg, data, reg_size);
 	/* Transfer TPM fifo data to the I2CS HW fifo */
-	i2cs_post_read_fill_fifo(data, reg_size);
+	i2cp_post_read_fill_fifo(data, reg_size);
 }
 
 static void process_write_access(uint16_t reg_size, uint16_t tpm_reg,
-				 uint8_t *data, size_t i2cs_data_size)
+				 uint8_t *data, size_t i2cp_data_size)
 {
 	/* This is an actual write request. */
 
@@ -143,12 +143,12 @@ static void process_write_access(uint16_t reg_size, uint16_t tpm_reg,
 	 * down directly
 	 */
 	if (reg_size == 0) {
-		tpm_register_put(tpm_reg, data, i2cs_data_size);
+		tpm_register_put(tpm_reg, data, i2cp_data_size);
 		return;
 	}
 
-	if (i2cs_data_size != reg_size) {
-		i2cs_write_error_count++;
+	if (i2cp_data_size != reg_size) {
+		i2cp_write_error_count++;
 		return;
 	}
 
@@ -156,15 +156,15 @@ static void process_write_access(uint16_t reg_size, uint16_t tpm_reg,
 	tpm_register_put(tpm_reg, data, reg_size);
 }
 
-static void wr_complete_handler(void *i2cs_data, size_t i2cs_data_size)
+static void wr_complete_handler(void *i2cp_data, size_t i2cp_data_size)
 {
 	size_t i;
 	uint16_t tpm_reg;
-	uint8_t *data = i2cs_data;
+	uint8_t *data = i2cp_data;
 	const struct i2c_tpm_reg_map *i2c_reg_entry = NULL;
 	uint16_t reg_size;
 
-	if (i2cs_data_size < 1) {
+	if (i2cp_data_size < 1) {
 		/*
 		 * This is a misformatted request, should never happen, just
 		 * ignore it.
@@ -196,14 +196,14 @@ static void wr_complete_handler(void *i2cs_data, size_t i2cs_data_size)
 	tpm_reg = i2c_reg_entry->tpm_address;
 	reg_size = i2c_reg_entry->reg_size;
 
-	i2cs_data_size--;
+	i2cp_data_size--;
 	data++;
 
-	if (!i2cs_data_size)
+	if (!i2cp_data_size)
 		process_read_access(reg_size, tpm_reg, data);
 	else
 		process_write_access(reg_size, tpm_reg,
-				     data, i2cs_data_size);
+				     data, i2cp_data_size);
 
 	if (assert_int_ap()) {
 		gpio_enable_interrupt(GPIO_MONITOR_I2CS_SDA);
@@ -222,69 +222,69 @@ static void wr_complete_handler(void *i2cs_data, size_t i2cs_data_size)
 	gpio_set_level(GPIO_INT_AP_L, 1);
 }
 
-void i2cs_sda_isr(enum gpio_signal signal)
+void i2cp_sda_isr(enum gpio_signal signal)
 {
 	gpio_disable_interrupt(GPIO_MONITOR_I2CS_SDA);
 
 	deassert_int_ap();
 }
 
-static void i2cs_if_stop(void)
+static void i2cp_if_stop(void)
 {
 	if (int_ap_extension_enabled_)
 		int_ap_extension_stop_pulse();
 
-	i2cs_register_write_complete_handler(NULL);
+	i2cp_register_write_complete_handler(NULL);
 }
 
-static void i2cs_if_start(void)
+static void i2cp_if_start(void)
 {
-	i2cs_register_write_complete_handler(wr_complete_handler);
+	i2cp_register_write_complete_handler(wr_complete_handler);
 }
 
 /* Function that sets up for I2CS to enable INT_AP_L extension. */
-static void i2cs_int_ap_extension_enable_(void)
+static void i2cp_int_ap_extension_enable_(void)
 {
 	int_ap_extension_enabled_ = true;
 }
 
-static void i2cs_if_register(void)
+static void i2cp_if_register(void)
 {
 	if (!board_tpm_uses_i2c())
 		return;
 
-	tpm_register_interface(i2cs_if_start, i2cs_if_stop);
-	i2cs_fifo_adjust_count = 0;
-	i2cs_write_error_count = 0;
+	tpm_register_interface(i2cp_if_start, i2cp_if_stop);
+	i2cp_fifo_adjust_count = 0;
+	i2cp_write_error_count = 0;
 
-	int_ap_register(i2cs_int_ap_extension_enable_);
+	int_ap_register(i2cp_int_ap_extension_enable_);
 }
-DECLARE_HOOK(HOOK_INIT, i2cs_if_register, HOOK_PRIO_INIT_CR50_BOARD - 1);
+DECLARE_HOOK(HOOK_INIT, i2cp_if_register, HOOK_PRIO_INIT_CR50_BOARD - 1);
 
-static int command_i2cs(int argc, char **argv)
+static int command_i2cp(int argc, char **argv)
 {
 	static uint16_t base_read_recovery_count;
-	struct i2cs_status status;
+	struct i2cp_status status;
 
-	i2cs_get_status(&status);
+	i2cp_get_status(&status);
 
-	ccprintf("rd fifo adjust cnt = %d\n", i2cs_fifo_adjust_count);
-	ccprintf("wr mismatch cnt = %d\n", i2cs_write_error_count);
+	ccprintf("rd fifo adjust cnt = %d\n", i2cp_fifo_adjust_count);
+	ccprintf("wr mismatch cnt = %d\n", i2cp_write_error_count);
 	ccprintf("read recovered cnt = %d\n", status.read_recovery_count
 		 - base_read_recovery_count);
 	if (argc < 2)
 		return EC_SUCCESS;
 
 	if (!strcasecmp(argv[1], "reset")) {
-		i2cs_fifo_adjust_count = 0;
-		i2cs_write_error_count = 0;
+		i2cp_fifo_adjust_count = 0;
+		i2cp_write_error_count = 0;
 		base_read_recovery_count = status.read_recovery_count;
-		ccprintf("i2cs error counts reset\n");
+		ccprintf("i2cp error counts reset\n");
 	} else
 		return EC_ERROR_PARAM1;
 
 	return EC_SUCCESS;
 }
-DECLARE_SAFE_CONSOLE_COMMAND(i2cstpm, command_i2cs,
+DECLARE_SAFE_CONSOLE_COMMAND(i2cptpm, command_i2cp,
 			     "reset",
 			     "Display fifo adjust count");
diff --git a/common/tpm_registers.c b/common/tpm_registers.c
index c73a38ab1e..b40dd0758a 100644
--- a/common/tpm_registers.c
+++ b/common/tpm_registers.c
@@ -602,8 +602,8 @@ static void tpm_init(void)
 	set_tpm_state(tpm_state_idle);
 	tpm_.regs.access = tpm_reg_valid_sts;
 	/*
-	 * I2CS writes must limit the burstsize to 63 for fifo writes to work
-	 * properly. For I2CS fifo writes the first byte is the I2C TPM address
+	 * I2CP writes must limit the burstsize to 63 for fifo writes to work
+	 * properly. For I2CP fifo writes the first byte is the I2C TPM address
 	 * and the next up to 62 bytes are the data to write to that register.
 	 */
 	tpm_.regs.sts = (tpm_family_tpm2 << tpm_family_shift) |
diff --git a/include/i2c.h b/include/i2c.h
index 0121bfb413..83cd05b77a 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -524,6 +524,6 @@ void i2c_trace_notify(int port, uint16_t periph_addr_flags,
  * Its role is to detect any transaction start during INT_AP_L
  *  assertion and to deassert INT_AP_L.
  */
-void i2cs_sda_isr(enum gpio_signal signal);
+void i2cp_sda_isr(enum gpio_signal signal);
 
 #endif  /* __CROS_EC_I2C_H */