diff options
| author | Edward Hill <ecgh@chromium.org> | 2019-10-15 13:37:10 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-10-16 01:16:38 +0000 |
| commit | 7508a9a69a061dd74fb0d9d83c8ebf17335a5c38 (patch) | |
| tree | 962681af12f744e3c42d4fa96752811228e4113e | |
| parent | d673ee383c432a85901de1d5ad3cf937a484a240 (diff) | |
| download | chrome-ec-7508a9a69a061dd74fb0d9d83c8ebf17335a5c38.tar.gz | |
NPCX ESPI: fix some typos
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I7f9089ce8028f12a94d8e73dd58a5bb36ebc614f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1862090
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
| -rw-r--r-- | chip/npcx/espi.c | 4 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index e6d0a37bac..b930579c70 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -611,11 +611,11 @@ void espi_init(void) NPCX_ESPICFG |= ESPI_SUPP_CH_ALL; /* Support all I/O modes */ - SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FILED, + SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, NPCX_ESPI_IO_MODE_ALL); /* Set eSPI speed to max supported */ - SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FILED, + SET_FIELD(NPCX_ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, NPCX_ESPI_MAXFREQ_MAX); /* Configure Master-to-Slave Virtual Wire indexes (Inputs) */ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3a63f6ccb7..3716b18dfe 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1541,7 +1541,7 @@ enum ITIM16_MODULE_T { #define NPCX_FLASHTXWRHEAD REG32(NPCX_ESPI_BASE_ADDR + 0X2C) #define NPCX_FLASHCFG REG32(NPCX_ESPI_BASE_ADDR + 0X34) #define NPCX_FLASHCTL REG32(NPCX_ESPI_BASE_ADDR + 0X38) -#define NPCX_ESPIIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C) +#define NPCX_ESPIERR REG32(NPCX_ESPI_BASE_ADDR + 0X3C) /* eSPI Virtual Wire channel registers */ #define NPCX_VWEVSM(n) REG32(NPCX_ESPI_BASE_ADDR + 0x100 + (4*(n))) @@ -1553,8 +1553,8 @@ enum ITIM16_MODULE_T { #define NPCX_ESPICFG_VWCHANEN 1 #define NPCX_ESPICFG_OOBCHANEN 2 #define NPCX_ESPICFG_FLASHCHANEN 3 -#define NPCX_ESPICFG_IOMODE_FILED FIELD(8, 9) -#define NPCX_ESPICFG_MAXFREQ_FILED FIELD(10, 12) +#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 9) +#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 12) #define NPCX_ESPICFG_PCCHN_SUPP 24 #define NPCX_ESPICFG_VWCHN_SUPP 25 #define NPCX_ESPICFG_OOBCHN_SUPP 26 @@ -1688,7 +1688,7 @@ enum ITIM16_MODULE_T { (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ ESPI_VW_TYPE_NONE) -/* Bit filed manipulation for VWEVMS Value */ +/* Bit field manipulation for VWEVMS Value */ #define VWEVMS_INX(i) ((i<<8) & 0x00007F00) #define VWEVMS_INX_EN(n) ((n<<15) & 0x00008000) #define VWEVMS_PLTRST_EN(p) ((p<<17) & 0x00020000) @@ -1705,7 +1705,7 @@ enum ITIM16_MODULE_T { VWEVMS_ESPIRST_EN(r)) #define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00)>>8)) -/* Bit filed manipulation for VWEVSM Value */ +/* Bit field manipulation for VWEVSM Value */ #define VWEVSM_VALID_N(v) ((v<<4) & 0x000000F0) #define VWEVSM_INX(i) ((i<<8) & 0x00007F00) #define VWEVSM_INX_EN(n) ((n<<15) & 0x00008000) @@ -1722,7 +1722,7 @@ enum ITIM16_MODULE_T { #define SMI_STATUS_MASK ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002)) /* * Read SCI VWire status from VWEVSM(offset 2) register. - * Left shift 2 to meet the SCIB filed in HIPMIC register. + * Left shift 2 to meet the SCIB field in HIPMIC register. */ #define SCI_STATUS_MASK (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2) #define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) |