cleanup: Use appropriate image geometry CONFIGs

- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.

BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None

Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269

31 files changed, 121 insertions, 359 deletions

diff --git a/board/zinger/board.h b/board/zinger/board.h
index ba1709850b..64a4a22606 100644
--- a/board/zinger/board.h
+++ b/board/zinger/board.h
@@ -39,6 +39,9 @@
 #undef CONFIG_DEBUG_STACK_OVERFLOW
 #undef CONFIG_FLASH
 #undef CONFIG_FMAP
+/* Not using pstate but keep some space for the public key */
+#undef  CONFIG_FW_PSTATE_SIZE
+#define CONFIG_FW_PSTATE_SIZE 544
 #define CONFIG_HIBERNATE
 #define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP1
 #define CONFIG_HW_CRC
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
index d6dfe8fa13..79b44f4ddd 100644
--- a/chip/g/config_chip.h
+++ b/chip/g/config_chip.h
@@ -28,10 +28,8 @@
 /* #define CONFIG_FLASH_PHYSICAL_SIZE (512 * 1024) */
 #define CONFIG_FLASH_PHYSICAL_SIZE (256 * 1024)
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (128 * 1024)
 /* Compute the rest of the flash params from these */
-#include "config_std_flash.h"
+#include "config_std_internal_flash.h"
 
 /* Interval between HOOK_TICK notifications */
 #define HOOK_TICK_INTERVAL_MS 500
diff --git a/chip/g/config_std_flash.h b/chip/g/config_std_flash.h
deleted file mode 100644
index 86df29c4e4..0000000000
--- a/chip/g/config_std_flash.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_STD_FLASH_H
-#define __CROS_EC_CONFIG_STD_FLASH_H
-
-/* RO firmware must start at beginning of flash */
-#define CONFIG_RO_MEM_OFF		0
-
-/*
- * The EC uses the one bank of flash to emulate a SPI-like write protect
- * register with persistent state.
- */
-#define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
-
-/* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
-					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
-#define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
-
-/* RW firmware is one firmware image offset from the start */
-#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
-
-/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
-
-#endif	/* __CROS_EC_CONFIG_STD_FLASH_H */
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
index df84143883..b809134e83 100644
--- a/chip/host/config_chip.h
+++ b/chip/host/config_chip.h
@@ -10,7 +10,6 @@
 
 /* Memory mapping */
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
 
 #define CONFIG_FLASH_BASE       ((uintptr_t)__host_flash)
@@ -23,22 +22,7 @@ extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
 
 #define CONFIG_FPU
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put this after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_OFF    CONFIG_RO_SIZE
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#include "config_std_internal_flash.h"
 
 /* Maximum number of deferrable functions */
 #define DEFERRABLE_MAX_COUNT 8
diff --git a/chip/host/flash.c b/chip/host/flash.c
index 2be40b37df..77639218aa 100644
--- a/chip/host/flash.c
+++ b/chip/host/flash.c
@@ -114,7 +114,7 @@ uint32_t flash_physical_get_protect_flags(void)
 
 int flash_physical_protect_now(int all)
 {
-	memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : RO_BANK_COUNT);
+	memset(__host_flash_protect, 1, all ? PHYSICAL_BANKS : WP_BANK_COUNT);
 	return EC_SUCCESS;
 }
 
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 5caf50562b..2c433262c9 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -56,33 +56,7 @@
 /****************************************************************************/
 /* Define our flash layout. */
 
-/* Size of one firmware image in flash */
-#ifndef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE		(CONFIG_FLASH_PHYSICAL_SIZE / 2)
-#endif
-
-/* RO firmware must start at beginning of flash */
-#define CONFIG_RO_MEM_OFF		0
-
-/*
- * The EC uses the one bank of flash to emulate a SPI-like write protect
- * register with persistent state.
- */
-#define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
-
-/* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
-					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
-#define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
-
-/* RW firmware is one firmware image offset from the start */
-#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
-
-/* TODO: why 2 sets of configs with the same numbers? */
-#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
+#include "config_std_internal_flash.h"
 
 /****************************************************************************/
 /* Customize the build */
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index 433510d460..4bf6c75a18 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -69,33 +69,7 @@
 /****************************************************************************/
 /* Define our flash layout. */
 
-/* Size of one firmware image in flash */
-#ifndef CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_IMAGE_SIZE		(CONFIG_FLASH_PHYSICAL_SIZE / 2)
-#endif
-
-/* RO firmware must start at beginning of flash */
-#define CONFIG_RO_MEM_OFF		0
-
-/*
- * The EC uses the one bank of flash to emulate a SPI-like write protect
- * register with persistent state.
- */
-#define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
-
-/* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
-					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
-#define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
-
-/* RW firmware is one firmware image offset from the start */
-#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
-
-/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
+#include "config_std_internal_flash.h"
 
 /****************************************************************************/
 /* Lock the boot configuration to prevent brickage. */
diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c
index 6c6a01072b..6a5634f5b3 100644
--- a/chip/lm4/flash.c
+++ b/chip/lm4/flash.c
@@ -195,13 +195,9 @@ int flash_physical_protect_now(int all)
 		all_protected = 1;
 		protect_banks(0, CONFIG_FLASH_PHYSICAL_SIZE /
 			      CONFIG_FLASH_BANK_SIZE);
-	} else {
-		/* Protect the read-only section and persistent state */
-		protect_banks(RO_BANK_OFFSET, RO_BANK_COUNT);
-#ifdef PSTATE_BANK
-		protect_banks(PSTATE_BANK, 1);
-#endif
-	}
+	} else
+		/* Protect the WP region (read-only section and pstate) */
+		protect_banks(WP_BANK_OFFSET, WP_BANK_COUNT);
 
 	return EC_SUCCESS;
 }
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index ffdf0e56d4..aaf4feb6b8 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -131,7 +131,6 @@ which contains Loader and RO Images */
      located at the end of the flash */
 #define CONFIG_FLASH_BASE_SPI	(CONFIG_SPI_FLASH_SIZE - (0x40000))
 
-#define CONFIG_RO_WP_SPI_OFF		0x20000
 #define CONFIG_RO_STORAGE_OFF		0x20000
 #define CONFIG_RW_STORAGE_OFF		0
 #define CONFIG_RO_IMAGE_FLASHADDR	(CONFIG_FLASH_BASE_SPI +	\
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
index 78beb72429..92a7dacb33 100644
--- a/chip/mec1322/flash.c
+++ b/chip/mec1322/flash.c
@@ -123,8 +123,8 @@ int flash_physical_protect_now(int all)
 		offset = 0;
 		size = CONFIG_FLASH_PHYSICAL_SIZE;
 	} else {
-		offset = CONFIG_RO_MEM_OFF;
-		size = CONFIG_RO_SIZE;
+		offset = CONFIG_WP_OFF;
+		size = CONFIG_WP_SIZE;
 	}
 
 	spi_enable(1);
@@ -145,9 +145,9 @@ uint32_t flash_physical_get_protect_flags(void)
 	uint32_t flags = 0;
 
 	spi_enable(1);
-	if (spi_flash_check_protect(CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE)) {
+	if (spi_flash_check_protect(CONFIG_RO_STORAGE_OFF, CONFIG_RO_SIZE)) {
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-		if (spi_flash_check_protect(CONFIG_RW_MEM_OFF,
+		if (spi_flash_check_protect(CONFIG_RW_STORAGE_OFF,
 					    CONFIG_RW_SIZE))
 			flags |= EC_FLASH_PROTECT_ALL_NOW;
 	}
@@ -206,8 +206,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
 		offset = size = 0;
 		break;
 	case FLASH_WP_RO:
-		offset = CONFIG_RO_MEM_OFF;
-		size = CONFIG_RO_SIZE;
+		offset = CONFIG_WP_OFF;
+		size = CONFIG_WP_SIZE;
 		break;
 	case FLASH_WP_ALL:
 		offset = 0;
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 560be8e6c9..272c5eebed 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -76,15 +76,16 @@
 
 /* RO firmware offset of flash */
 #define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_STORAGE_OFF   0
 #define CONFIG_RO_SIZE          CONFIG_FW_IMAGE_SIZE
 #define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware is one firmware image offset from the start */
 #define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_STORAGE_OFF   CONFIG_FW_IMAGE_SIZE
 #define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
 
-/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_OFF           CONFIG_RO_STORAGE_OFF
 #define CONFIG_WP_SIZE          CONFIG_RO_SIZE
 
 /*
diff --git a/chip/npcx/flash.c b/chip/npcx/flash.c
index e551b0c977..30091a39f0 100644
--- a/chip/npcx/flash.c
+++ b/chip/npcx/flash.c
@@ -602,9 +602,9 @@ uint32_t flash_physical_get_protect_flags(void)
 {
 	uint32_t flags = 0;
 
-	/* Check if RO section is protected in status register */
-	if (flash_check_prot_reg(RO_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
-				 RO_BANK_COUNT*CONFIG_FLASH_BANK_SIZE))
+	/* Check if WP region is protected in status register */
+	if (flash_check_prot_reg(WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
+				 WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE))
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT;
 
 	/*
@@ -639,8 +639,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
 	case FLASH_WP_RO:
 		/* Protect read-only */
 		return flash_write_prot_reg(
-			    RO_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
-			    RO_BANK_COUNT*CONFIG_FLASH_BANK_SIZE);
+			    WP_BANK_OFFSET*CONFIG_FLASH_BANK_SIZE,
+			    WP_BANK_COUNT*CONFIG_FLASH_BANK_SIZE);
 	case FLASH_WP_ALL:
 	default:
 		return EC_ERROR_INVAL;
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
index 104fceb0ca..78ee610601 100644
--- a/chip/nrf51/config_chip.h
+++ b/chip/nrf51/config_chip.h
@@ -41,33 +41,16 @@
 /* Flash mapping */
 #define CONFIG_FLASH_BASE       0x00000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (128 * 1024)
-
-/* Define the RO/RW offset */
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect
- * region contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
+#include "config_std_internal_flash.h"
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
 
 /* Not that much RAM, set to smaller */
-#undef CONFIG_UART_TX_BUF_SIZE
+#undef  CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 1024
 
-
 #endif /* __CROS_EC_CONFIG_CHIP_H */
 
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index 2bd4da74cb..18c8806908 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00008000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -17,28 +16,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00001000
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (16 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#if defined(BOARD_ZINGER) || defined(BOARD_MINIMUFFIN)
-/* Not using pstate but keep some space for the public key */
-#define CONFIG_FW_PSTATE_SIZE   544
-#else
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#endif
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
 
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index d1d01824e9..45b340355c 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE (128 * 1024)
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -17,23 +16,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00004000
 
-/* Size of the first firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (CONFIG_FLASH_SIZE / 2)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_FW_IMAGE_SIZE)
-#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
 
diff --git a/chip/stm32/config-stm32f100.h b/chip/stm32/config-stm32f100.h
index 297da6b238..09a638c28f 100644
--- a/chip/stm32/config-stm32f100.h
+++ b/chip/stm32/config-stm32f100.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -17,23 +16,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00002000
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 61
 
diff --git a/chip/stm32/config-stm32f10x.h b/chip/stm32/config-stm32f10x.h
index e638fdd377..e568d7ea87 100644
--- a/chip/stm32/config-stm32f10x.h
+++ b/chip/stm32/config-stm32f10x.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -17,22 +16,5 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         (10 * 1024)
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 68
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index 05f50f9cdd..42857af2c9 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x2000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* minimum write size */
@@ -17,23 +16,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00008000
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (128 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 81
 
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index ae063be847..e751e396cd 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
 
@@ -26,23 +25,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00002800
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_RO_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect
- * region contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE  CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF   (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
 
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index 4e5a9dca06..dc897253aa 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0100  /* erase bank size */
 
@@ -26,23 +25,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00004000
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_RO_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect
- * region contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
 
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h
index 85a78af6d5..540855c724 100644
--- a/chip/stm32/config-stm32ts60.h
+++ b/chip/stm32/config-stm32ts60.h
@@ -6,7 +6,6 @@
 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
 #define CONFIG_FLASH_PHYSICAL_SIZE 0x0010000 /* Actually 0x8000 */
-#define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000  /* TODO */
 #define CONFIG_FLASH_ERASE_SIZE 0x0400  /* TODO erase bank size */
 #define CONFIG_FLASH_WRITE_SIZE 0x0002  /* TODO minimum write size */
@@ -17,23 +16,6 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00002800
 
-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (32 * 1024)
-
-#define CONFIG_RO_MEM_OFF       0
-#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
-#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
-#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
-
-/*
- * Put pstate after RO to give RW more space and make RO write protect region
- * contiguous.
- */
-#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
-
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 59
 
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index a8814df217..541b50d8a4 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -43,6 +43,8 @@
 #error "Unsupported chip variant"
 #endif
 
+#include "config_std_internal_flash.h"
+
 /* System stack size */
 #define CONFIG_STACK_SIZE 1024
 
diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c
index 1fa809a449..090e223ec7 100644
--- a/chip/stm32/flash-f.c
+++ b/chip/stm32/flash-f.c
@@ -342,12 +342,12 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
 	for (i = 0; i < 4; ++i)
 		original_val[i] = val[i] = read_optb(i * 2 + 8);
 
-	for (block = RO_BANK_OFFSET;
-	     block < RO_BANK_OFFSET + PHYSICAL_BANKS;
+	for (block = WP_BANK_OFFSET;
+	     block < WP_BANK_OFFSET + PHYSICAL_BANKS;
 	     block++) {
 		int byte_off = STM32_OPTB_WRP_OFF(block/8) / 2 - 4;
 
-		if (block >= RO_BANK_OFFSET + RO_BANK_COUNT + PSTATE_BANK_COUNT)
+		if (block >= WP_BANK_OFFSET + WP_BANK_COUNT)
 			cur_range = FLASH_WP_ALL;
 		else
 			cur_range = FLASH_WP_RO;
@@ -384,9 +384,8 @@ static int registers_need_reset(void)
 	uint32_t flags = flash_get_protect();
 	int i;
 	int ro_at_boot = (flags & EC_FLASH_PROTECT_RO_AT_BOOT) ? 1 : 0;
-	int ro_wp_region_start = RO_BANK_OFFSET;
-	int ro_wp_region_end =
-		RO_BANK_OFFSET + RO_BANK_COUNT + PSTATE_BANK_COUNT;
+	int ro_wp_region_start = WP_BANK_OFFSET;
+	int ro_wp_region_end = WP_BANK_OFFSET + WP_BANK_COUNT;
 
 	for (i = ro_wp_region_start; i < ro_wp_region_end; i++)
 		if (flash_physical_get_protect_at_boot(i) != ro_at_boot)
diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c
index 106e436c80..5a84d31f46 100644
--- a/chip/stm32/flash-stm32l.c
+++ b/chip/stm32/flash-stm32l.c
@@ -319,8 +319,7 @@ int flash_physical_get_protect(int block)
 int flash_physical_protect_at_boot(enum flash_wp_range range)
 {
 	uint32_t prot;
-	uint32_t mask = ((1 << (RO_BANK_COUNT + PSTATE_BANK_COUNT)) - 1)
-			<< RO_BANK_OFFSET;
+	uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET;
 	int rv;
 
 	if (range == FLASH_WP_ALL)
diff --git a/common/flash.c b/common/flash.c
index 302dae0f08..6d903eca95 100644
--- a/common/flash.c
+++ b/common/flash.c
@@ -400,17 +400,11 @@ uint32_t flash_get_protect(void)
 	/* Scan flash protection */
 	for (i = 0; i < PHYSICAL_BANKS; i++) {
 		/* Is this bank part of RO */
-		int is_ro = (i >= RO_BANK_OFFSET &&
-			     i < RO_BANK_OFFSET + RO_BANK_COUNT) ? 1 : 0;
-		int bank_flag;
-
-#if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)
-		/* PSTATE acts like part of RO; protected at same time */
-		if (i >= PSTATE_BANK && i < PSTATE_BANK + PSTATE_BANK_COUNT)
-			is_ro = 1;
-#endif
-		bank_flag = (is_ro ? EC_FLASH_PROTECT_RO_NOW :
-			     EC_FLASH_PROTECT_ALL_NOW);
+		int is_ro = (i >= WP_BANK_OFFSET &&
+			     i < WP_BANK_OFFSET + WP_BANK_COUNT) ? 1 : 0;
+
+		int bank_flag = (is_ro ? EC_FLASH_PROTECT_RO_NOW :
+				EC_FLASH_PROTECT_ALL_NOW);
 
 		if (flash_physical_get_protect(i)) {
 			/* At least one bank in the region is protected */
@@ -879,11 +873,11 @@ static int flash_command_region_info(struct host_cmd_handler_args *args)
 
 	switch (p->region) {
 	case EC_FLASH_REGION_RO:
-		r->offset = CONFIG_RO_MEM_OFF;
+		r->offset = CONFIG_RO_STORAGE_OFF;
 		r->size = CONFIG_RO_SIZE;
 		break;
 	case EC_FLASH_REGION_RW:
-		r->offset = CONFIG_RW_MEM_OFF;
+		r->offset = CONFIG_RW_STORAGE_OFF;
 		r->size = CONFIG_RW_SIZE;
 		break;
 	case EC_FLASH_REGION_WP_RO:
diff --git a/common/fmap.c b/common/fmap.c
index 0785dc30d7..16b45c9db6 100644
--- a/common/fmap.c
+++ b/common/fmap.c
@@ -17,10 +17,10 @@
 #define FMAP_VER_MINOR 0
 
 /*
- * For address containing CONFIG_FLASH_BASE (symbols in *.lds.S and variable),
- * this computes the offset to the start of flash.
+ * For address containing CONFIG_FLASH_BASE (symbols in *.RO.lds.S and
+ * variable), this computes the offset to the start of the image on flash.
  */
-#define RELATIVE(addr) ((addr) - CONFIG_FLASH_BASE)
+#define RELATIVE_RO(addr) ((addr) - CONFIG_FLASH_BASE - CONFIG_RO_MEM_OFF)
 
 struct fmap_header {
 	char        fmap_signature[FMAP_SIGNATURE_SIZE];
@@ -69,14 +69,14 @@ const struct _ec_fmap {
 			 * volatile data (ex, calibration results).
 			 */
 			.area_name = "EC_RO",
-			.area_offset = CONFIG_RO_MEM_OFF,
+			.area_offset = CONFIG_RO_STORAGE_OFF,
 			.area_size = CONFIG_RO_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
 		{
 			/* (Optional) RO firmware code. */
 			.area_name = "FR_MAIN",
-			.area_offset = CONFIG_RO_MEM_OFF,
+			.area_offset = CONFIG_RO_STORAGE_OFF,
 			.area_size = CONFIG_RO_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -86,8 +86,8 @@ const struct _ec_fmap {
 			 * ASCII, and padded with \0.
 			 */
 			.area_name = "RO_FRID",
-			.area_offset = CONFIG_RO_MEM_OFF +
-				RELATIVE((uint32_t)__version_struct_offset) +
+			.area_offset = CONFIG_RO_STORAGE_OFF +
+				RELATIVE_RO((uint32_t)__version_struct_offset) +
 				offsetof(struct version_struct,  version),
 			.area_size = sizeof(version_data.version),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
@@ -96,8 +96,8 @@ const struct _ec_fmap {
 		/* Other RO stuff: FMAP, WP, KEYS, etc. */
 		{
 			.area_name = "FMAP",
-			.area_offset = CONFIG_RO_MEM_OFF +
-				RELATIVE((uint32_t)&ec_fmap),
+			.area_offset = CONFIG_RO_STORAGE_OFF +
+				RELATIVE_RO((uint32_t)&ec_fmap),
 			.area_size = sizeof(ec_fmap),
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -117,7 +117,7 @@ const struct _ec_fmap {
 		{
 			 /* The range of RW firmware to be auto-updated. */
 			.area_name = "EC_RW",
-			.area_offset = CONFIG_RW_MEM_OFF,
+			.area_offset = CONFIG_RW_STORAGE_OFF,
 			.area_size = CONFIG_RW_SIZE,
 			.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
 		},
@@ -125,10 +125,13 @@ const struct _ec_fmap {
 			/*
 			 * RW firmware version ID. Must be NULL terminated
 			 * ASCII, and padded with \0.
+			 * TODO: Get the relative offset of
+			 * __version_struct_offset within our RW image to
+			 * accomodate image asymmetry.
 			 */
 			.area_name = "RW_FWID",
-			.area_offset = CONFIG_RW_MEM_OFF +
-				RELATIVE((uint32_t)__version_struct_offset) +
+			.area_offset = CONFIG_RW_STORAGE_OFF +
+				RELATIVE_RO((uint32_t)__version_struct_offset) +
 				offsetof(struct version_struct,  version),
 			.area_size = sizeof(version_data.version),
 			.area_flags = FMAP_AREA_STATIC,
diff --git a/common/system.c b/common/system.c
index abb62e331b..a144935c4b 100644
--- a/common/system.c
+++ b/common/system.c
@@ -357,11 +357,11 @@ test_mockable int system_unsafe_to_overwrite(uint32_t offset, uint32_t size)
 
 	switch (system_get_image_copy()) {
 	case SYSTEM_IMAGE_RO:
-		r_offset = CONFIG_RO_MEM_OFF;
+		r_offset = CONFIG_RO_STORAGE_OFF;
 		r_size = CONFIG_RO_SIZE;
 		break;
 	case SYSTEM_IMAGE_RW:
-		r_offset = CONFIG_RW_MEM_OFF;
+		r_offset = CONFIG_RW_STORAGE_OFF;
 		r_size = CONFIG_RW_SIZE;
 		break;
 	default:
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c
index 0ed69cb8a7..4ab8f870a3 100644
--- a/common/usb_pd_policy.c
+++ b/common/usb_pd_policy.c
@@ -819,7 +819,7 @@ DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE,
 
 #endif
 
-#define FW_RW_END (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)
+#define FW_RW_END (CONFIG_RW_STORAGE_OFF + CONFIG_RW_SIZE)
 
 uint8_t *flash_hash_rw(void)
 {
@@ -881,14 +881,14 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
 		if (system_get_image_copy() != SYSTEM_IMAGE_RO)
 			break;
 		pd_log_event(PD_EVENT_ACC_RW_ERASE, 0, 0, NULL);
-		flash_offset = CONFIG_RW_MEM_OFF;
-		flash_physical_erase(CONFIG_RW_MEM_OFF, CONFIG_RW_SIZE);
+		flash_offset = CONFIG_RW_STORAGE_OFF;
+		flash_physical_erase(CONFIG_RW_STORAGE_OFF, CONFIG_RW_SIZE);
 		rw_flash_changed = 1;
 		break;
 	case VDO_CMD_FLASH_WRITE:
 		/* do not kill the code under our feet */
 		if ((system_get_image_copy() != SYSTEM_IMAGE_RO) ||
-		    (flash_offset < CONFIG_RW_MEM_OFF))
+		    (flash_offset < CONFIG_RW_STORAGE_OFF))
 			break;
 		flash_physical_write(flash_offset, 4*(cnt - 1),
 				     (const char *)(payload+1));
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
new file mode 100644
index 0000000000..c0df3d4199
--- /dev/null
+++ b/include/config_std_internal_flash.h
@@ -0,0 +1,38 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
+#define __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H
+
+/*
+ * Standard memory-mapped flash layout:
+ * - RO image starts at the beginning of flash.
+ * - PSTATE immediately follows the RO image.
+ * - RW image starts at the second half of flash.
+ * - WP region consists of the first half of flash (RO + PSTATE).
+ */
+
+/*
+ * The EC uses the one bank of flash to emulate a SPI-like write protect
+ * register with persistent state.
+ */
+#define CONFIG_FW_PSTATE_SIZE	CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF	(CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+
+/* Size of one firmware image in flash */
+#define CONFIG_FW_IMAGE_SIZE	(CONFIG_FLASH_PHYSICAL_SIZE / 2)
+#define CONFIG_FLASH_SIZE	CONFIG_FLASH_PHYSICAL_SIZE
+
+#define CONFIG_RO_MEM_OFF	0
+#define CONFIG_RO_STORAGE_OFF	0
+#define CONFIG_RO_SIZE		(CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF	CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_STORAGE_OFF	CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE		CONFIG_FW_IMAGE_SIZE
+
+#define CONFIG_WP_OFF		CONFIG_RO_STORAGE_OFF
+#define CONFIG_WP_SIZE		CONFIG_FW_IMAGE_SIZE
+
+#endif /* __CROS_EC_CONFIG_STD_INTERNAL_FLASH_H */
diff --git a/include/flash.h b/include/flash.h
index b9cccb82cd..0c3d12e1e1 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -14,13 +14,9 @@
 /* Number of physical flash banks */
 #define PHYSICAL_BANKS (CONFIG_FLASH_PHYSICAL_SIZE / CONFIG_FLASH_BANK_SIZE)
 
-/* Read-only firmware offset and size in units of flash banks */
-#define RO_BANK_OFFSET		(CONFIG_RO_MEM_OFF / CONFIG_FLASH_BANK_SIZE)
-#define RO_BANK_COUNT		(CONFIG_RO_SIZE / CONFIG_FLASH_BANK_SIZE)
-
-/* Read-write firmware offset and size in units of flash banks */
-#define RW_BANK_OFFSET		(CONFIG_RW_MEM_OFF / CONFIG_FLASH_BANK_SIZE)
-#define RW_BANK_COUNT		(CONFIG_RW_SIZE / CONFIG_FLASH_BANK_SIZE)
+/*WP region offset and size in units of flash banks */
+#define WP_BANK_OFFSET		(CONFIG_WP_OFF / CONFIG_FLASH_BANK_SIZE)
+#define WP_BANK_COUNT		(CONFIG_WP_SIZE / CONFIG_FLASH_BANK_SIZE)
 
 /* Persistent protection state flash offset / size / bank */
 #if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)
diff --git a/test/flash.c b/test/flash.c
index ab99272ff2..3f7676d0f1 100644
--- a/test/flash.c
+++ b/test/flash.c
@@ -286,10 +286,10 @@ static int test_overwrite_current(void)
 
 	/* Test that we cannot overwrite current image */
 	if (system_get_image_copy() == SYSTEM_IMAGE_RO) {
-		offset = CONFIG_RO_MEM_OFF;
+		offset = CONFIG_RO_STORAGE_OFF;
 		size = CONFIG_RO_SIZE;
 	} else {
-		offset = CONFIG_RW_MEM_OFF;
+		offset = CONFIG_RW_STORAGE_OFF;
 		size = CONFIG_RW_SIZE;
 	}
 
@@ -312,10 +312,10 @@ static int test_overwrite_other(void)
 
 	/* Test that we can overwrite the other image */
 	if (system_get_image_copy() == SYSTEM_IMAGE_RW) {
-		offset = CONFIG_RO_MEM_OFF;
+		offset = CONFIG_RO_STORAGE_OFF;
 		size = CONFIG_RO_SIZE;
 	} else {
-		offset = CONFIG_RW_MEM_OFF;
+		offset = CONFIG_RW_STORAGE_OFF;
 		size = CONFIG_RW_SIZE;
 	}
 
@@ -335,10 +335,10 @@ static int test_overwrite_other(void)
 static int test_op_failure(void)
 {
 	mock_flash_op_fail = EC_ERROR_UNKNOWN;
-	VERIFY_NO_WRITE(CONFIG_RO_MEM_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_WRITE(CONFIG_RW_MEM_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_ERASE(CONFIG_RO_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_ERASE(CONFIG_RW_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
+	VERIFY_NO_WRITE(CONFIG_RO_STORAGE_OFF, sizeof(testdata), testdata);
+	VERIFY_NO_WRITE(CONFIG_RW_STORAGE_OFF, sizeof(testdata), testdata);
+	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
+	VERIFY_NO_ERASE(CONFIG_RW_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
 	mock_flash_op_fail = EC_SUCCESS;
 
 	return EC_SUCCESS;
@@ -360,9 +360,9 @@ static int test_flash_info(void)
 static int test_region_info(void)
 {
 	VERIFY_REGION_INFO(EC_FLASH_REGION_RO,
-			   CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE);
+			   CONFIG_RO_STORAGE_OFF, CONFIG_RO_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_RW,
-			   CONFIG_RW_MEM_OFF, CONFIG_RW_SIZE);
+			   CONFIG_RW_STORAGE_OFF, CONFIG_RW_SIZE);
 	VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO,
 			   CONFIG_WP_OFF, CONFIG_WP_SIZE);
 
@@ -391,16 +391,16 @@ static int test_write_protect(void)
 	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
 
 	/* Check we cannot erase anything */
-	TEST_ASSERT(flash_physical_erase(CONFIG_RO_MEM_OFF,
+	TEST_ASSERT(flash_physical_erase(CONFIG_RO_STORAGE_OFF,
 			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
-	TEST_ASSERT(flash_physical_erase(CONFIG_RW_MEM_OFF,
+	TEST_ASSERT(flash_physical_erase(CONFIG_RW_STORAGE_OFF,
 			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
 
 	/* We should not even try to write/erase */
-	VERIFY_NO_ERASE(CONFIG_RO_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_ERASE(CONFIG_RW_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
-	VERIFY_NO_WRITE(CONFIG_RO_MEM_OFF, sizeof(testdata), testdata);
-	VERIFY_NO_WRITE(CONFIG_RW_MEM_OFF, sizeof(testdata), testdata);
+	VERIFY_NO_ERASE(CONFIG_RO_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
+	VERIFY_NO_ERASE(CONFIG_RW_STORAGE_OFF, CONFIG_FLASH_ERASE_SIZE);
+	VERIFY_NO_WRITE(CONFIG_RO_STORAGE_OFF, sizeof(testdata), testdata);
+	VERIFY_NO_WRITE(CONFIG_RW_STORAGE_OFF, sizeof(testdata), testdata);
 
 	return EC_SUCCESS;
 }
@@ -409,7 +409,7 @@ static int test_boot_write_protect(void)
 {
 	/* Check write protect state persists through reboot */
 	ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
-	TEST_ASSERT(flash_physical_erase(CONFIG_RO_MEM_OFF,
+	TEST_ASSERT(flash_physical_erase(CONFIG_RO_STORAGE_OFF,
 			CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
 
 	return EC_SUCCESS;