diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-09-20 14:35:04 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-09-21 12:48:43 -0700 |
| commit | 7d430cde7ee6f39e55b5b7ef2863c1263f699eaf (patch) | |
| tree | cf6426bebb3b5f7447eb5be9dc6cf7960bc8b055 | |
| parent | 33ec163ac21ce0fda82c3ae60744e48822d978bb (diff) | |
| download | chrome-ec-7d430cde7ee6f39e55b5b7ef2863c1263f699eaf.tar.gz | |
npcx: Fixed bug i2c sometime cannot generates NACK in Read Byte protocol
We should clear STASTR to release SCL only after NACK/STOP bits are set.
If an interrupt which priority is higher than i2c's issues at this moment,
i2c hardware might not generate NACK since SCL is already released by
clearing stall's pending bit.
Modified sources:
1. i2c.c: Fixed bug i2c sometime cannot generate NACK during Read Byte.
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:57452
TEST=make buildall; passed "while(1); do; ectool i2cread 8 0 0x50 0x44;
done;" on reef.
Change-Id: I68ee5bf3d703cbe4fceefcfcc9afab9cb14bc2dc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/386586
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/npcx/i2c.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c index b4b879cfa8..7598fd8b02 100644 --- a/chip/npcx/i2c.c +++ b/chip/npcx/i2c.c @@ -533,9 +533,8 @@ void i2c_master_int_handler (int controller) /* Condition 3: A Stall after START has occurred for READ-BYTE */ if (IS_BIT_SET(NPCX_SMBST(controller), NPCX_SMBST_STASTR)) { CPUTS("-STL"); - /* Clear STASTR Bit */ - SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR); - /* Disable Stall-After-Start mode */ + + /* Disable Stall-After-Start mode first */ CLEAR_BIT(NPCX_SMBCTL1(controller), NPCX_SMBCTL1_STASTRE); /* @@ -550,6 +549,9 @@ void i2c_master_int_handler (int controller) */ else if (p_status->flags & I2C_XFER_STOP) I2C_NACK(controller); + + /* Clear STASTR to release SCL after setting NACK/STOP bits */ + SET_BIT(NPCX_SMBST(controller), NPCX_SMBST_STASTR); } /* Condition 4: SDA status is set - transmit or receive */ |