diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-05-06 14:58:59 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-10 09:34:45 -0700 |
| commit | b8154d02467b7f36475ba9e6e8b4d8e3ccc5b590 (patch) | |
| tree | cf0a9dd06f9ae5e073e27d1b28b5328fb9760438 | |
| parent | 65bca9b9fdd797c1a659718f08b4eaa3d7de41ce (diff) | |
| download | chrome-ec-b8154d02467b7f36475ba9e6e8b4d8e3ccc5b590.tar.gz | |
kevin: Move RAM from data section to code
Kevin is code space constrained, so use RAM normally used for data
instead for code.
BUG=chrome-os-partner:52876
BRANCH=None
TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data
RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes
to add sensor task). Also, verify kevin continues to boot + power sequence.
Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343191
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
| -rw-r--r-- | board/kevin/board.h | 12 | ||||
| -rw-r--r-- | chip/npcx/config_chip.h | 4 | ||||
| -rw-r--r-- | chip/npcx/config_flash_layout.h | 2 |
3 files changed, 15 insertions, 3 deletions
diff --git a/board/kevin/board.h b/board/kevin/board.h index b7735015d3..9f399e1a5b 100644 --- a/board/kevin/board.h +++ b/board/kevin/board.h @@ -20,6 +20,18 @@ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands for testing */ +/* + * We are code space-constrained on kevin, so take 4K that is normally used + * as data RAM (was 30K, now 26K) and use it for code RAM (was 96K, now 100K) + */ +#define RAM_SHIFT_SIZE (4 * 1024) +#undef CONFIG_RO_SIZE +#define CONFIG_RO_SIZE (NPCX_PROGRAM_MEMORY_SIZE + RAM_SHIFT_SIZE) +#undef CONFIG_RAM_BASE +#define CONFIG_RAM_BASE (0x200C0000 + RAM_SHIFT_SIZE) +#undef CONFIG_RAM_SIZE +#define CONFIG_RAM_SIZE (0x00008000 - 0x800 - RAM_SHIFT_SIZE) + /* Optional features */ #define CONFIG_BOARD_VERSION #define CONFIG_BOARD_SPECIFIC_VERSION diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 39cdf9ef51..ff5264ec75 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -50,12 +50,12 @@ /* Use chip variant to specify the size and start address of program memory */ #if defined(CHIP_VARIANT_NPCX5M5G) /* 96KB RAM for FW code */ -#define CONFIG_PROGRAM_MEMORY_SIZE (96 * 1024) +#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024) /* program memory base address for 128KB RAM */ #define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 #elif defined(CHIP_VARIANT_NPCX5M6G) /* 224KB RAM for FW code */ -#define CONFIG_PROGRAM_MEMORY_SIZE (224 * 1024) +#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024) /* program memory base address for 256KB RAM */ #define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 #else diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 065f4a3645..b79eed3e17 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -44,7 +44,7 @@ /* RO firmware offset in flash */ #define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE CONFIG_PROGRAM_MEMORY_SIZE +#define CONFIG_RO_SIZE NPCX_PROGRAM_MEMORY_SIZE /* RW firmware offset in flash */ #define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF |