diff options
| author | Mary Ruthven <mruthven@chromium.org> | 2016-03-27 20:12:45 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-29 15:56:30 -0700 |
| commit | 170d6bdd44ea97b213a95adcf8c2cae04ffbca0e (patch) | |
| tree | 0f03481e5d1c673f5d669505530c6a29174a9b7b | |
| parent | 4c294d144bd479c6269e183215fa0f9cfbe49f8d (diff) | |
| download | chrome-ec-170d6bdd44ea97b213a95adcf8c2cae04ffbca0e.tar.gz | |
cr50: update GPIOs
Update the GPIO mapping based on the Kevin P0 schematic and drive the EC
and AP select signals low.
BUG=chrome-os-partner:50728
BRANCH=none
TEST=test that DIOB2 and B3 default to low, but can be set high or low.
Change-Id: If574436913ad0271540bcce2939fe1f4574dae97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335381
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
| -rw-r--r-- | board/cr50/gpio.inc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index 451e3075ff..9ad8d64774 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -11,8 +11,8 @@ GPIO(INT_AP_L, PIN(0, 0), GPIO_INPUT) /* Use these to take over the AP & EC flash (only when AP & EC are off!) */ -GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_INPUT) -GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_INPUT) +GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW) +GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW) /* As an input this mirrors EC_WP_L (which is controlled by RBOX, not a GPIO). * As an output it can override EC_WP_L, although why would we? */ @@ -41,11 +41,11 @@ UNIMPLEMENTED(ENTERING_RW) #endif /* GPIOs - mark outputs as inputs too, to read back from the driven pad */ -PINMUX(GPIO(INT_AP_L), B7, DIO_INPUT) /* DIOB7 is p_digitial_od */ +PINMUX(GPIO(INT_AP_L), A5, DIO_INPUT) /* DIOB7 is p_digitial_od */ /* We can't pull it up */ -PINMUX(GPIO(EC_FLASH_SELECT), A3, DIO_INPUT) -PINMUX(GPIO(AP_FLASH_SELECT), A7, DIO_INPUT) -PINMUX(GPIO(AP_WP_L), A5, 0) +PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT) +PINMUX(GPIO(AP_FLASH_SELECT), B3, DIO_INPUT) +PINMUX(GPIO(AP_WP_L), M3, 0) PINMUX(GPIO(SYS_RST), M0, DIO_INPUT) PINMUX(GPIO(CCD_MODE), M1, DIO_INPUT) PINMUX(GPIO(BATT_PRES), M2, 0) @@ -53,8 +53,8 @@ PINMUX(GPIO(BATT_PRES), M2, 0) /* UARTs */ PINMUX(FUNC(UART0_TX), A0, DIO_OUTPUT) /* Cr50 console */ PINMUX(FUNC(UART0_RX), A1, DIO_INPUT) -PINMUX(FUNC(UART1_TX), B3, DIO_INPUT) /* AP console */ -PINMUX(FUNC(UART1_RX), B2, DIO_INPUT) +PINMUX(FUNC(UART1_TX), A3, DIO_INPUT) /* AP console */ +PINMUX(FUNC(UART1_RX), A7, DIO_INPUT) PINMUX(FUNC(UART2_TX), B5, DIO_INPUT) /* EC console */ PINMUX(FUNC(UART2_RX), B6, DIO_INPUT) |