diff options
| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-11-02 09:56:01 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-03 09:08:07 -0800 |
| commit | 80b997dc276b099714e1c5b6eeea02adbae44081 (patch) | |
| tree | a014a58999eaba4974bcf637b8a5fdf04fccb27e | |
| parent | 59fd91317ce966d713b4ec077b39f385e6029e18 (diff) | |
| download | chrome-ec-80b997dc276b099714e1c5b6eeea02adbae44081.tar.gz | |
mec1322: fix gpio_disable_interrupt
MEC1322_INT_DISABLE(interrupt enable clear register) is 'Write 1 to Clear'
for each bit. To disable interrupt for specific GPIO pin, only specific
bit should be written with 1.
BUG=NONE
BRANCH=NONE
TEST=NONE
Change-Id: Ibf40a20656c4c99f9625b516cff3e7da9bf2f69d
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/309979
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/mec1322/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index fe1bf89fd6..0d59dc5849 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -168,7 +168,7 @@ int gpio_disable_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; bit_id = (port - int_map[port].port_offset) * 8 + i; - MEC1322_INT_DISABLE(girq_id) |= (1 << bit_id); + MEC1322_INT_DISABLE(girq_id) = (1 << bit_id); return EC_SUCCESS; } |