diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-09-29 09:49:09 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-29 19:38:22 -0700 |
| commit | b8475a13c068633bea328f311c3b655e1fb9b107 (patch) | |
| tree | ff974f1d547050b5a5865e6f3061b63d09a2cbb6 | |
| parent | ac234f05e0ac34f168805ad186b00ac13c9594fa (diff) | |
| download | chrome-ec-b8475a13c068633bea328f311c3b655e1fb9b107.tar.gz | |
cr50: update to the next fpga revision
This patch upgrades the hardware definition to the latest released
FPGA image, which is reported as follows:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
m3.0.0> info
IDCODE: 2ba01477
DPCTRL: f0000000
m3.0.0> Note: MD5Sums match: 77e8a79e
m3.0.0> Note: CPU0 halted at @ a76
m3debug serial: 0x0
PROJECT: haven revB1
DATE(yyyymmdd): 20150925
TIME(hhmmss): 21715
XML MD5SUM: 0x77e8a79e
HDR MD5SUM: 0xfd9218ab
P4 last CL: 73753
Xml file name include/havenTop.xml
m3.0.0>
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This latest FPGA image includes a more sophisticated bootrom,
requiring a differently signed firmware image. The signer update is in
the next patch.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=verified that the image boots fine when signed by the updated
signer (which comes in the next patch).
Change-Id: I9a5d8e9e786dfa905619f1c629fe75b82c565490
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302803
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
| -rw-r--r-- | chip/g/config_chip.h | 2 | ||||
| -rw-r--r-- | chip/g/cr50_fpga_regdefs.h | 12087 |
2 files changed, 7331 insertions, 4758 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 14d5ead8d6..8bef2e687a 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -10,7 +10,7 @@ /* Number of IRQ vectors on the NVIC */ /* TODO_FPGA this should come from the generated .h file */ -#define CONFIG_IRQ_COUNT 188 +#define CONFIG_IRQ_COUNT 192 /* Describe the RAM layout */ #define CONFIG_RAM_BASE 0x10000 diff --git a/chip/g/cr50_fpga_regdefs.h b/chip/g/cr50_fpga_regdefs.h index 6a4f171ba2..5622dd1ce0 100644 --- a/chip/g/cr50_fpga_regdefs.h +++ b/chip/g/cr50_fpga_regdefs.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 The Chromium OS Authors. All rights reserved. + * Copyright 2015 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -76,12 +76,12 @@ #define GC_PINMUX_GPIO1_GPIO13_SEL 0x1e #define GC_PINMUX_GPIO1_GPIO14_SEL 0x1f #define GC_PINMUX_GPIO1_GPIO15_SEL 0x20 -#define GC_PINMUX_I2C0_SCL_SEL 0x23 -#define GC_PINMUX_I2C0_SDA_SEL 0x24 -#define GC_PINMUX_I2C1_SCL_SEL 0x25 -#define GC_PINMUX_I2C1_SDA_SEL 0x26 -#define GC_PINMUX_I2CS0_SCL_SEL 0x21 -#define GC_PINMUX_I2CS0_SDA_SEL 0x22 +#define GC_PINMUX_I2C0_SCL_SEL 0x21 +#define GC_PINMUX_I2C0_SDA_SEL 0x22 +#define GC_PINMUX_I2C1_SCL_SEL 0x23 +#define GC_PINMUX_I2C1_SDA_SEL 0x24 +#define GC_PINMUX_I2CS0_SCL_SEL 0x25 +#define GC_PINMUX_I2CS0_SDA_SEL 0x26 #define GC_PINMUX_PMU_BROWNOUT_DET_SEL 0x27 #define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL 0x28 #define GC_PINMUX_SPI1_SPICLK_SEL 0x29 @@ -173,166 +173,173 @@ #define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2f #define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x30 #define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x31 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x32 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x33 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x34 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x35 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x36 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x37 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x38 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x39 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3a -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3b -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3c -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x3d -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x3e -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x3f -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x40 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x41 -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x42 -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x43 -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x44 -#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x45 -#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x46 -#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x47 -#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x48 -#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x4a -#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x4b -#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x4c -#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x4d -#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x4e -#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x4f -#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x50 -#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x51 -#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x52 -#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x53 -#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x54 -#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x55 -#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x56 -#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x57 -#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x58 -#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x59 -#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x49 -#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x5b -#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x5c -#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x5d -#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x5e -#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x5f -#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x60 -#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x61 -#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x62 -#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x63 -#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x64 -#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x65 -#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x66 -#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x67 -#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x68 -#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x69 -#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x6a -#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x5a -#define GC_EXCEPTNUM_I2C0_I2CINT 0x6e -#define GC_EXCEPTNUM_I2C1_I2CINT 0x6f -#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x6b -#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x6c -#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x6d -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x70 -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x71 -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x72 -#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x73 -#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x74 -#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x75 -#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT 0x76 -#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x77 -#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x78 -#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x79 -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x7a -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x7b -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x7c -#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_L_FED_INT 0x7d -#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_L_RED_INT 0x7e -#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x7f -#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x80 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x81 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x82 -#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x83 -#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x84 -#define GC_EXCEPTNUM_RDD0_INTR_NEW_STATE_DETECTED_INT 0x85 -#define GC_EXCEPTNUM_SPI0_SPITXINT 0x86 -#define GC_EXCEPTNUM_SPI1_SPITXINT 0x87 -#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x88 -#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x89 -#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x8a -#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x8b -#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x8c -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x8d -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x8e -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x8f -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x90 -#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x91 -#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x92 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x93 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x94 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x95 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x96 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x97 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x98 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0x99 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0x9a -#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0x9b -#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0x9c -#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0x9d -#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0x9e -#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0x9f -#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0xa1 -#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0xa2 -#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0xa0 -#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0xa4 -#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0xa5 -#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0xa3 -#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xa6 -#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xa7 -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xa8 -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xa9 -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xaa -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xab -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xac -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xad -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xae -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xaf -#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xb0 -#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xb1 -#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xb2 -#define GC_EXCEPTNUM_UART0_RXBINT 0xb3 -#define GC_EXCEPTNUM_UART0_RXFINT 0xb4 -#define GC_EXCEPTNUM_UART0_RXINT 0xb5 -#define GC_EXCEPTNUM_UART0_RXOVINT 0xb6 -#define GC_EXCEPTNUM_UART0_RXTOINT 0xb7 -#define GC_EXCEPTNUM_UART0_TXINT 0xb8 -#define GC_EXCEPTNUM_UART0_TXOVINT 0xb9 -#define GC_EXCEPTNUM_UART1_RXBINT 0xba -#define GC_EXCEPTNUM_UART1_RXFINT 0xbb -#define GC_EXCEPTNUM_UART1_RXINT 0xbc -#define GC_EXCEPTNUM_UART1_RXOVINT 0xbd -#define GC_EXCEPTNUM_UART1_RXTOINT 0xbe -#define GC_EXCEPTNUM_UART1_TXINT 0xbf -#define GC_EXCEPTNUM_UART1_TXOVINT 0xc0 -#define GC_EXCEPTNUM_UART2_RXBINT 0xc1 -#define GC_EXCEPTNUM_UART2_RXFINT 0xc2 -#define GC_EXCEPTNUM_UART2_RXINT 0xc3 -#define GC_EXCEPTNUM_UART2_RXOVINT 0xc4 -#define GC_EXCEPTNUM_UART2_RXTOINT 0xc5 -#define GC_EXCEPTNUM_UART2_TXINT 0xc6 -#define GC_EXCEPTNUM_UART2_TXOVINT 0xc7 -#define GC_EXCEPTNUM_USB0_USBINTR 0xc8 -#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xc9 -#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xca -#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xcb -#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xcc -#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xcd -#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xce -#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xcf -#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd0 -#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xd1 +#define GC_EXCEPTNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 0x32 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x33 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x34 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x35 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x36 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x37 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x38 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x39 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x3a +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3b +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 0x3c +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3d +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3e +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x3f +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x40 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x41 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x42 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 0x43 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 0x44 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x45 +#define GC_EXCEPTNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 0x46 +#define GC_EXCEPTNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 0x47 +#define GC_EXCEPTNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 0x48 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x49 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x4a +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x4b +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x4c +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x4d +#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x4e +#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x4f +#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x50 +#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x51 +#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x52 +#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x53 +#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x54 +#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x55 +#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x56 +#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x57 +#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x58 +#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x59 +#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x5a +#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x5b +#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x5c +#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x5d +#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x5e +#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x5f +#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x60 +#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x61 +#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x62 +#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x63 +#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x64 +#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x65 +#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x66 +#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x67 +#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x68 +#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x69 +#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x6a +#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x6b +#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x6c +#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x6d +#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x6e +#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x6f +#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x70 +#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x71 +#define GC_EXCEPTNUM_I2C0_I2CINT 0x72 +#define GC_EXCEPTNUM_I2C1_I2CINT 0x73 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x74 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x75 +#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x76 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x77 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x78 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x79 +#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x7a +#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x7b +#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x7c +#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT 0x7d +#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x7e +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x7f +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x80 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x81 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x82 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x83 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_FED_INT 0x84 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_RED_INT 0x85 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x86 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x87 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x88 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x89 +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x8a +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x8b +#define GC_EXCEPTNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 0x8c +#define GC_EXCEPTNUM_SPI0_SPITXINT 0x8d +#define GC_EXCEPTNUM_SPI1_SPITXINT 0x8e +#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x8f +#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x90 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x91 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x92 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x93 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x94 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x95 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x96 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x97 +#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x98 +#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x99 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x9a +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x9b +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x9c +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x9d +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x9e +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x9f +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0xa0 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0xa1 +#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0xa2 +#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0xa3 +#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0xa4 +#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0xa5 +#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0xa6 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0xa7 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0xa8 +#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0xa9 +#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0xaa +#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0xab +#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0xac +#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xad +#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xae +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xaf +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xb0 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xb1 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xb2 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xb3 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xb4 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xb5 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xb6 +#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xb7 +#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xb8 +#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xb9 +#define GC_EXCEPTNUM_UART0_RXBINT 0xba +#define GC_EXCEPTNUM_UART0_RXFINT 0xbb +#define GC_EXCEPTNUM_UART0_RXINT 0xbc +#define GC_EXCEPTNUM_UART0_RXOVINT 0xbd +#define GC_EXCEPTNUM_UART0_RXTOINT 0xbe +#define GC_EXCEPTNUM_UART0_TXINT 0xbf +#define GC_EXCEPTNUM_UART0_TXOVINT 0xc0 +#define GC_EXCEPTNUM_UART1_RXBINT 0xc1 +#define GC_EXCEPTNUM_UART1_RXFINT 0xc2 +#define GC_EXCEPTNUM_UART1_RXINT 0xc3 +#define GC_EXCEPTNUM_UART1_RXOVINT 0xc4 +#define GC_EXCEPTNUM_UART1_RXTOINT 0xc5 +#define GC_EXCEPTNUM_UART1_TXINT 0xc6 +#define GC_EXCEPTNUM_UART1_TXOVINT 0xc7 +#define GC_EXCEPTNUM_UART2_RXBINT 0xc8 +#define GC_EXCEPTNUM_UART2_RXFINT 0xc9 +#define GC_EXCEPTNUM_UART2_RXINT 0xca +#define GC_EXCEPTNUM_UART2_RXOVINT 0xcb +#define GC_EXCEPTNUM_UART2_RXTOINT 0xcc +#define GC_EXCEPTNUM_UART2_TXINT 0xcd +#define GC_EXCEPTNUM_UART2_TXOVINT 0xce +#define GC_EXCEPTNUM_USB0_USBINTR 0xcf +#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xd0 +#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xd1 +#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xd2 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xd3 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xd4 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xd5 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xd6 +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd7 +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xd8 #define GC_IRQNUM_RESET 0 #define GC_IRQNUM_NMI 0 #define GC_IRQNUM_HARDFAULT 0 @@ -382,184 +389,191 @@ #define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 31 #define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 32 #define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 33 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 34 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 35 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 36 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 37 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 38 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 39 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 40 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 41 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 42 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 43 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 44 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 45 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 46 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 47 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 48 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 49 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 50 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 51 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 52 -#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 53 -#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 54 -#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 55 -#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 56 -#define GC_IRQNUM_GPIO0_GPIO0INT 58 -#define GC_IRQNUM_GPIO0_GPIO1INT 59 -#define GC_IRQNUM_GPIO0_GPIO2INT 60 -#define GC_IRQNUM_GPIO0_GPIO3INT 61 -#define GC_IRQNUM_GPIO0_GPIO4INT 62 -#define GC_IRQNUM_GPIO0_GPIO5INT 63 -#define GC_IRQNUM_GPIO0_GPIO6INT 64 -#define GC_IRQNUM_GPIO0_GPIO7INT 65 -#define GC_IRQNUM_GPIO0_GPIO8INT 66 -#define GC_IRQNUM_GPIO0_GPIO9INT 67 -#define GC_IRQNUM_GPIO0_GPIO10INT 68 -#define GC_IRQNUM_GPIO0_GPIO11INT 69 -#define GC_IRQNUM_GPIO0_GPIO12INT 70 -#define GC_IRQNUM_GPIO0_GPIO13INT 71 -#define GC_IRQNUM_GPIO0_GPIO14INT 72 -#define GC_IRQNUM_GPIO0_GPIO15INT 73 -#define GC_IRQNUM_GPIO0_GPIOCOMBINT 57 -#define GC_IRQNUM_GPIO1_GPIO0INT 75 -#define GC_IRQNUM_GPIO1_GPIO1INT 76 -#define GC_IRQNUM_GPIO1_GPIO2INT 77 -#define GC_IRQNUM_GPIO1_GPIO3INT 78 -#define GC_IRQNUM_GPIO1_GPIO4INT 79 -#define GC_IRQNUM_GPIO1_GPIO5INT 80 -#define GC_IRQNUM_GPIO1_GPIO6INT 81 -#define GC_IRQNUM_GPIO1_GPIO7INT 82 -#define GC_IRQNUM_GPIO1_GPIO8INT 83 -#define GC_IRQNUM_GPIO1_GPIO9INT 84 -#define GC_IRQNUM_GPIO1_GPIO10INT 85 -#define GC_IRQNUM_GPIO1_GPIO11INT 86 -#define GC_IRQNUM_GPIO1_GPIO12INT 87 -#define GC_IRQNUM_GPIO1_GPIO13INT 88 -#define GC_IRQNUM_GPIO1_GPIO14INT 89 -#define GC_IRQNUM_GPIO1_GPIO15INT 90 -#define GC_IRQNUM_GPIO1_GPIOCOMBINT 74 -#define GC_IRQNUM_I2C0_I2CINT 94 -#define GC_IRQNUM_I2C1_I2CINT 95 -#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 91 -#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 92 -#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 93 -#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT 96 -#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 97 -#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 98 -#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 99 -#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 100 -#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 101 -#define GC_IRQNUM_KEYMGR0_DSHA_INT 102 -#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 103 -#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 104 -#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 105 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 106 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 107 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 108 -#define GC_IRQNUM_RBOX0_INTR_EC_RST_L_FED_INT 109 -#define GC_IRQNUM_RBOX0_INTR_EC_RST_L_RED_INT 110 -#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 111 -#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 112 -#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 113 -#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 114 -#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 115 -#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 116 -#define GC_IRQNUM_RDD0_INTR_NEW_STATE_DETECTED_INT 117 -#define GC_IRQNUM_SPI0_SPITXINT 118 -#define GC_IRQNUM_SPI1_SPITXINT 119 -#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 120 -#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 121 -#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 122 -#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 123 -#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 124 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 125 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 126 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 127 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 128 -#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 129 -#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 130 -#define GC_IRQNUM_SPS0_SPSCTRLINT0 131 -#define GC_IRQNUM_SPS0_SPSCTRLINT1 132 -#define GC_IRQNUM_SPS0_SPSCTRLINT2 133 -#define GC_IRQNUM_SPS0_SPSCTRLINT3 134 -#define GC_IRQNUM_SPS0_SPSCTRLINT4 135 -#define GC_IRQNUM_SPS0_SPSCTRLINT5 136 -#define GC_IRQNUM_SPS0_SPSCTRLINT6 137 -#define GC_IRQNUM_SPS0_SPSCTRLINT7 138 -#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 139 -#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 140 -#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 141 -#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 142 -#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 143 -#define GC_IRQNUM_TIMEHS0_TIMINT1 145 -#define GC_IRQNUM_TIMEHS0_TIMINT2 146 -#define GC_IRQNUM_TIMEHS0_TIMINTC 144 -#define GC_IRQNUM_TIMEHS1_TIMINT1 148 -#define GC_IRQNUM_TIMEHS1_TIMINT2 149 -#define GC_IRQNUM_TIMEHS1_TIMINTC 147 -#define GC_IRQNUM_TIMELS0_TIMINT0 150 -#define GC_IRQNUM_TIMELS0_TIMINT1 151 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 152 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 153 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 154 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 155 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 156 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 157 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 158 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 159 -#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 160 -#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 161 -#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 162 -#define GC_IRQNUM_UART0_RXBINT 163 -#define GC_IRQNUM_UART0_RXFINT 164 -#define GC_IRQNUM_UART0_RXINT 165 -#define GC_IRQNUM_UART0_RXOVINT 166 -#define GC_IRQNUM_UART0_RXTOINT 167 -#define GC_IRQNUM_UART0_TXINT 168 -#define GC_IRQNUM_UART0_TXOVINT 169 -#define GC_IRQNUM_UART1_RXBINT 170 -#define GC_IRQNUM_UART1_RXFINT 171 -#define GC_IRQNUM_UART1_RXINT 172 -#define GC_IRQNUM_UART1_RXOVINT 173 -#define GC_IRQNUM_UART1_RXTOINT 174 -#define GC_IRQNUM_UART1_TXINT 175 -#define GC_IRQNUM_UART1_TXOVINT 176 -#define GC_IRQNUM_UART2_RXBINT 177 -#define GC_IRQNUM_UART2_RXFINT 178 -#define GC_IRQNUM_UART2_RXINT 179 -#define GC_IRQNUM_UART2_RXOVINT 180 -#define GC_IRQNUM_UART2_RXTOINT 181 -#define GC_IRQNUM_UART2_TXINT 182 -#define GC_IRQNUM_UART2_TXOVINT 183 -#define GC_IRQNUM_USB0_USBINTR 184 -#define GC_IRQNUM_WATCHDOG0_WDOGINT 185 -#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 186 -#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 187 -#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 188 -#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 189 -#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 190 -#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 191 -#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 192 -#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 193 -#define GC_CAMO0_BASE_ADDR 0x40430000 +#define GC_IRQNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 34 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 35 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 36 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 37 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 38 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 39 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 40 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 41 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 42 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 43 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 44 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 45 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 46 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 47 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 48 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 49 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 50 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 51 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 52 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 53 +#define GC_IRQNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 54 +#define GC_IRQNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 55 +#define GC_IRQNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 56 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 57 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 58 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 59 +#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 60 +#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 61 +#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 62 +#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 63 +#define GC_IRQNUM_GPIO0_GPIO0INT 64 +#define GC_IRQNUM_GPIO0_GPIO1INT 65 +#define GC_IRQNUM_GPIO0_GPIO2INT 66 +#define GC_IRQNUM_GPIO0_GPIO3INT 67 +#define GC_IRQNUM_GPIO0_GPIO4INT 68 +#define GC_IRQNUM_GPIO0_GPIO5INT 69 +#define GC_IRQNUM_GPIO0_GPIO6INT 70 +#define GC_IRQNUM_GPIO0_GPIO7INT 71 +#define GC_IRQNUM_GPIO0_GPIO8INT 72 +#define GC_IRQNUM_GPIO0_GPIO9INT 73 +#define GC_IRQNUM_GPIO0_GPIO10INT 74 +#define GC_IRQNUM_GPIO0_GPIO11INT 75 +#define GC_IRQNUM_GPIO0_GPIO12INT 76 +#define GC_IRQNUM_GPIO0_GPIO13INT 77 +#define GC_IRQNUM_GPIO0_GPIO14INT 78 +#define GC_IRQNUM_GPIO0_GPIO15INT 79 +#define GC_IRQNUM_GPIO0_GPIOCOMBINT 80 +#define GC_IRQNUM_GPIO1_GPIO0INT 81 +#define GC_IRQNUM_GPIO1_GPIO1INT 82 +#define GC_IRQNUM_GPIO1_GPIO2INT 83 +#define GC_IRQNUM_GPIO1_GPIO3INT 84 +#define GC_IRQNUM_GPIO1_GPIO4INT 85 +#define GC_IRQNUM_GPIO1_GPIO5INT 86 +#define GC_IRQNUM_GPIO1_GPIO6INT 87 +#define GC_IRQNUM_GPIO1_GPIO7INT 88 +#define GC_IRQNUM_GPIO1_GPIO8INT 89 +#define GC_IRQNUM_GPIO1_GPIO9INT 90 +#define GC_IRQNUM_GPIO1_GPIO10INT 91 +#define GC_IRQNUM_GPIO1_GPIO11INT 92 +#define GC_IRQNUM_GPIO1_GPIO12INT 93 +#define GC_IRQNUM_GPIO1_GPIO13INT 94 +#define GC_IRQNUM_GPIO1_GPIO14INT 95 +#define GC_IRQNUM_GPIO1_GPIO15INT 96 +#define GC_IRQNUM_GPIO1_GPIOCOMBINT 97 +#define GC_IRQNUM_I2C0_I2CINT 98 +#define GC_IRQNUM_I2C1_I2CINT 99 +#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 100 +#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 101 +#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 102 +#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT 103 +#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 104 +#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 105 +#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 106 +#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 107 +#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 108 +#define GC_IRQNUM_KEYMGR0_DSHA_INT 109 +#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 110 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 111 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 112 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 113 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 114 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 115 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_FED_INT 116 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_RED_INT 117 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 118 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 119 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 120 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 121 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 122 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 123 +#define GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 124 +#define GC_IRQNUM_SPI0_SPITXINT 125 +#define GC_IRQNUM_SPI1_SPITXINT 126 +#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 127 +#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 128 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 129 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 130 +#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 131 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 132 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 133 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 134 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 135 +#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 136 +#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 137 +#define GC_IRQNUM_SPS0_SPSCTRLINT0 138 +#define GC_IRQNUM_SPS0_SPSCTRLINT1 139 +#define GC_IRQNUM_SPS0_SPSCTRLINT2 140 +#define GC_IRQNUM_SPS0_SPSCTRLINT3 141 +#define GC_IRQNUM_SPS0_SPSCTRLINT4 142 +#define GC_IRQNUM_SPS0_SPSCTRLINT5 143 +#define GC_IRQNUM_SPS0_SPSCTRLINT6 144 +#define GC_IRQNUM_SPS0_SPSCTRLINT7 145 +#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 146 +#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 147 +#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 148 +#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 149 +#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 150 +#define GC_IRQNUM_TIMEHS0_TIMINT1 151 +#define GC_IRQNUM_TIMEHS0_TIMINT2 152 +#define GC_IRQNUM_TIMEHS0_TIMINTC 153 +#define GC_IRQNUM_TIMEHS1_TIMINT1 154 +#define GC_IRQNUM_TIMEHS1_TIMINT2 155 +#define GC_IRQNUM_TIMEHS1_TIMINTC 156 +#define GC_IRQNUM_TIMELS0_TIMINT0 157 +#define GC_IRQNUM_TIMELS0_TIMINT1 158 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 159 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 160 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 161 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 162 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 163 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 164 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 165 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 166 +#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 167 +#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 168 +#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 169 +#define GC_IRQNUM_UART0_RXBINT 170 +#define GC_IRQNUM_UART0_RXFINT 171 +#define GC_IRQNUM_UART0_RXINT 172 +#define GC_IRQNUM_UART0_RXOVINT 173 +#define GC_IRQNUM_UART0_RXTOINT 174 +#define GC_IRQNUM_UART0_TXINT 175 +#define GC_IRQNUM_UART0_TXOVINT 176 +#define GC_IRQNUM_UART1_RXBINT 177 +#define GC_IRQNUM_UART1_RXFINT 178 +#define GC_IRQNUM_UART1_RXINT 179 +#define GC_IRQNUM_UART1_RXOVINT 180 +#define GC_IRQNUM_UART1_RXTOINT 181 +#define GC_IRQNUM_UART1_TXINT 182 +#define GC_IRQNUM_UART1_TXOVINT 183 +#define GC_IRQNUM_UART2_RXBINT 184 +#define GC_IRQNUM_UART2_RXFINT 185 +#define GC_IRQNUM_UART2_RXINT 186 +#define GC_IRQNUM_UART2_RXOVINT 187 +#define GC_IRQNUM_UART2_RXTOINT 188 +#define GC_IRQNUM_UART2_TXINT 189 +#define GC_IRQNUM_UART2_TXOVINT 190 +#define GC_IRQNUM_USB0_USBINTR 191 +#define GC_IRQNUM_WATCHDOG0_WDOGINT 192 +#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 193 +#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 194 +#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 195 +#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 196 +#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 197 +#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 198 +#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 199 +#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 200 +#define GC_CAMO0_BASE_ADDR 0x40560000 #define GC_CRYPTO0_BASE_ADDR 0x40420000 -#define GC_DMA0_BASE_ADDR 0x40440000 +#define GC_DMA0_BASE_ADDR 0x40430000 #define GC_FLASH0_BASE_ADDR 0x40710000 -#define GC_FUSE0_BASE_ADDR 0x40460000 +#define GC_FUSE0_BASE_ADDR 0x40450000 #define GC_GLOBALSEC_BASE_ADDR 0x40090000 #define GC_GPIO0_BASE_ADDR 0x40200000 #define GC_GPIO1_BASE_ADDR 0x40210000 #define GC_I2C0_BASE_ADDR 0x40630000 #define GC_I2C1_BASE_ADDR 0x40640000 #define GC_I2CS0_BASE_ADDR 0x40530000 -#define GC_KEYMGR0_BASE_ADDR 0x40480000 +#define GC_KEYMGR0_BASE_ADDR 0x40570000 #define GC_MAU_BASE_ADDR 0x40080000 #define GC_PINMUX_BASE_ADDR 0x40060000 #define GC_PMU_BASE_ADDR 0x40000000 #define GC_M3_BASE_ADDR 0xe0000000 #define GC_RBOX0_BASE_ADDR 0x40550000 -#define GC_RDD0_BASE_ADDR 0x40450000 +#define GC_RDD0_BASE_ADDR 0x40440000 #define GC_RTC0_BASE_ADDR 0x400a0000 #define GC_SPI0_BASE_ADDR 0x40680000 #define GC_SPI1_BASE_ADDR 0x40690000 @@ -575,25 +589,21 @@ #define GC_UART1_BASE_ADDR 0x40610000 #define GC_UART2_BASE_ADDR 0x40620000 #define GC_USB0_BASE_ADDR 0x40300000 -#define GC_VOLT0_BASE_ADDR 0x40470000 +#define GC_VOLT0_BASE_ADDR 0x40460000 #define GC_WATCHDOG0_BASE_ADDR 0x40500000 #define GC_XO0_BASE_ADDR 0x400b0000 -#define GC_CAMO_CLKPERIOD_X256_OFFSET 0x0 -#define GC_CAMO_CLKPERIOD_X256_DEFAULT 0x4 -#define GC_CAMO_RESTART_PRBS_OFFSET 0x4 -#define GC_CAMO_RESTART_PRBS_DEFAULT 0x0 -#define GC_CAMO_BREACH_COUNT_OFFSET 0x8 +#define GC_CAMO_BREACH_COUNT_OFFSET 0x0 #define GC_CAMO_BREACH_COUNT_DEFAULT 0x0 -#define GC_CAMO_CLEAR_COUNTER_OFFSET 0xc +#define GC_CAMO_CLEAR_COUNTER_OFFSET 0x4 #define GC_CAMO_CLEAR_COUNTER_DEFAULT 0x0 -#define GC_CAMO_VERSION_OFFSET 0x10 -#define GC_CAMO_VERSION_DEFAULT 0x200e1a1 +#define GC_CAMO_VERSION_OFFSET 0x8 +#define GC_CAMO_VERSION_DEFAULT 0x3011319 #define GC_CRYPTO_VERSION_OFFSET 0x0 -#define GC_CRYPTO_VERSION_DEFAULT 0x24010ed8 +#define GC_CRYPTO_VERSION_DEFAULT 0x28011ed5 #define GC_CRYPTO_CONTROL_OFFSET 0x4 #define GC_CRYPTO_CONTROL_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_DEFAULT 0x10 +#define GC_CRYPTO_PARITY_CFG_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_DEFAULT 0x10 #define GC_CRYPTO_IMEM_SCRUB_RANGE_OFFSET 0xc #define GC_CRYPTO_IMEM_SCRUB_RANGE_DEFAULT 0x3ff #define GC_CRYPTO_DMEM_SCRUB_RANGE_OFFSET 0x10 @@ -620,173 +630,183 @@ #define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 #define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x3c #define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 -#define GC_CRYPTO_IMEM_PARITY_CFG_OFFSET 0x40 -#define GC_CRYPTO_IMEM_PARITY_CFG_DEFAULT 0x0 -#define GC_CRYPTO_DMEM_PARITY_CFG_OFFSET 0x44 -#define GC_CRYPTO_DMEM_PARITY_CFG_DEFAULT 0x0 -#define GC_CRYPTO_DRF_PARITY_CFG_OFFSET 0x48 -#define GC_CRYPTO_DRF_PARITY_CFG_DEFAULT 0x0 -#define GC_CRYPTO_PGM_LFSR_OFFSET 0x4c +#define GC_CRYPTO_PGM_LFSR_OFFSET 0x40 #define GC_CRYPTO_PGM_LFSR_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x44 #define GC_CRYPTO_DEBUG_BRKPT0_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x54 +#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x48 #define GC_CRYPTO_DEBUG_BRKPT1_DEFAULT 0x0 -#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x58 +#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x4c #define GC_CRYPTO_WIPE_SECRETS_DEFAULT 0x0 #define GC_CRYPTO_DMEM_DUMMY_OFFSET 0x4000 #define GC_CRYPTO_IMEM_DUMMY_OFFSET 0x8000 #define GC_DMA_VERSION_OFFSET 0x0 -#define GC_DMA_VERSION_DEFAULT 0xf010532 +#define GC_DMA_VERSION_DEFAULT 0x12011d58 #define GC_DMA_INT_ENABLE_OFFSET 0x4 #define GC_DMA_INT_ENABLE_DEFAULT 0x0 #define GC_DMA_INT_STATE_OFFSET 0x8 #define GC_DMA_INT_STATE_DEFAULT 0x0 #define GC_DMA_INT_TEST_OFFSET 0xc #define GC_DMA_INT_TEST_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN0_OFFSET 0x104 +#define GC_DMA_START_CHAN0_OFFSET 0x100 +#define GC_DMA_START_CHAN0_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN0_OFFSET 0x104 +#define GC_DMA_STOP_CHAN0_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN0_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN0_OFFSET 0x10c #define GC_DMA_SRC_ADDR_CHAN0_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN0_OFFSET 0x108 +#define GC_DMA_DST_ADDR_CHAN0_OFFSET 0x110 #define GC_DMA_DST_ADDR_CHAN0_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x10c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x114 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN0_OFFSET 0x110 +#define GC_DMA_PROG_COUNT_CHAN0_OFFSET 0x118 #define GC_DMA_PROG_COUNT_CHAN0_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x114 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x11c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN0_OFFSET 0x118 -#define GC_DMA_RETRY_WAIT_TIME_CHAN0_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET 0x11c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x120 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET 0x120 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x124 #define GC_DMA_FSM_STATE_CHAN0_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN1_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN1_OFFSET 0x204 +#define GC_DMA_START_CHAN1_OFFSET 0x200 +#define GC_DMA_START_CHAN1_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN1_OFFSET 0x204 +#define GC_DMA_STOP_CHAN1_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN1_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN1_OFFSET 0x20c #define GC_DMA_SRC_ADDR_CHAN1_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN1_OFFSET 0x208 +#define GC_DMA_DST_ADDR_CHAN1_OFFSET 0x210 #define GC_DMA_DST_ADDR_CHAN1_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x20c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x214 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN1_OFFSET 0x210 +#define GC_DMA_PROG_COUNT_CHAN1_OFFSET 0x218 #define GC_DMA_PROG_COUNT_CHAN1_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x214 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x21c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN1_OFFSET 0x218 -#define GC_DMA_RETRY_WAIT_TIME_CHAN1_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET 0x21c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x220 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET 0x220 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x224 #define GC_DMA_FSM_STATE_CHAN1_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN2_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN2_OFFSET 0x304 +#define GC_DMA_START_CHAN2_OFFSET 0x300 +#define GC_DMA_START_CHAN2_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN2_OFFSET 0x304 +#define GC_DMA_STOP_CHAN2_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN2_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN2_OFFSET 0x30c #define GC_DMA_SRC_ADDR_CHAN2_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN2_OFFSET 0x308 +#define GC_DMA_DST_ADDR_CHAN2_OFFSET 0x310 #define GC_DMA_DST_ADDR_CHAN2_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x30c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x314 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN2_OFFSET 0x310 +#define GC_DMA_PROG_COUNT_CHAN2_OFFSET 0x318 #define GC_DMA_PROG_COUNT_CHAN2_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x314 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x31c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN2_OFFSET 0x318 -#define GC_DMA_RETRY_WAIT_TIME_CHAN2_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET 0x31c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x320 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET 0x320 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x324 #define GC_DMA_FSM_STATE_CHAN2_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN3_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN3_OFFSET 0x404 +#define GC_DMA_START_CHAN3_OFFSET 0x400 +#define GC_DMA_START_CHAN3_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN3_OFFSET 0x404 +#define GC_DMA_STOP_CHAN3_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN3_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN3_OFFSET 0x40c #define GC_DMA_SRC_ADDR_CHAN3_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN3_OFFSET 0x408 +#define GC_DMA_DST_ADDR_CHAN3_OFFSET 0x410 #define GC_DMA_DST_ADDR_CHAN3_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x40c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x414 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN3_OFFSET 0x410 +#define GC_DMA_PROG_COUNT_CHAN3_OFFSET 0x418 #define GC_DMA_PROG_COUNT_CHAN3_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x414 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x41c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN3_OFFSET 0x418 -#define GC_DMA_RETRY_WAIT_TIME_CHAN3_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET 0x41c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x420 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET 0x420 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x424 #define GC_DMA_FSM_STATE_CHAN3_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN4_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN4_OFFSET 0x504 +#define GC_DMA_START_CHAN4_OFFSET 0x500 +#define GC_DMA_START_CHAN4_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN4_OFFSET 0x504 +#define GC_DMA_STOP_CHAN4_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN4_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN4_OFFSET 0x50c #define GC_DMA_SRC_ADDR_CHAN4_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN4_OFFSET 0x508 +#define GC_DMA_DST_ADDR_CHAN4_OFFSET 0x510 #define GC_DMA_DST_ADDR_CHAN4_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x50c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x514 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN4_OFFSET 0x510 +#define GC_DMA_PROG_COUNT_CHAN4_OFFSET 0x518 #define GC_DMA_PROG_COUNT_CHAN4_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x514 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x51c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN4_OFFSET 0x518 -#define GC_DMA_RETRY_WAIT_TIME_CHAN4_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET 0x51c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x520 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET 0x520 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x524 #define GC_DMA_FSM_STATE_CHAN4_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN5_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN5_OFFSET 0x604 +#define GC_DMA_START_CHAN5_OFFSET 0x600 +#define GC_DMA_START_CHAN5_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN5_OFFSET 0x604 +#define GC_DMA_STOP_CHAN5_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN5_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN5_OFFSET 0x60c #define GC_DMA_SRC_ADDR_CHAN5_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN5_OFFSET 0x608 +#define GC_DMA_DST_ADDR_CHAN5_OFFSET 0x610 #define GC_DMA_DST_ADDR_CHAN5_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x60c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x614 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN5_OFFSET 0x610 +#define GC_DMA_PROG_COUNT_CHAN5_OFFSET 0x618 #define GC_DMA_PROG_COUNT_CHAN5_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x614 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x61c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN5_OFFSET 0x618 -#define GC_DMA_RETRY_WAIT_TIME_CHAN5_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET 0x61c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x620 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET 0x620 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x624 #define GC_DMA_FSM_STATE_CHAN5_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN6_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN6_OFFSET 0x704 +#define GC_DMA_START_CHAN6_OFFSET 0x700 +#define GC_DMA_START_CHAN6_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN6_OFFSET 0x704 +#define GC_DMA_STOP_CHAN6_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN6_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN6_OFFSET 0x70c #define GC_DMA_SRC_ADDR_CHAN6_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN6_OFFSET 0x708 +#define GC_DMA_DST_ADDR_CHAN6_OFFSET 0x710 #define GC_DMA_DST_ADDR_CHAN6_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x70c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x714 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN6_OFFSET 0x710 +#define GC_DMA_PROG_COUNT_CHAN6_OFFSET 0x718 #define GC_DMA_PROG_COUNT_CHAN6_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x714 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x71c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN6_OFFSET 0x718 -#define GC_DMA_RETRY_WAIT_TIME_CHAN6_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET 0x71c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x720 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET 0x720 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x724 #define GC_DMA_FSM_STATE_CHAN6_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN7_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_DEFAULT 0x28 -#define GC_DMA_SRC_ADDR_CHAN7_OFFSET 0x804 +#define GC_DMA_START_CHAN7_OFFSET 0x800 +#define GC_DMA_START_CHAN7_DEFAULT 0x0 +#define GC_DMA_STOP_CHAN7_OFFSET 0x804 +#define GC_DMA_STOP_CHAN7_DEFAULT 0x0 +#define GC_DMA_CTRL_CHAN7_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_DEFAULT 0xa +#define GC_DMA_SRC_ADDR_CHAN7_OFFSET 0x80c #define GC_DMA_SRC_ADDR_CHAN7_DEFAULT 0x0 -#define GC_DMA_DST_ADDR_CHAN7_OFFSET 0x808 +#define GC_DMA_DST_ADDR_CHAN7_OFFSET 0x810 #define GC_DMA_DST_ADDR_CHAN7_DEFAULT 0x0 -#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x80c +#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x814 #define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x3ff -#define GC_DMA_PROG_COUNT_CHAN7_OFFSET 0x810 +#define GC_DMA_PROG_COUNT_CHAN7_OFFSET 0x818 #define GC_DMA_PROG_COUNT_CHAN7_DEFAULT 0x0 -#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x814 +#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x81c #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x0 -#define GC_DMA_RETRY_WAIT_TIME_CHAN7_OFFSET 0x818 -#define GC_DMA_RETRY_WAIT_TIME_CHAN7_DEFAULT 0x80 -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET 0x81c -#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT 0x64 -#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x820 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET 0x820 +#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT 0xf9f +#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x824 #define GC_DMA_FSM_STATE_CHAN7_DEFAULT 0x1 #define GC_FLASH_FSH_PE_CONTROL0_OFFSET 0x0 #define GC_FLASH_FSH_PE_CONTROL0_DEFAULT 0x0 @@ -802,188 +822,194 @@ #define GC_FLASH_FSH_PE_CONTROL1_READ 0x16021765 #define GC_FLASH_FSH_TRANS_OFFSET 0x8 #define GC_FLASH_FSH_TRANS_DEFAULT 0x0 -#define GC_FLASH_FSH_ENABLE_INFO1_OFFSET 0xc -#define GC_FLASH_FSH_ENABLE_INFO1_DEFAULT 0x0 -#define GC_FLASH_FSH_ICTRL_OFFSET 0x10 +#define GC_FLASH_FSH_PROTECT_INFO1_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_DEFAULT 0x0 +#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_OFFSET 0x10 +#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_DEFAULT 0x0 +#define GC_FLASH_FSH_ICTRL_OFFSET 0x14 #define GC_FLASH_FSH_ICTRL_DEFAULT 0x0 -#define GC_FLASH_FSH_ISTATE_OFFSET 0x14 +#define GC_FLASH_FSH_ISTATE_OFFSET 0x18 #define GC_FLASH_FSH_ISTATE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD0_UNLOCK_OFFSET 0x18 +#define GC_FLASH_FSH_OVRD0_UNLOCK_OFFSET 0x1c #define GC_FLASH_FSH_OVRD0_UNLOCK_DEFAULT 0x0 #define GC_FLASH_FSH_OVRD0_UNLOCK_KEY 0x13806488 -#define GC_FLASH_FSH_OVRD1_UNLOCK_OFFSET 0x1c +#define GC_FLASH_FSH_OVRD1_UNLOCK_OFFSET 0x20 #define GC_FLASH_FSH_OVRD1_UNLOCK_DEFAULT 0x0 #define GC_FLASH_FSH_OVRD1_UNLOCK_KEY 0x13806488 -#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_OFFSET 0x20 +#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_OFFSET 0x24 #define GC_FLASH_FSH_OVRD_SIGVAL_DIN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_OFFSET 0x24 +#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_OFFSET 0x28 #define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_DEFAULT 0x0 -#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_OFFSET 0x30 +#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_OFFSET 0x34 #define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_DEFAULT 0x0 -#define GC_FLASH_FSH_DOUT_VAL0_OFFSET 0x34 +#define GC_FLASH_FSH_DOUT_VAL0_OFFSET 0x38 #define GC_FLASH_FSH_DOUT_VAL0_DEFAULT 0x0 -#define GC_FLASH_FSH_DOUT_VAL1_OFFSET 0x38 +#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_OFFSET 0x3c +#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_DEFAULT 0x0 +#define GC_FLASH_FSH_DOUT_VAL1_OFFSET 0x40 #define GC_FLASH_FSH_DOUT_VAL1_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA0_OFFSET 0x3c +#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_OFFSET 0x44 +#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_DEFAULT 0x0 +#define GC_FLASH_FSH_WR_DATA0_OFFSET 0x48 #define GC_FLASH_FSH_WR_DATA0_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA1_OFFSET 0x40 +#define GC_FLASH_FSH_WR_DATA1_OFFSET 0x4c #define GC_FLASH_FSH_WR_DATA1_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA2_OFFSET 0x44 +#define GC_FLASH_FSH_WR_DATA2_OFFSET 0x50 #define GC_FLASH_FSH_WR_DATA2_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA3_OFFSET 0x48 +#define GC_FLASH_FSH_WR_DATA3_OFFSET 0x54 #define GC_FLASH_FSH_WR_DATA3_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA4_OFFSET 0x4c +#define GC_FLASH_FSH_WR_DATA4_OFFSET 0x58 #define GC_FLASH_FSH_WR_DATA4_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA5_OFFSET 0x50 +#define GC_FLASH_FSH_WR_DATA5_OFFSET 0x5c #define GC_FLASH_FSH_WR_DATA5_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA6_OFFSET 0x54 +#define GC_FLASH_FSH_WR_DATA6_OFFSET 0x60 #define GC_FLASH_FSH_WR_DATA6_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA7_OFFSET 0x58 +#define GC_FLASH_FSH_WR_DATA7_OFFSET 0x64 #define GC_FLASH_FSH_WR_DATA7_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA8_OFFSET 0x5c +#define GC_FLASH_FSH_WR_DATA8_OFFSET 0x68 #define GC_FLASH_FSH_WR_DATA8_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA9_OFFSET 0x60 +#define GC_FLASH_FSH_WR_DATA9_OFFSET 0x6c #define GC_FLASH_FSH_WR_DATA9_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA10_OFFSET 0x64 +#define GC_FLASH_FSH_WR_DATA10_OFFSET 0x70 #define GC_FLASH_FSH_WR_DATA10_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA11_OFFSET 0x68 +#define GC_FLASH_FSH_WR_DATA11_OFFSET 0x74 #define GC_FLASH_FSH_WR_DATA11_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA12_OFFSET 0x6c +#define GC_FLASH_FSH_WR_DATA12_OFFSET 0x78 #define GC_FLASH_FSH_WR_DATA12_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA13_OFFSET 0x70 +#define GC_FLASH_FSH_WR_DATA13_OFFSET 0x7c #define GC_FLASH_FSH_WR_DATA13_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA14_OFFSET 0x74 +#define GC_FLASH_FSH_WR_DATA14_OFFSET 0x80 #define GC_FLASH_FSH_WR_DATA14_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA15_OFFSET 0x78 +#define GC_FLASH_FSH_WR_DATA15_OFFSET 0x84 #define GC_FLASH_FSH_WR_DATA15_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA16_OFFSET 0x7c +#define GC_FLASH_FSH_WR_DATA16_OFFSET 0x88 #define GC_FLASH_FSH_WR_DATA16_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA17_OFFSET 0x80 +#define GC_FLASH_FSH_WR_DATA17_OFFSET 0x8c #define GC_FLASH_FSH_WR_DATA17_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA18_OFFSET 0x84 +#define GC_FLASH_FSH_WR_DATA18_OFFSET 0x90 #define GC_FLASH_FSH_WR_DATA18_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA19_OFFSET 0x88 +#define GC_FLASH_FSH_WR_DATA19_OFFSET 0x94 #define GC_FLASH_FSH_WR_DATA19_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA20_OFFSET 0x8c +#define GC_FLASH_FSH_WR_DATA20_OFFSET 0x98 #define GC_FLASH_FSH_WR_DATA20_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA21_OFFSET 0x90 +#define GC_FLASH_FSH_WR_DATA21_OFFSET 0x9c #define GC_FLASH_FSH_WR_DATA21_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA22_OFFSET 0x94 +#define GC_FLASH_FSH_WR_DATA22_OFFSET 0xa0 #define GC_FLASH_FSH_WR_DATA22_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA23_OFFSET 0x98 +#define GC_FLASH_FSH_WR_DATA23_OFFSET 0xa4 #define GC_FLASH_FSH_WR_DATA23_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA24_OFFSET 0x9c +#define GC_FLASH_FSH_WR_DATA24_OFFSET 0xa8 #define GC_FLASH_FSH_WR_DATA24_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA25_OFFSET 0xa0 +#define GC_FLASH_FSH_WR_DATA25_OFFSET 0xac #define GC_FLASH_FSH_WR_DATA25_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA26_OFFSET 0xa4 +#define GC_FLASH_FSH_WR_DATA26_OFFSET 0xb0 #define GC_FLASH_FSH_WR_DATA26_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA27_OFFSET 0xa8 +#define GC_FLASH_FSH_WR_DATA27_OFFSET 0xb4 #define GC_FLASH_FSH_WR_DATA27_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA28_OFFSET 0xac +#define GC_FLASH_FSH_WR_DATA28_OFFSET 0xb8 #define GC_FLASH_FSH_WR_DATA28_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA29_OFFSET 0xb0 +#define GC_FLASH_FSH_WR_DATA29_OFFSET 0xbc #define GC_FLASH_FSH_WR_DATA29_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA30_OFFSET 0xb4 +#define GC_FLASH_FSH_WR_DATA30_OFFSET 0xc0 #define GC_FLASH_FSH_WR_DATA30_DEFAULT 0x0 -#define GC_FLASH_FSH_WR_DATA31_OFFSET 0xb8 +#define GC_FLASH_FSH_WR_DATA31_OFFSET 0xc4 #define GC_FLASH_FSH_WR_DATA31_DEFAULT 0x0 -#define GC_FLASH_FSH_PE_EN_OFFSET 0xbc +#define GC_FLASH_FSH_PE_EN_OFFSET 0xc8 #define GC_FLASH_FSH_PE_EN_DEFAULT 0x0 #define GC_FLASH_FSH_PE_EN_KEY 0xb11924e1 -#define GC_FLASH_FSH_REDUN0_OFFSET 0xc0 +#define GC_FLASH_FSH_REDUN0_OFFSET 0xcc #define GC_FLASH_FSH_REDUN0_DEFAULT 0x0 -#define GC_FLASH_FSH_REDUN1_OFFSET 0xc4 +#define GC_FLASH_FSH_REDUN1_OFFSET 0xd0 #define GC_FLASH_FSH_REDUN1_DEFAULT 0x0 -#define GC_FLASH_FSH_ERROR_OFFSET 0xc8 +#define GC_FLASH_FSH_ERROR_OFFSET 0xd4 #define GC_FLASH_FSH_ERROR_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_OFFSET 0xcc +#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_OFFSET 0xd8 #define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_OFFSET 0xd0 +#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_OFFSET 0xdc #define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_OFFSET 0xd4 +#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_OFFSET 0xe0 #define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_OFFSET 0xd8 +#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_OFFSET 0xe4 #define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_OFFSET 0xdc +#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_OFFSET 0xe8 #define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_OFFSET 0xe0 +#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_OFFSET 0xec #define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_OFFSET 0xe4 +#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_OFFSET 0xf0 #define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_OFFSET 0xe8 +#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_OFFSET 0xf4 #define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_OFFSET 0xec +#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_OFFSET 0xf8 #define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_OFFSET 0xf0 +#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_OFFSET 0xfc #define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_OFFSET 0xf4 +#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_OFFSET 0x100 #define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_OFFSET 0xf8 +#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_OFFSET 0x104 #define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_OFFSET 0xfc +#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_OFFSET 0x108 #define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_DEFAULT 0x30e -#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_OFFSET 0x100 +#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_OFFSET 0x10c #define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_OFFSET 0x104 +#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_OFFSET 0x110 #define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_DEFAULT 0x21b -#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_OFFSET 0x108 +#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_OFFSET 0x114 #define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_DEFAULT 0x16e -#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_OFFSET 0x10c +#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_OFFSET 0x118 #define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_DEFAULT 0x19f -#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_OFFSET 0x110 +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_OFFSET 0x11c #define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_DEFAULT 0x16d -#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_OFFSET 0x114 +#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_OFFSET 0x120 #define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_DEFAULT 0x1a0 -#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_OFFSET 0x118 +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_OFFSET 0x124 #define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_OFFSET 0x11c +#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_OFFSET 0x128 #define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_DEFAULT 0x1a0 -#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_OFFSET 0x120 +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_OFFSET 0x12c #define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_DEFAULT 0x7a -#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_OFFSET 0x124 +#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_OFFSET 0x130 #define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_DEFAULT 0x21a -#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_OFFSET 0x128 +#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_OFFSET 0x134 #define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_OFFSET 0x12c +#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_OFFSET 0x138 #define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_DEFAULT 0xc075 -#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_OFFSET 0x130 +#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_OFFSET 0x13c #define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_OFFSET 0x134 +#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_OFFSET 0x140 #define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_DEFAULT 0xbf82 -#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_OFFSET 0x138 +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_OFFSET 0x144 #define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_OFFSET 0x13c +#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_OFFSET 0x148 #define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_DEFAULT 0xbf07 -#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_OFFSET 0x140 +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_OFFSET 0x14c #define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_DEFAULT 0x7a -#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_OFFSET 0x144 +#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_OFFSET 0x150 #define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_DEFAULT 0xbf81 -#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_OFFSET 0x148 +#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_OFFSET 0x154 #define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_OFFSET 0x14c +#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_OFFSET 0x158 #define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_DEFAULT 0xc982 -#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_OFFSET 0x150 +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_OFFSET 0x15c #define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_OFFSET 0x154 +#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_OFFSET 0x160 #define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_DEFAULT 0xc88f -#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_OFFSET 0x158 +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_OFFSET 0x164 #define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_DEFAULT 0x1 -#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_OFFSET 0x15c +#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_OFFSET 0x168 #define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_DEFAULT 0xbf07 -#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_OFFSET 0x160 +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_OFFSET 0x16c #define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_DEFAULT 0x0 -#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_OFFSET 0x164 +#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_OFFSET 0x170 #define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_DEFAULT 0xc88f -#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_OFFSET 0x168 +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_OFFSET 0x174 #define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_DEFAULT 0x7a -#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_OFFSET 0x16c +#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_OFFSET 0x178 #define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_DEFAULT 0xc88e -#define GC_FLASH_FSH_DBG_OFFSET 0x170 +#define GC_FLASH_FSH_DBG_OFFSET 0x17c #define GC_FLASH_FSH_DBG_DEFAULT 0x0 #define GC_FLASH_FSH_ITCR_OFFSET 0xf00 #define GC_FLASH_FSH_ITCR_DEFAULT 0x0 @@ -991,530 +1017,800 @@ #define GC_FLASH_FSH_ITOP_DEFAULT 0x0 #define GC_FUSE_STATUS_OFFSET 0x0 #define GC_FUSE_STATUS_DEFAULT 0x0 -#define GC_FUSE_STATUS_CLR_OFFSET 0x4 -#define GC_FUSE_STATUS_CLR_DEFAULT 0x0 -#define GC_FUSE_READ_START_OFFSET 0x8 +#define GC_FUSE_READ_START_OFFSET 0x4 #define GC_FUSE_READ_START_DEFAULT 0x0 -#define GC_FUSE_READ_START_ENABLE 0x0 +#define GC_FUSE_READ_START_ENABLE 0xc8eca61e #define GC_FUSE_READ_START_DISABLE 0x0 -#define GC_FUSE_WRITE_START_OFFSET 0xc -#define GC_FUSE_WRITE_START_DEFAULT 0x0 -#define GC_FUSE_WRITE_START_ENABLE 0x0 -#define GC_FUSE_WRITE_START_DISABLE 0x0 -#define GC_FUSE_SCRUB_LFSR_OFFSET 0x10 -#define GC_FUSE_SCRUB_LFSR_DEFAULT 0x0 -#define GC_FUSE_SCRUB_CTRL_OFFSET 0x14 -#define GC_FUSE_SCRUB_CTRL_DEFAULT 0xffff -#define GC_FUSE_ERROR_INJECTION_OFFSET 0x18 -#define GC_FUSE_ERROR_INJECTION_DEFAULT 0x0 -#define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET 0x1c +#define GC_FUSE_PROG_START_OFFSET 0x8 +#define GC_FUSE_PROG_START_DEFAULT 0x0 +#define GC_FUSE_PROG_START_ENABLE 0xdc98157b +#define GC_FUSE_PROG_START_DISABLE 0x0 +#define GC_FUSE_OVERRIDE_START_OFFSET 0xc +#define GC_FUSE_OVERRIDE_START_DEFAULT 0x0 +#define GC_FUSE_OVERRIDE_START_ENABLE 0x894e4cf3 +#define GC_FUSE_OVERRIDE_START_DISABLE 0x0 +#define GC_FUSE_FPGA_MODEL_CTRL_OFFSET 0x10 +#define GC_FUSE_FPGA_MODEL_CTRL_DEFAULT 0x0 +#define GC_FUSE_SCRUB_PRBS_CLK_DIV_OFFSET 0x14 +#define GC_FUSE_SCRUB_PRBS_CLK_DIV_DEFAULT 0xffffff +#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_OFFSET 0x18 +#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_DEFAULT 0x7fff +#define GC_FUSE_SCRUB_ENABLE_OFFSET 0x1c +#define GC_FUSE_SCRUB_ENABLE_DEFAULT 0x0 +#define GC_FUSE_SCRUB_ENABLE_ENABLE 0x5 +#define GC_FUSE_SCRUB_ENABLE_DISABLE 0x0 +#define GC_FUSE_ERROR_INJECT_OFFSET 0x20 +#define GC_FUSE_ERROR_INJECT_DEFAULT 0x0 +#define GC_FUSE_ERROR_INJECT_ENABLE 0x690c7334 +#define GC_FUSE_ERROR_INJECT_DISABLE 0x0 +#define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET 0x24 #define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT 0x1d4c0 -#define GC_FUSE_VERSION_OFFSET 0x20 -#define GC_FUSE_VERSION_DEFAULT 0x3010240 -#define GC_FUSE_INT_ENABLE_OFFSET 0x24 -#define GC_FUSE_INT_ENABLE_DEFAULT 0x0 -#define GC_FUSE_INT_STATE_OFFSET 0x28 -#define GC_FUSE_INT_STATE_DEFAULT 0x0 -#define GC_FUSE_INT_TEST_OFFSET 0x2c -#define GC_FUSE_INT_TEST_DEFAULT 0x0 -#define GC_FUSE_DS_GRP0_OFFSET 0x30 -#define GC_FUSE_DS_GRP0_DEFAULT 0x0 -#define GC_FUSE_DS_GRP1_OFFSET 0x34 -#define GC_FUSE_DS_GRP1_DEFAULT 0x0 -#define GC_FUSE_DS_GRP2_OFFSET 0x38 -#define GC_FUSE_DS_GRP2_DEFAULT 0x0 -#define GC_FUSE_DEV_ID0_OFFSET 0x3c +#define GC_FUSE_VERSION_OFFSET 0x28 +#define GC_FUSE_VERSION_DEFAULT 0xf011cd4 +#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x2c +#define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT 0x55000000 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_OFFSET 0x30 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_DS_GRP0_OFFSET 0x34 +#define GC_FUSE_DS_GRP0_DEFAULT 0x55555400 +#define GC_FUSE_DS_GRP1_OFFSET 0x38 +#define GC_FUSE_DS_GRP1_DEFAULT 0x55555400 +#define GC_FUSE_DS_GRP2_OFFSET 0x3c +#define GC_FUSE_DS_GRP2_DEFAULT 0x55555400 +#define GC_FUSE_DEV_ID0_OFFSET 0x40 #define GC_FUSE_DEV_ID0_DEFAULT 0x0 -#define GC_FUSE_DEV_ID1_OFFSET 0x40 +#define GC_FUSE_DEV_ID1_OFFSET 0x44 #define GC_FUSE_DEV_ID1_DEFAULT 0x0 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_OFFSET 0x44 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x48 -#define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x4c -#define GC_FUSE_LB0_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x50 -#define GC_FUSE_LB0_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x54 -#define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x58 -#define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x5c -#define GC_FUSE_LB1_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x60 -#define GC_FUSE_LB1_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x64 -#define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x68 -#define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x6c -#define GC_FUSE_LB2_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x70 -#define GC_FUSE_LB2_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x74 -#define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x78 -#define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x7c -#define GC_FUSE_LB3_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x80 -#define GC_FUSE_LB3_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x84 -#define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x88 -#define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0x8c -#define GC_FUSE_MBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0x90 -#define GC_FUSE_LBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0x94 -#define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0x98 -#define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_TAP_DISABLE_OFFSET 0x9c -#define GC_FUSE_TAP_DISABLE_DEFAULT 0x0 -#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xa0 -#define GC_FUSE_RNGBIST_AR_EN_DEFAULT 0x0 -#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xa4 -#define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT 0x0 -#define GC_FUSE_PKG_ID_OFFSET 0xa8 -#define GC_FUSE_PKG_ID_DEFAULT 0x0 -#define GC_FUSE_BIN_ID_OFFSET 0xac -#define GC_FUSE_BIN_ID_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xb0 -#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xb4 -#define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xb8 -#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xbc -#define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xc0 -#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xc4 -#define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xc8 -#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xcc -#define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 -#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_OFFSET 0xd0 -#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_RC_RTC_OSC32K_CC_EN_OFFSET 0xd4 -#define GC_FUSE_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 -#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xd8 -#define GC_FUSE_SEL_VREG_REG_EN_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_REG_OFFSET 0xdc -#define GC_FUSE_SEL_VREF_REG_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xe0 -#define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xe4 -#define GC_FUSE_SEL_VREF_BATMON_DEFAULT 0x0 -#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0xe8 -#define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 -#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0xec -#define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT 0x0 -#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0xf0 -#define GC_FUSE_EXT_XTAL_PDB_DEFAULT 0x0 -#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0xf4 -#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 -#define GC_FUSE_OBFUSCATION_EN_OFFSET 0xf8 -#define GC_FUSE_OBFUSCATION_EN_DEFAULT 0x0 -#define GC_FUSE_JITTER_CLK_EN_OFFSET 0xfc -#define GC_FUSE_JITTER_CLK_EN_DEFAULT 0x0 -#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x100 -#define GC_FUSE_HIK_CREATE_LOCK_DEFAULT 0x0 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_OFFSET 0x104 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x108 -#define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x10c -#define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT 0x0 -#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x110 -#define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 -#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET 0x114 -#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0 -#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x118 -#define GC_FUSE_ALERT_RSP_CFG_DEFAULT 0x0 -#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x11c -#define GC_FUSE_BNK2_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x120 -#define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x124 -#define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK1_OFFSET 0x128 -#define GC_FUSE_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK2_OFFSET 0x12c -#define GC_FUSE_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 -#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x130 -#define GC_FUSE_BNK3_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x134 -#define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x138 -#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x13c -#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x140 -#define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 -#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET 0x144 -#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET 0x148 -#define GC_FUSE_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_RBOX_DEBOUNCE_OFFSET 0x14c -#define GC_FUSE_RBOX_DEBOUNCE_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x150 -#define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x154 -#define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x158 -#define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x15c -#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x160 -#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x164 -#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY0_OFFSET 0x168 -#define GC_FUSE_RBOX_BLOCK_KEY0_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY1_OFFSET 0x16c -#define GC_FUSE_RBOX_BLOCK_KEY1_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x170 -#define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x174 -#define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x178 -#define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x17c -#define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x180 -#define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x184 -#define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x188 -#define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x18c -#define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET 0x190 -#define GC_FUSE_RBOX_TERM_ENTERING_RW_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x194 -#define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x198 -#define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x19c -#define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x1a0 -#define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x1a4 -#define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x1a8 -#define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1ac -#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1b0 -#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1b4 -#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DS_GRP0_OFFSET 0x1b8 -#define GC_FUSE_WRITE_SHADOW_DS_GRP0_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DS_GRP1_OFFSET 0x1bc -#define GC_FUSE_WRITE_SHADOW_DS_GRP1_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DS_GRP2_OFFSET 0x1c0 -#define GC_FUSE_WRITE_SHADOW_DS_GRP2_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DEV_ID0_OFFSET 0x1c4 -#define GC_FUSE_WRITE_SHADOW_DEV_ID0_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DEV_ID1_OFFSET 0x1c8 -#define GC_FUSE_WRITE_SHADOW_DEV_ID1_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_N_WR_LOCK_OFFSET 0x1cc -#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_CHKSUM_OFFSET 0x1d0 -#define GC_FUSE_WRITE_SHADOW_BNK0_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_OVRD_OFFSET 0x1d4 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_PATCNT_OFFSET 0x1d8 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_OVRD_OFFSET 0x1dc -#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_CNT_OFFSET 0x1e0 -#define GC_FUSE_WRITE_SHADOW_LB0_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_OVRD_OFFSET 0x1e4 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_PATCNT_OFFSET 0x1e8 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_OVRD_OFFSET 0x1ec -#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_CNT_OFFSET 0x1f0 -#define GC_FUSE_WRITE_SHADOW_LB1_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_OVRD_OFFSET 0x1f4 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_PATCNT_OFFSET 0x1f8 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_OVRD_OFFSET 0x1fc -#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_CNT_OFFSET 0x200 -#define GC_FUSE_WRITE_SHADOW_LB2_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_OVRD_OFFSET 0x204 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_PATCNT_OFFSET 0x208 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_OVRD_OFFSET 0x20c -#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_CNT_OFFSET 0x210 -#define GC_FUSE_WRITE_SHADOW_LB3_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_MBIST_POST_SEQ_OFFSET 0x214 -#define GC_FUSE_WRITE_SHADOW_MBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LBIST_POST_SEQ_OFFSET 0x218 -#define GC_FUSE_WRITE_SHADOW_LBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_LBIST_VIA_TAP_DIS_OFFSET 0x21c -#define GC_FUSE_WRITE_SHADOW_LBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_MBIST_VIA_TAP_DIS_OFFSET 0x220 -#define GC_FUSE_WRITE_SHADOW_MBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_TAP_DISABLE_OFFSET 0x224 -#define GC_FUSE_WRITE_SHADOW_TAP_DISABLE_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RNGBIST_AR_EN_OFFSET 0x228 -#define GC_FUSE_WRITE_SHADOW_RNGBIST_AR_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_TESTMODE_KEYS_EN_OFFSET 0x22c -#define GC_FUSE_WRITE_SHADOW_TESTMODE_KEYS_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_PKG_ID_OFFSET 0x230 -#define GC_FUSE_WRITE_SHADOW_PKG_ID_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BIN_ID_OFFSET 0x234 -#define GC_FUSE_WRITE_SHADOW_BIN_ID_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_TRIM_OFFSET 0x238 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_EN_OFFSET 0x23c -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_TRIM_OFFSET 0x240 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_EN_OFFSET 0x244 -#define GC_FUSE_WRITE_SHADOW_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x248 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_EN_OFFSET 0x24c -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x250 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_EN_OFFSET 0x254 -#define GC_FUSE_WRITE_SHADOW_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_TRIM_OFFSET 0x258 -#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_EN_OFFSET 0x25c -#define GC_FUSE_WRITE_SHADOW_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_SEL_VREG_REG_EN_OFFSET 0x260 -#define GC_FUSE_WRITE_SHADOW_SEL_VREG_REG_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_REG_OFFSET 0x264 -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_REG_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_EN_OFFSET 0x268 -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_OFFSET 0x26c -#define GC_FUSE_WRITE_SHADOW_SEL_VREF_BATMON_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_EN_OFFSET 0x270 -#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_OFFSET 0x274 -#define GC_FUSE_WRITE_SHADOW_X_OSC_LDO_CTRL_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_EXT_XTAL_PDB_OFFSET 0x278 -#define GC_FUSE_WRITE_SHADOW_EXT_XTAL_PDB_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x27c -#define GC_FUSE_WRITE_SHADOW_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBFUSCATION_EN_OFFSET 0x280 -#define GC_FUSE_WRITE_SHADOW_OBFUSCATION_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_JITTER_CLK_EN_OFFSET 0x284 -#define GC_FUSE_WRITE_SHADOW_JITTER_CLK_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS0_OFFSET 0x288 -#define GC_FUSE_WRITE_SHADOW_OBS0_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS1_OFFSET 0x28c -#define GC_FUSE_WRITE_SHADOW_OBS1_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS2_OFFSET 0x290 -#define GC_FUSE_WRITE_SHADOW_OBS2_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS3_OFFSET 0x294 -#define GC_FUSE_WRITE_SHADOW_OBS3_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS4_OFFSET 0x298 -#define GC_FUSE_WRITE_SHADOW_OBS4_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS5_OFFSET 0x29c -#define GC_FUSE_WRITE_SHADOW_OBS5_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS6_OFFSET 0x2a0 -#define GC_FUSE_WRITE_SHADOW_OBS6_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_OBS7_OFFSET 0x2a4 -#define GC_FUSE_WRITE_SHADOW_OBS7_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_HIK_CREATE_LOCK_OFFSET 0x2a8 -#define GC_FUSE_WRITE_SHADOW_HIK_CREATE_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_N_WR_LOCK_OFFSET 0x2ac -#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_CHKSUM_OFFSET 0x2b0 -#define GC_FUSE_WRITE_SHADOW_BNK1_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_TESTMODE_OTPW_DIS_OFFSET 0x2b4 -#define GC_FUSE_WRITE_SHADOW_TESTMODE_OTPW_DIS_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_HKEY_WDOG_TIMER_EN_OFFSET 0x2b8 -#define GC_FUSE_WRITE_SHADOW_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_FLASH_PERSO_PAGE_LOCK_OFFSET 0x2bc -#define GC_FUSE_WRITE_SHADOW_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_ALERT_RSP_CFG_OFFSET 0x2c0 -#define GC_FUSE_WRITE_SHADOW_ALERT_RSP_CFG_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_LOCK_OFFSET 0x2c4 -#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_CHKSUM_OFFSET 0x2c8 -#define GC_FUSE_WRITE_SHADOW_BNK2_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK0_OFFSET 0x2cc -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK1_OFFSET 0x2d0 -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK2_OFFSET 0x2d4 -#define GC_FUSE_WRITE_SHADOW_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_LOCK_OFFSET 0x2d8 -#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_CHKSUM_OFFSET 0x2dc -#define GC_FUSE_WRITE_SHADOW_BNK3_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x2e0 -#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x2e4 -#define GC_FUSE_WRITE_SHADOW_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_CLK10HZ_COUNT_OFFSET 0x2e8 -#define GC_FUSE_WRITE_SHADOW_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_SHORT_DELAY_COUNT_OFFSET 0x2ec -#define GC_FUSE_WRITE_SHADOW_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_LONG_DELAY_COUNT_OFFSET 0x2f0 -#define GC_FUSE_WRITE_SHADOW_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_DEBOUNCE_OFFSET 0x2f4 -#define GC_FUSE_WRITE_SHADOW_RBOX_DEBOUNCE_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_VAL_OFFSET 0x2f8 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_VAL_OFFSET 0x2fc -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_VAL_OFFSET 0x300 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_HOLD_OFFSET 0x304 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_HOLD_OFFSET 0x308 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_HOLD_OFFSET 0x30c -#define GC_FUSE_WRITE_SHADOW_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY0_OFFSET 0x310 -#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY0_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY1_OFFSET 0x314 -#define GC_FUSE_WRITE_SHADOW_RBOX_BLOCK_KEY1_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_AC_PRESENT_OFFSET 0x318 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_IN_OFFSET 0x31c -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_OUT_OFFSET 0x320 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_IN_OFFSET 0x324 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_OUT_OFFSET 0x328 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_IN_OFFSET 0x32c -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_OUT_OFFSET 0x330 -#define GC_FUSE_WRITE_SHADOW_RBOX_POL_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_AC_PRESENT_OFFSET 0x334 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_ENTERING_RW_OFFSET 0x338 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_ENTERING_RW_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_IN_OFFSET 0x33c -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_OUT_OFFSET 0x340 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_IN_OFFSET 0x344 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_OUT_OFFSET 0x348 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_IN_OFFSET 0x34c -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_OUT_OFFSET 0x350 -#define GC_FUSE_WRITE_SHADOW_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_PWRB_OUT_OFFSET 0x354 -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY0_OUT_OFFSET 0x358 -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY1_OUT_OFFSET 0x35c -#define GC_FUSE_WRITE_SHADOW_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_DEFAULT 0xbfff -#define GC_GLOBALSEC_SRAM0_REGION0_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_DEFAULT 0xbfff -#define GC_GLOBALSEC_SRAM0_REGION1_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DEFAULT 0xbfff -#define GC_GLOBALSEC_SRAM1_REGION0_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DEFAULT 0xbfff -#define GC_GLOBALSEC_SRAM1_REGION1_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH0_REGION0_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH0_REGION1_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH0_REGION2_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH0_REGION3_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH1_REGION0_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH1_REGION1_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH1_REGION2_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_DEFAULT 0xbfff -#define GC_GLOBALSEC_FLASH1_REGION3_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_DEFAULT 0xbfff -#define GC_GLOBALSEC_ROM0_REGION0_BASE_ADDR_OFFSET 0x34 -#define GC_GLOBALSEC_ROM0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_SIZE_OFFSET 0x38 -#define GC_GLOBALSEC_ROM0_REGION0_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_SRAM0_REGION0_BASE_ADDR_OFFSET 0x3c -#define GC_GLOBALSEC_SRAM0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM0_REGION0_SIZE_OFFSET 0x40 -#define GC_GLOBALSEC_SRAM0_REGION0_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_SRAM0_REGION1_BASE_ADDR_OFFSET 0x44 -#define GC_GLOBALSEC_SRAM0_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM0_REGION1_SIZE_OFFSET 0x48 -#define GC_GLOBALSEC_SRAM0_REGION1_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_SRAM1_REGION0_BASE_ADDR_OFFSET 0x4c -#define GC_GLOBALSEC_SRAM1_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM1_REGION0_SIZE_OFFSET 0x50 -#define GC_GLOBALSEC_SRAM1_REGION0_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_SRAM1_REGION1_BASE_ADDR_OFFSET 0x54 -#define GC_GLOBALSEC_SRAM1_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM1_REGION1_SIZE_OFFSET 0x58 -#define GC_GLOBALSEC_SRAM1_REGION1_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_OFFSET 0x5c -#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_OFFSET 0x60 -#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_OFFSET 0x64 -#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_OFFSET 0x68 -#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_OFFSET 0x6c -#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_OFFSET 0x70 -#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_OFFSET 0x74 -#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_OFFSET 0x78 -#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_OFFSET 0x7c -#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_OFFSET 0x80 -#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_OFFSET 0x84 -#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_OFFSET 0x88 -#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_OFFSET 0x8c -#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_OFFSET 0x90 -#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_OFFSET 0x94 -#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_OFFSET 0x98 -#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_DEFAULT 0xffff -#define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_OFFSET 0x9c +#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x48 +#define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT 0x55000000 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_OFFSET 0x4c +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x50 +#define GC_FUSE_LB0_POST_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x54 +#define GC_FUSE_LB0_POST_PATCNT_DEFAULT 0x55555554 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x58 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x5c +#define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT 0x55555554 +#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x60 +#define GC_FUSE_LB1_POST_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x64 +#define GC_FUSE_LB1_POST_PATCNT_DEFAULT 0x55555554 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x68 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x6c +#define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT 0x55555554 +#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x70 +#define GC_FUSE_LB2_POST_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x74 +#define GC_FUSE_LB2_POST_PATCNT_DEFAULT 0x55555554 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x78 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x7c +#define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT 0x55555554 +#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x80 +#define GC_FUSE_LB3_POST_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x84 +#define GC_FUSE_LB3_POST_PATCNT_DEFAULT 0x55555554 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x88 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT 0x55555550 +#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x8c +#define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT 0x55555554 +#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0x90 +#define GC_FUSE_MBIST_POST_SEQ_DEFAULT 0x54000000 +#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0x94 +#define GC_FUSE_LBIST_POST_SEQ_DEFAULT 0x55550000 +#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0x98 +#define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT 0x55555550 +#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0x9c +#define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT 0x55555550 +#define GC_FUSE_TAP_DISABLE_OFFSET 0xa0 +#define GC_FUSE_TAP_DISABLE_DEFAULT 0x55555550 +#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xa4 +#define GC_FUSE_RNGBIST_AR_EN_DEFAULT 0x55555550 +#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xa8 +#define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT 0x55555550 +#define GC_FUSE_PKG_ID_OFFSET 0xac +#define GC_FUSE_PKG_ID_DEFAULT 0x55555550 +#define GC_FUSE_BIN_ID_OFFSET 0xb0 +#define GC_FUSE_BIN_ID_DEFAULT 0x55555550 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xb4 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x55555500 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xb8 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT 0x55555550 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xbc +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x55555500 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xc0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT 0x55555550 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xc4 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x55555500 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xc8 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT 0x55555550 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xcc +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x55555540 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xd0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT 0x55555550 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_OFFSET 0xd4 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x55555500 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_OFFSET 0xd8 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_DEFAULT 0x55555550 +#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xdc +#define GC_FUSE_SEL_VREG_REG_EN_DEFAULT 0x55555550 +#define GC_FUSE_SEL_VREF_REG_OFFSET 0xe0 +#define GC_FUSE_SEL_VREF_REG_DEFAULT 0x55555550 +#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xe4 +#define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT 0x55555550 +#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xe8 +#define GC_FUSE_SEL_VREF_BATMON_DEFAULT 0x55555550 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0xec +#define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT 0x55555550 +#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0xf0 +#define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT 0x55555550 +#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0xf4 +#define GC_FUSE_EXT_XTAL_PDB_DEFAULT 0x55555554 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0xf8 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x55555550 +#define GC_FUSE_OBFUSCATION_EN_OFFSET 0xfc +#define GC_FUSE_OBFUSCATION_EN_DEFAULT 0x55555550 +#define GC_FUSE_JITTER_CLK_EN_OFFSET 0x100 +#define GC_FUSE_JITTER_CLK_EN_DEFAULT 0x55555550 +#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x104 +#define GC_FUSE_HIK_CREATE_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x108 +#define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT 0x55000000 +#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x10c +#define GC_FUSE_BNK2_INTG_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x110 +#define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT 0x55555550 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x114 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT 0x55555550 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET 0x118 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x11c +#define GC_FUSE_ALERT_RSP_CFG_DEFAULT 0x55555500 +#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x120 +#define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT 0x55000000 +#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x124 +#define GC_FUSE_BNK3_INTG_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x128 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_OFFSET 0x12c +#define GC_FUSE_FW_DEFINED_DATA_BLK1_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_OFFSET 0x130 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_OFFSET 0x134 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_OFFSET 0x138 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK5_OFFSET 0x13c +#define GC_FUSE_FW_DEFINED_DATA_BLK5_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_OFFSET 0x140 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_OFFSET 0x144 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_OFFSET 0x148 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK9_OFFSET 0x14c +#define GC_FUSE_FW_DEFINED_DATA_BLK9_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_OFFSET 0x150 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_OFFSET 0x154 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x158 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x15c +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x160 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT 0x55550000 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET 0x164 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x55550000 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET 0x168 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_OFFSET 0x16c +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x55550000 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x170 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x174 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x178 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x17c +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x180 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x184 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x188 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x18c +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x190 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x55555500 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_OFFSET 0x194 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_OFFSET 0x198 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_OFFSET 0x19c +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_OFFSET 0x1a0 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x1a4 +#define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x1a8 +#define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x1ac +#define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x1b0 +#define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x1b4 +#define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x1b8 +#define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x1bc +#define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_EC_RST_OFFSET 0x1c0 +#define GC_FUSE_RBOX_POL_EC_RST_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_OFFSET 0x1c4 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x1c8 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET 0x1cc +#define GC_FUSE_RBOX_TERM_ENTERING_RW_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x1d0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x1d4 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x1d8 +#define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x1dc +#define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x1e0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x1e4 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1e8 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1ec +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1f0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DRIVE_EC_RST_OFFSET 0x1f4 +#define GC_FUSE_RBOX_DRIVE_EC_RST_DEFAULT 0x55555554 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x1f8 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x55555554 +#define GC_FUSE_BNK4_INTG_CHKSUM_OFFSET 0x1fc +#define GC_FUSE_BNK4_INTG_CHKSUM_DEFAULT 0x55000000 +#define GC_FUSE_BNK4_INTG_LOCK_OFFSET 0x200 +#define GC_FUSE_BNK4_INTG_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x204 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x208 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x20c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x210 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x214 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x218 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x21c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x220 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x224 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x228 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_DEFAULT 0x55555500 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x22c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_DEFAULT 0x55555500 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_OFFSET 0x230 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_OFFSET 0x234 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP0_OFFSET 0x238 +#define GC_FUSE_PROG_DS_GRP0_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP1_OFFSET 0x23c +#define GC_FUSE_PROG_DS_GRP1_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP2_OFFSET 0x240 +#define GC_FUSE_PROG_DS_GRP2_DEFAULT 0x0 +#define GC_FUSE_PROG_DEV_ID0_OFFSET 0x244 +#define GC_FUSE_PROG_DEV_ID0_DEFAULT 0x0 +#define GC_FUSE_PROG_DEV_ID1_OFFSET 0x248 +#define GC_FUSE_PROG_DEV_ID1_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_OFFSET 0x24c +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_OFFSET 0x250 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_OVRD_OFFSET 0x254 +#define GC_FUSE_PROG_LB0_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_PATCNT_OFFSET 0x258 +#define GC_FUSE_PROG_LB0_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_OFFSET 0x25c +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_OFFSET 0x260 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_OVRD_OFFSET 0x264 +#define GC_FUSE_PROG_LB1_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_PATCNT_OFFSET 0x268 +#define GC_FUSE_PROG_LB1_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_OFFSET 0x26c +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_OFFSET 0x270 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_OVRD_OFFSET 0x274 +#define GC_FUSE_PROG_LB2_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_PATCNT_OFFSET 0x278 +#define GC_FUSE_PROG_LB2_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_OFFSET 0x27c +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_OFFSET 0x280 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_OVRD_OFFSET 0x284 +#define GC_FUSE_PROG_LB3_POST_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_PATCNT_OFFSET 0x288 +#define GC_FUSE_PROG_LB3_POST_PATCNT_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_OFFSET 0x28c +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_OFFSET 0x290 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_DEFAULT 0x0 +#define GC_FUSE_PROG_MBIST_POST_SEQ_OFFSET 0x294 +#define GC_FUSE_PROG_MBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_PROG_LBIST_POST_SEQ_OFFSET 0x298 +#define GC_FUSE_PROG_LBIST_POST_SEQ_DEFAULT 0x0 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_OFFSET 0x29c +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_OFFSET 0x2a0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_DEFAULT 0x0 +#define GC_FUSE_PROG_TAP_DISABLE_OFFSET 0x2a4 +#define GC_FUSE_PROG_TAP_DISABLE_DEFAULT 0x0 +#define GC_FUSE_PROG_RNGBIST_AR_EN_OFFSET 0x2a8 +#define GC_FUSE_PROG_RNGBIST_AR_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_OFFSET 0x2ac +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_PKG_ID_OFFSET 0x2b0 +#define GC_FUSE_PROG_PKG_ID_DEFAULT 0x0 +#define GC_FUSE_PROG_BIN_ID_OFFSET 0x2b4 +#define GC_FUSE_PROG_BIN_ID_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_OFFSET 0x2b8 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_OFFSET 0x2bc +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_OFFSET 0x2c0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_OFFSET 0x2c4 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x2c8 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_OFFSET 0x2cc +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x2d0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_OFFSET 0x2d4 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_OFFSET 0x2d8 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_OFFSET 0x2dc +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_OFFSET 0x2e0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_REG_OFFSET 0x2e4 +#define GC_FUSE_PROG_SEL_VREF_REG_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_OFFSET 0x2e8 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_OFFSET 0x2ec +#define GC_FUSE_PROG_SEL_VREF_BATMON_DEFAULT 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_OFFSET 0x2f0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_OFFSET 0x2f4 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_DEFAULT 0x0 +#define GC_FUSE_PROG_EXT_XTAL_PDB_OFFSET 0x2f8 +#define GC_FUSE_PROG_EXT_XTAL_PDB_DEFAULT 0x0 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x2fc +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 +#define GC_FUSE_PROG_OBFUSCATION_EN_OFFSET 0x300 +#define GC_FUSE_PROG_OBFUSCATION_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_JITTER_CLK_EN_OFFSET 0x304 +#define GC_FUSE_PROG_JITTER_CLK_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS0_OFFSET 0x308 +#define GC_FUSE_PROG_OBS0_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS1_OFFSET 0x30c +#define GC_FUSE_PROG_OBS1_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS2_OFFSET 0x310 +#define GC_FUSE_PROG_OBS2_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS3_OFFSET 0x314 +#define GC_FUSE_PROG_OBS3_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS4_OFFSET 0x318 +#define GC_FUSE_PROG_OBS4_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS5_OFFSET 0x31c +#define GC_FUSE_PROG_OBS5_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS6_OFFSET 0x320 +#define GC_FUSE_PROG_OBS6_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS7_OFFSET 0x324 +#define GC_FUSE_PROG_OBS7_DEFAULT 0x0 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_OFFSET 0x328 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_OFFSET 0x32c +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_OFFSET 0x330 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_OFFSET 0x334 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_DEFAULT 0x0 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_OFFSET 0x338 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_OFFSET 0x33c +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_ALERT_RSP_CFG_OFFSET 0x340 +#define GC_FUSE_PROG_ALERT_RSP_CFG_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_OFFSET 0x344 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_OFFSET 0x348 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_OFFSET 0x34c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_OFFSET 0x350 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_OFFSET 0x354 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_OFFSET 0x358 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_OFFSET 0x35c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_OFFSET 0x360 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_OFFSET 0x364 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_OFFSET 0x368 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_OFFSET 0x36c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_OFFSET 0x370 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_OFFSET 0x374 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_OFFSET 0x378 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x37c +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x380 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_OFFSET 0x384 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_OFFSET 0x388 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_OFFSET 0x38c +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_OFFSET 0x390 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x394 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x398 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x39c +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_OFFSET 0x3a0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_OFFSET 0x3a4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_OFFSET 0x3a8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_OFFSET 0x3ac +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_OFFSET 0x3b0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_OFFSET 0x3b4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_OFFSET 0x3b8 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_OFFSET 0x3bc +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_OFFSET 0x3c0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_OFFSET 0x3c4 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_OFFSET 0x3c8 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_OFFSET 0x3cc +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_OFFSET 0x3d0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_OFFSET 0x3d4 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_OFFSET 0x3d8 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_OFFSET 0x3dc +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_OFFSET 0x3e0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_OFFSET 0x3e4 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_OFFSET 0x3e8 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_OFFSET 0x3ec +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_OFFSET 0x3f0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_OFFSET 0x3f4 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_OFFSET 0x3f8 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_OFFSET 0x3fc +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_OFFSET 0x400 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_OFFSET 0x404 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_OFFSET 0x408 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_OFFSET 0x40c +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_OFFSET 0x410 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_OFFSET 0x414 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_OFFSET 0x418 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x41c +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_OFFSET 0x420 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_OFFSET 0x424 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x428 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x42c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x430 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x434 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x438 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x43c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x440 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x444 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x448 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x44c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x450 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_OFFSET 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_OFFSET 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_OFFSET 0x8 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_OFFSET 0xc +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_OFFSET 0x10 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_OFFSET 0x14 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_OFFSET 0x18 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_OFFSET 0x1c +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_DEFAULT 0x7 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_OFFSET 0x20 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_OFFSET 0x24 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_OFFSET 0x28 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_OFFSET 0x2c +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_OFFSET 0x30 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_OFFSET 0x34 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_OFFSET 0x38 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_OFFSET 0x3c +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_OFFSET 0x40 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_OFFSET 0x44 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_OFFSET 0x48 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_OFFSET 0x4c +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_OFFSET 0x50 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_OFFSET 0x54 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_OFFSET 0x58 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_OFFSET 0x5c +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_OFFSET 0x60 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_OFFSET 0x64 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_OFFSET 0x68 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_OFFSET 0x6c +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_OFFSET 0x70 +#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_OFFSET 0x74 +#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_OFFSET 0x78 +#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_OFFSET 0x7c +#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_OFFSET 0x80 +#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_OFFSET 0x84 +#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_OFFSET 0x88 +#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_OFFSET 0x8c +#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_OFFSET 0x90 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_OFFSET 0x94 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_OFFSET 0x98 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_OFFSET 0x9c +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_OFFSET 0xa0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_OFFSET 0xa4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_OFFSET 0xa8 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_OFFSET 0xac +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_OFFSET 0xb0 +#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_OFFSET 0xb4 +#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_OFFSET 0xb8 +#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_OFFSET 0xbc +#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_OFFSET 0xc0 +#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_OFFSET 0xc4 +#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_OFFSET 0xc8 +#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_OFFSET 0xcc +#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_OFFSET 0xd0 +#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_OFFSET 0xd4 +#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_OFFSET 0xd8 +#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_OFFSET 0xdc +#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_OFFSET 0xe0 +#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_OFFSET 0xe4 +#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_OFFSET 0xe8 +#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_OFFSET 0xec +#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_OFFSET 0xf0 +#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_OFFSET 0xf4 +#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_OFFSET 0xf8 +#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_OFFSET 0xfc +#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_OFFSET 0x100 +#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_OFFSET 0x104 +#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_OFFSET 0x108 +#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_OFFSET 0x10c +#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_OFFSET 0x110 +#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_OFFSET 0x114 +#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_OFFSET 0x118 +#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_OFFSET 0x11c +#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_OFFSET 0x120 +#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_OFFSET 0x124 +#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_OFFSET 0x128 +#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_OFFSET 0x12c +#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_OFFSET 0x130 +#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_OFFSET 0x134 +#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_OFFSET 0x138 +#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_OFFSET 0x13c +#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_OFFSET 0x140 +#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_OFFSET 0x144 +#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_OFFSET 0x148 +#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_OFFSET 0x14c +#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_OFFSET 0x154 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_OFFSET 0x158 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_OFFSET 0x160 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_OFFSET 0x164 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_OFFSET 0x16c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_OFFSET 0x170 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_OFFSET 0x178 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_OFFSET 0x17c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_OFFSET 0x184 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_OFFSET 0x188 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_OFFSET 0x190 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_OFFSET 0x194 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_OFFSET 0x19c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_OFFSET 0x1a0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_OFFSET 0x1a8 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_OFFSET 0x1ac +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_OFFSET 0x1b0 #define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET 0xa0 +#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET 0x1b4 #define GC_GLOBALSEC_CPU0_S_PERMISSION_DEFAULT 0x55 -#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_OFFSET 0xa4 +#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_OFFSET 0x1b8 #define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0xa8 +#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0x1bc #define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DEFAULT 0x55 -#define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_OFFSET 0xac +#define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_OFFSET 0x1c0 #define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0xb0 +#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0x1c4 #define GC_GLOBALSEC_DDMA0_PERMISSION_DEFAULT 0x55 +#define GC_GLOBALSEC_SOFTWARE_LVL_DECREMENT_OFFSET 0x1c8 +#define GC_GLOBALSEC_SOFTWARE_LVL_DECREMENT_DEFAULT 0x0 +#define GC_GLOBALSEC_SOFTWARE_LVL_OFFSET 0x1cc +#define GC_GLOBALSEC_SOFTWARE_LVL_DEFAULT 0x55 #define GC_GLOBALSEC_SB_COMP_STATUS_OFFSET 0x1000 #define GC_GLOBALSEC_SB_COMP_STATUS_DEFAULT 0x0 #define GC_GLOBALSEC_SB_BL_SIG0_OFFSET 0x1004 @@ -1533,7 +1829,9 @@ #define GC_GLOBALSEC_SB_BL_SIG6_DEFAULT 0xfacecafe #define GC_GLOBALSEC_SB_BL_SIG7_OFFSET 0x1020 #define GC_GLOBALSEC_SB_BL_SIG7_DEFAULT 0xfacecafe -#define GC_GLOBALSEC_INT_ERR_FLAGS_OFFSET 0x1024 +#define GC_GLOBALSEC_SIG_UNLOCK_OFFSET 0x1024 +#define GC_GLOBALSEC_SIG_UNLOCK_DEFAULT 0x0 +#define GC_GLOBALSEC_INT_ERR_FLAGS_OFFSET 0x1028 #define GC_GLOBALSEC_INT_ERR_FLAGS_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_FW_TRIGGER_OFFSET 0x4000 #define GC_GLOBALSEC_ALERT_FW_TRIGGER_DEFAULT 0xaa @@ -1629,12 +1927,20 @@ #define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_EMPTY_DEFAULT 0x0 #define GC_GLOBALSEC_OBFS_SW_EN_OFFSET 0x40b8 #define GC_GLOBALSEC_OBFS_SW_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_OFFSET 0x40bc +#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_OFFSET 0x40bc +#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_DEFAULT 0x0 +#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_OFFSET 0x40c0 #define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_OFFSET 0x40c0 +#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_OFFSET 0x40c4 #define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_OFFSET 0x40c4 +#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_OFFSET 0x40c8 #define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DEFAULT 0x2f +#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_OFFSET 0x40d0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_DEFAULT 0x0 +#define GC_GLOBALSEC_VERSION_OFFSET 0x40d4 +#define GC_GLOBALSEC_VERSION_DEFAULT 0x26011ff3 #define GC_GPIO_DATAIN_OFFSET 0x0 #define GC_GPIO_DATAIN_DEFAULT 0x0 #define GC_GPIO_DOUT_OFFSET 0x4 @@ -2965,8 +3271,10 @@ #define GC_KEYMGR_SHA_CFG_MSGLEN_HI_DEFAULT 0x0 #define GC_KEYMGR_SHA_CFG_EN_OFFSET 0x408 #define GC_KEYMGR_SHA_CFG_EN_DEFAULT 0x1 -#define GC_KEYMGR_SHA_TRIG_OFFSET 0x40c -#define GC_KEYMGR_SHA_TRIG_DEFAULT 0x2 +#define GC_KEYMGR_SHA_CFG_WR_EN_OFFSET 0x40c +#define GC_KEYMGR_SHA_CFG_WR_EN_DEFAULT 0x1 +#define GC_KEYMGR_SHA_TRIG_OFFSET 0x410 +#define GC_KEYMGR_SHA_TRIG_DEFAULT 0x0 #define GC_KEYMGR_SHA_INPUT_FIFO_OFFSET 0x440 #define GC_KEYMGR_SHA_INPUT_FIFO_DEFAULT 0x0 #define GC_KEYMGR_SHA_STS_H0_OFFSET 0x444 @@ -3015,6 +3323,16 @@ #define GC_KEYMGR_SHA_CERT_OVERRIDE_DEFAULT 0x0 #define GC_KEYMGR_SHA_RAND_STALL_CTL_OFFSET 0x49c #define GC_KEYMGR_SHA_RAND_STALL_CTL_DEFAULT 0x7 +#define GC_KEYMGR_SHA_EXECUTE_COUNT_STATE_OFFSET 0x4a0 +#define GC_KEYMGR_SHA_EXECUTE_COUNT_STATE_DEFAULT 0x0 +#define GC_KEYMGR_SHA_EXECUTE_COUNT_MAX_OFFSET 0x4a4 +#define GC_KEYMGR_SHA_EXECUTE_COUNT_MAX_DEFAULT 0x0 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DEFAULT 0xaaaaaaaa +#define GC_KEYMGR_CERT_REVOKE_CTRL1_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DEFAULT 0xaaaaaaaa +#define GC_KEYMGR_CERT_REVOKE_CTRL2_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_DEFAULT 0xaaaa #define GC_KEYMGR_TM_PW_ATTEMPT0_OFFSET 0x2100 #define GC_KEYMGR_TM_PW_ATTEMPT0_DEFAULT 0x0 #define GC_KEYMGR_TM_PW_ATTEMPT1_OFFSET 0x2104 @@ -3051,6 +3369,8 @@ #define GC_KEYMGR_HKEY_RWR7_DEFAULT 0x0 #define GC_KEYMGR_RWR_VLD_OFFSET 0x3020 #define GC_KEYMGR_RWR_VLD_DEFAULT 0x1 +#define GC_KEYMGR_RWR_LOCK_OFFSET 0x3024 +#define GC_KEYMGR_RWR_LOCK_DEFAULT 0x1 #define GC_KEYMGR_HKEY_FWR0_OFFSET 0x3100 #define GC_KEYMGR_HKEY_FWR0_DEFAULT 0x0 #define GC_KEYMGR_HKEY_FWR1_OFFSET 0x3104 @@ -3070,7 +3390,7 @@ #define GC_KEYMGR_FWR_VLD_OFFSET 0x3120 #define GC_KEYMGR_FWR_VLD_DEFAULT 0x1 #define GC_KEYMGR_FW_MAJOR_VERSION_OFFSET 0x3124 -#define GC_KEYMGR_FW_MAJOR_VERSION_DEFAULT 0x3f +#define GC_KEYMGR_FW_MAJOR_VERSION_DEFAULT 0x0 #define GC_KEYMGR_FWR_LOCK_OFFSET 0x3128 #define GC_KEYMGR_FWR_LOCK_DEFAULT 0x1 #define GC_KEYMGR_HKEY_HWR0_OFFSET 0x3200 @@ -3093,26 +3413,6 @@ #define GC_KEYMGR_HWR_VLD_DEFAULT 0x1 #define GC_KEYMGR_HWR_LOCK_OFFSET 0x3224 #define GC_KEYMGR_HWR_LOCK_DEFAULT 0x1 -#define GC_KEYMGR_HKEY_RBC0_OFFSET 0x3280 -#define GC_KEYMGR_HKEY_RBC0_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC1_OFFSET 0x3284 -#define GC_KEYMGR_HKEY_RBC1_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC2_OFFSET 0x3288 -#define GC_KEYMGR_HKEY_RBC2_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC3_OFFSET 0x328c -#define GC_KEYMGR_HKEY_RBC3_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC4_OFFSET 0x3290 -#define GC_KEYMGR_HKEY_RBC4_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC5_OFFSET 0x3294 -#define GC_KEYMGR_HKEY_RBC5_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC6_OFFSET 0x3298 -#define GC_KEYMGR_HKEY_RBC6_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_RBC7_OFFSET 0x329c -#define GC_KEYMGR_HKEY_RBC7_DEFAULT 0x0 -#define GC_KEYMGR_RBC_VLD_OFFSET 0x32a0 -#define GC_KEYMGR_RBC_VLD_DEFAULT 0x1 -#define GC_KEYMGR_RBC_LOCK_OFFSET 0x32a4 -#define GC_KEYMGR_RBC_LOCK_DEFAULT 0x1 #define GC_KEYMGR_HKEY_FRR0_OFFSET 0x3300 #define GC_KEYMGR_HKEY_FRR0_DEFAULT 0x0 #define GC_KEYMGR_HKEY_FRR1_OFFSET 0x3304 @@ -3131,6 +3431,8 @@ #define GC_KEYMGR_HKEY_FRR7_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_OFFSET 0x3320 #define GC_KEYMGR_HKEY_ERR_FLAGS_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_DEFAULT 0x0 #define GC_MAU_EN_OFFSET 0x0 #define GC_MAU_EN_DEFAULT 0x3 #define GC_MAU_TRACECLR_OFFSET 0x4 @@ -3265,199 +3567,179 @@ #define GC_PINMUX_RESETB_SEL_DEFAULT 0x0 #define GC_PINMUX_RESETB_CTL_OFFSET 0xf4 #define GC_PINMUX_RESETB_CTL_DEFAULT 0x7 -#define GC_PINMUX_TRSTN_SEL_OFFSET 0xf8 -#define GC_PINMUX_TRSTN_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRSTN_CTL_OFFSET 0xfc -#define GC_PINMUX_TRSTN_CTL_DEFAULT 0x3 -#define GC_PINMUX_TDI_SEL_OFFSET 0x100 -#define GC_PINMUX_TDI_SEL_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_OFFSET 0x104 -#define GC_PINMUX_TDI_CTL_DEFAULT 0x3 -#define GC_PINMUX_TMS_SEL_OFFSET 0x108 -#define GC_PINMUX_TMS_SEL_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_OFFSET 0x10c -#define GC_PINMUX_TMS_CTL_DEFAULT 0x3 -#define GC_PINMUX_TCK_SEL_OFFSET 0x110 -#define GC_PINMUX_TCK_SEL_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_OFFSET 0x114 -#define GC_PINMUX_TCK_CTL_DEFAULT 0x3 -#define GC_PINMUX_TDO_SEL_OFFSET 0x118 -#define GC_PINMUX_TDO_SEL_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_OFFSET 0x11c -#define GC_PINMUX_TDO_CTL_DEFAULT 0x3 -#define GC_PINMUX_VIO0_SEL_OFFSET 0x120 +#define GC_PINMUX_VIO0_SEL_OFFSET 0xf8 #define GC_PINMUX_VIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_OFFSET 0xfc #define GC_PINMUX_VIO0_CTL_DEFAULT 0x3 -#define GC_PINMUX_VIO1_SEL_OFFSET 0x128 +#define GC_PINMUX_VIO1_SEL_OFFSET 0x100 #define GC_PINMUX_VIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_OFFSET 0x104 #define GC_PINMUX_VIO1_CTL_DEFAULT 0x3 -#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET 0x130 +#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET 0x108 #define GC_PINMUX_GPIO0_GPIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET 0x134 +#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET 0x10c #define GC_PINMUX_GPIO0_GPIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET 0x138 +#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET 0x110 #define GC_PINMUX_GPIO0_GPIO2_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET 0x13c +#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET 0x114 #define GC_PINMUX_GPIO0_GPIO3_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET 0x140 +#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET 0x118 #define GC_PINMUX_GPIO0_GPIO4_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET 0x144 +#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET 0x11c #define GC_PINMUX_GPIO0_GPIO5_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET 0x148 +#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET 0x120 #define GC_PINMUX_GPIO0_GPIO6_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET 0x14c +#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET 0x124 #define GC_PINMUX_GPIO0_GPIO7_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET 0x150 +#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET 0x128 #define GC_PINMUX_GPIO0_GPIO8_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET 0x154 +#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET 0x12c #define GC_PINMUX_GPIO0_GPIO9_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET 0x158 +#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET 0x130 #define GC_PINMUX_GPIO0_GPIO10_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET 0x15c +#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET 0x134 #define GC_PINMUX_GPIO0_GPIO11_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET 0x160 +#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET 0x138 #define GC_PINMUX_GPIO0_GPIO12_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET 0x164 +#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET 0x13c #define GC_PINMUX_GPIO0_GPIO13_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET 0x168 +#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET 0x140 #define GC_PINMUX_GPIO0_GPIO14_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET 0x16c +#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET 0x144 #define GC_PINMUX_GPIO0_GPIO15_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET 0x170 +#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET 0x148 #define GC_PINMUX_GPIO1_GPIO0_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET 0x174 +#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET 0x14c #define GC_PINMUX_GPIO1_GPIO1_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET 0x178 +#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET 0x150 #define GC_PINMUX_GPIO1_GPIO2_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET 0x17c +#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET 0x154 #define GC_PINMUX_GPIO1_GPIO3_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET 0x180 +#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET 0x158 #define GC_PINMUX_GPIO1_GPIO4_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET 0x184 +#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET 0x15c #define GC_PINMUX_GPIO1_GPIO5_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET 0x188 +#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET 0x160 #define GC_PINMUX_GPIO1_GPIO6_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET 0x18c +#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET 0x164 #define GC_PINMUX_GPIO1_GPIO7_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET 0x190 +#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET 0x168 #define GC_PINMUX_GPIO1_GPIO8_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET 0x194 +#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET 0x16c #define GC_PINMUX_GPIO1_GPIO9_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET 0x198 +#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET 0x170 #define GC_PINMUX_GPIO1_GPIO10_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET 0x19c +#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET 0x174 #define GC_PINMUX_GPIO1_GPIO11_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET 0x1a0 +#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET 0x178 #define GC_PINMUX_GPIO1_GPIO12_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET 0x1a4 +#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET 0x17c #define GC_PINMUX_GPIO1_GPIO13_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET 0x1a8 +#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET 0x180 #define GC_PINMUX_GPIO1_GPIO14_SEL_DEFAULT 0x0 -#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET 0x1ac +#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET 0x184 #define GC_PINMUX_GPIO1_GPIO15_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET 0x1b0 -#define GC_PINMUX_I2CS0_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET 0x1b4 -#define GC_PINMUX_I2CS0_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C0_SCL_SEL_OFFSET 0x1b8 +#define GC_PINMUX_I2C0_SCL_SEL_OFFSET 0x188 #define GC_PINMUX_I2C0_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C0_SDA_SEL_OFFSET 0x1bc +#define GC_PINMUX_I2C0_SDA_SEL_OFFSET 0x18c #define GC_PINMUX_I2C0_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C1_SCL_SEL_OFFSET 0x1c0 +#define GC_PINMUX_I2C1_SCL_SEL_OFFSET 0x190 #define GC_PINMUX_I2C1_SCL_SEL_DEFAULT 0x0 -#define GC_PINMUX_I2C1_SDA_SEL_OFFSET 0x1c4 +#define GC_PINMUX_I2C1_SDA_SEL_OFFSET 0x194 #define GC_PINMUX_I2C1_SDA_SEL_DEFAULT 0x0 -#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_OFFSET 0x1c8 +#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET 0x198 +#define GC_PINMUX_I2CS0_SCL_SEL_DEFAULT 0x0 +#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET 0x19c +#define GC_PINMUX_I2CS0_SDA_SEL_DEFAULT 0x0 +#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_OFFSET 0x1a0 #define GC_PINMUX_PMU_BROWNOUT_DET_SEL_DEFAULT 0x0 -#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_OFFSET 0x1cc +#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_OFFSET 0x1a4 #define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI1_SPICLK_SEL_OFFSET 0x1d0 +#define GC_PINMUX_SPI1_SPICLK_SEL_OFFSET 0x1a8 #define GC_PINMUX_SPI1_SPICLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI1_SPICSB_SEL_OFFSET 0x1d4 +#define GC_PINMUX_SPI1_SPICSB_SEL_OFFSET 0x1ac #define GC_PINMUX_SPI1_SPICSB_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI1_SPIMISO_SEL_OFFSET 0x1d8 +#define GC_PINMUX_SPI1_SPIMISO_SEL_OFFSET 0x1b0 #define GC_PINMUX_SPI1_SPIMISO_SEL_DEFAULT 0x0 -#define GC_PINMUX_SPI1_SPIMOSI_SEL_OFFSET 0x1dc +#define GC_PINMUX_SPI1_SPIMOSI_SEL_OFFSET 0x1b4 #define GC_PINMUX_SPI1_SPIMOSI_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x1e0 +#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x1b8 #define GC_PINMUX_SWDP0_TRACE2_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x1e4 +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x1bc #define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1e8 +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1c0 #define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1ec +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1c4 #define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1f0 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1c8 #define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x1f4 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x1cc #define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1f8 +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1d0 #define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x1fc +#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x1d4 #define GC_PINMUX_UART0_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x200 +#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x1d8 #define GC_PINMUX_UART0_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x204 +#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x1dc #define GC_PINMUX_UART0_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x208 +#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x1e0 #define GC_PINMUX_UART0_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x20c +#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x1e4 #define GC_PINMUX_UART1_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x210 +#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x1e8 #define GC_PINMUX_UART1_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x214 +#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x1ec #define GC_PINMUX_UART1_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x218 +#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x1f0 #define GC_PINMUX_UART1_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x21c +#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x1f4 #define GC_PINMUX_UART2_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x220 +#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x1f8 #define GC_PINMUX_UART2_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x224 +#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x1fc #define GC_PINMUX_UART2_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x228 +#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x200 #define GC_PINMUX_UART2_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x22c +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x204 #define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x230 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x208 #define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x234 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x20c #define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x238 +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x210 #define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x23c +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x214 #define GC_PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x240 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x218 #define GC_PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x244 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x21c #define GC_PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x248 +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x220 #define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x24c +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x224 #define GC_PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x250 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x228 #define GC_PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x254 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x22c #define GC_PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 -#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x258 +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230 #define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_DEFAULT 0x0 -#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x25c +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x234 #define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_OFFSET 0x23c #define GC_PINMUX_EXITEN1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_OFFSET 0x244 #define GC_PINMUX_EXITEDGE1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_OFFSET 0x24c #define GC_PINMUX_EXITINV1_DEFAULT 0x0 -#define GC_PINMUX_HOLD_OFFSET 0x278 +#define GC_PINMUX_HOLD_OFFSET 0x250 #define GC_PINMUX_HOLD_DEFAULT 0x0 #define GC_PMU_RESET_OFFSET 0x0 #define GC_PMU_RESET_DEFAULT 0x3 @@ -3484,14 +3766,14 @@ #define GC_PMU_SYSVTOR_DEFAULT 0xffffffff #define GC_PMU_NAP_EN_OFFSET 0x2c #define GC_PMU_NAP_EN_DEFAULT 0x0 -#define GC_PMU_MODEL_FPGA_OFFSET 0x30 -#define GC_PMU_MODEL_FPGA_DEFAULT 0x0 -#define GC_PMU_SW_PDB_OFFSET 0x34 +#define GC_PMU_SW_PDB_OFFSET 0x30 #define GC_PMU_SW_PDB_DEFAULT 0x0 -#define GC_PMU_SW_PDB_SECURE_OFFSET 0x38 +#define GC_PMU_SW_PDB_SECURE_OFFSET 0x34 #define GC_PMU_SW_PDB_SECURE_DEFAULT 0x0 -#define GC_PMU_VREF_OFFSET 0x3c +#define GC_PMU_VREF_OFFSET 0x38 #define GC_PMU_VREF_DEFAULT 0xfb +#define GC_PMU_XTL_OSC_BYPASS_OFFSET 0x3c +#define GC_PMU_XTL_OSC_BYPASS_DEFAULT 0x0 #define GC_PMU_BAT_LVL_OK_OFFSET 0x40 #define GC_PMU_BAT_LVL_OK_DEFAULT 0x0 #define GC_PMU_B_REG_DIG_CTRL_OFFSET 0x44 @@ -3509,13 +3791,13 @@ #define GC_PMU_MEMCLKCLR_OFFSET 0x5c #define GC_PMU_MEMCLKCLR_DEFAULT 0x7f #define GC_PMU_PERICLKSET0_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DEFAULT 0xbc1f80f7 +#define GC_PMU_PERICLKSET0_DEFAULT 0x3fcfd07b #define GC_PMU_PERICLKCLR0_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DEFAULT 0xbc1f80f7 +#define GC_PMU_PERICLKCLR0_DEFAULT 0x3fcfd07b #define GC_PMU_PERICLKSET1_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DEFAULT 0x78620 +#define GC_PMU_PERICLKSET1_DEFAULT 0x3cc4 #define GC_PMU_PERICLKCLR1_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DEFAULT 0x78620 +#define GC_PMU_PERICLKCLR1_DEFAULT 0x3cc4 #define GC_PMU_PERIGATEONSLEEPSET0_OFFSET 0x70 #define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET 0x74 @@ -3594,38 +3876,38 @@ #define GC_PMU_PWRDN_SCRATCH30_DEFAULT 0x0 #define GC_PMU_PWRDN_SCRATCH31_OFFSET 0x108 #define GC_PMU_PWRDN_SCRATCH31_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x10c +#define GC_PMU_PWRDN_SCRATCH_LOCK_OFFSET 0x10c +#define GC_PMU_PWRDN_SCRATCH_LOCK_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x110 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x114 #define GC_PMU_LONG_LIFE_SCRATCH0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x114 +#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x118 #define GC_PMU_LONG_LIFE_SCRATCH1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x118 +#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x11c #define GC_PMU_LONG_LIFE_SCRATCH2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x11c +#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x120 #define GC_PMU_LONG_LIFE_SCRATCH3_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_OFFSET 0x120 +#define GC_PMU_INT_ENABLE_OFFSET 0x124 #define GC_PMU_INT_ENABLE_DEFAULT 0x0 -#define GC_PMU_INT_STATE_OFFSET 0x124 +#define GC_PMU_INT_STATE_OFFSET 0x128 #define GC_PMU_INT_STATE_DEFAULT 0x0 -#define GC_PMU_INT_TEST_OFFSET 0x128 +#define GC_PMU_INT_TEST_OFFSET 0x12c #define GC_PMU_INT_TEST_DEFAULT 0x0 #define GC_PMU_ANTEST_TOP_CTRL_OFFSET 0x1008 #define GC_PMU_ANTEST_TOP_CTRL_DEFAULT 0x3 -#define GC_PMU_ANTEST1_REGDIG_OFFSET 0x1010 -#define GC_PMU_ANTEST1_REGDIG_DEFAULT 0x0 +#define GC_PMU_ANTEST_REGDIG_OFFSET 0x1010 +#define GC_PMU_ANTEST_REGDIG_DEFAULT 0x0 #define GC_PMU_ANTEST_FUSE_OFFSET 0x1018 #define GC_PMU_ANTEST_FUSE_DEFAULT 0x0 -#define GC_PMU_ANTEST_TRNG_OFFSET 0x101c -#define GC_PMU_ANTEST_TRNG_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_OFFSET 0x1020 -#define GC_PMU_ANTEST_TEMP_DEFAULT 0x0 +#define GC_PMU_ANTEST_XO_OFFSET 0x101c +#define GC_PMU_ANTEST_XO_DEFAULT 0x0 #define GC_PMU_TESTBUS_CTRL_OFFSET 0x2000 #define GC_PMU_TESTBUS_CTRL_DEFAULT 0x0 #define GC_PMU_CHIP_ID_OFFSET 0x1fff8 #define GC_PMU_CHIP_ID_DEFAULT 0x1485694d #define GC_PMU_VERSION_OFFSET 0x1fffc -#define GC_PMU_VERSION_DEFAULT 0x21010fc9 +#define GC_PMU_VERSION_DEFAULT 0x24011f6d #define GC_RBOX_INT_ENABLE_OFFSET 0x0 #define GC_RBOX_INT_ENABLE_DEFAULT 0x0 #define GC_RBOX_INT_STATE_OFFSET 0x4 @@ -3634,88 +3916,104 @@ #define GC_RBOX_INT_TEST_DEFAULT 0x0 #define GC_RBOX_EC_WP_L_OFFSET 0xc #define GC_RBOX_EC_WP_L_DEFAULT 0x0 -#define GC_RBOX_ASSERT_EC_RST_L_OFFSET 0x10 -#define GC_RBOX_ASSERT_EC_RST_L_DEFAULT 0x0 -#define GC_RBOX_CLK_DIV_LIMIT_OFFSET 0x14 -#define GC_RBOX_CLK_DIV_LIMIT_DEFAULT 0x0 -#define GC_RBOX_OVERRIDE_OUTPUT_OFFSET 0x18 -#define GC_RBOX_OVERRIDE_OUTPUT_DEFAULT 0x0 -#define GC_RBOX_CHECK_IO_OFFSET 0x1c -#define GC_RBOX_CHECK_IO_DEFAULT 0x0 -#define GC_RBOX_STATUS_OFFSET 0x20 +#define GC_RBOX_ASSERT_EC_RST_OFFSET 0x10 +#define GC_RBOX_ASSERT_EC_RST_DEFAULT 0x0 +#define GC_RBOX_OVERRIDE_OUTPUT_OFFSET 0x14 +#define GC_RBOX_OVERRIDE_OUTPUT_DEFAULT 0x2e80 +#define GC_RBOX_CHECK_INPUT_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_DEFAULT 0x0 +#define GC_RBOX_STATUS_OFFSET 0x28 #define GC_RBOX_STATUS_DEFAULT 0x0 -#define GC_RBOX_FUSE_CTRL_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_OFFSET 0x2c #define GC_RBOX_FUSE_CTRL_DEFAULT 0x0 -#define GC_RBOX_DEBUG_DEBOUNCE_OFFSET 0x28 -#define GC_RBOX_DEBUG_DEBOUNCE_DEFAULT 0x100 -#define GC_RBOX_DEBUG_KEY_COMBO0_OFFSET 0x2c -#define GC_RBOX_DEBUG_KEY_COMBO0_DEFAULT 0x63c0 -#define GC_RBOX_DEBUG_KEY_COMBO1_OFFSET 0x30 -#define GC_RBOX_DEBUG_KEY_COMBO1_DEFAULT 0x6300 -#define GC_RBOX_DEBUG_KEY_COMBO2_OFFSET 0x34 -#define GC_RBOX_DEBUG_KEY_COMBO2_DEFAULT 0x6300 -#define GC_RBOX_DEBUG_BLOCK_KEY_OFFSET 0x38 -#define GC_RBOX_DEBUG_BLOCK_KEY_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_OFFSET 0x3c +#define GC_RBOX_DEBUG_DEBOUNCE_OFFSET 0x30 +#define GC_RBOX_DEBUG_DEBOUNCE_DEFAULT 0x70000 +#define GC_RBOX_DEBUG_KEY_COMBO0_OFFSET 0x34 +#define GC_RBOX_DEBUG_KEY_COMBO0_DEFAULT 0xc0 +#define GC_RBOX_DEBUG_KEY_COMBO1_OFFSET 0x38 +#define GC_RBOX_DEBUG_KEY_COMBO1_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO2_OFFSET 0x3c +#define GC_RBOX_DEBUG_KEY_COMBO2_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_DEFAULT 0x1 -#define GC_RBOX_DEBUG_TERM_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_DEFAULT 0x0 -#define GC_RBOX_DEBUG_DRIVE_OFFSET 0x44 -#define GC_RBOX_DEBUG_DRIVE_DEFAULT 0x3f -#define GC_RBOX_DEBUG_CLK10HZ_COUNT_OFFSET 0x48 +#define GC_RBOX_DEBUG_DRIVE_OFFSET 0x4c +#define GC_RBOX_DEBUG_DRIVE_DEFAULT 0x17f +#define GC_RBOX_DEBUG_CLK10HZ_COUNT_OFFSET 0x50 #define GC_RBOX_DEBUG_CLK10HZ_COUNT_DEFAULT 0x63ff -#define GC_RBOX_DEBUG_SHORT_DELAY_COUNT_OFFSET 0x4c +#define GC_RBOX_DEBUG_SHORT_DELAY_COUNT_OFFSET 0x54 #define GC_RBOX_DEBUG_SHORT_DELAY_COUNT_DEFAULT 0x4ff -#define GC_RBOX_DEBUG_LONG_DELAY_COUNT_OFFSET 0x50 +#define GC_RBOX_DEBUG_LONG_DELAY_COUNT_OFFSET 0x58 #define GC_RBOX_DEBUG_LONG_DELAY_COUNT_DEFAULT 0x31 -#define GC_RBOX_CHECK_STATE_ENABLE_OFFSET 0x54 +#define GC_RBOX_CHECK_STATE_ENABLE_OFFSET 0x5c #define GC_RBOX_CHECK_STATE_ENABLE_DEFAULT 0x0 -#define GC_RBOX_CHECK_STATE0_OFFSET 0x58 +#define GC_RBOX_CHECK_STATE0_OFFSET 0x60 #define GC_RBOX_CHECK_STATE0_DEFAULT 0x0 -#define GC_RBOX_CHECK_STATE1_OFFSET 0x5c +#define GC_RBOX_CHECK_STATE1_OFFSET 0x64 #define GC_RBOX_CHECK_STATE1_DEFAULT 0x0 -#define GC_RBOX_CHECK_STATE2_OFFSET 0x60 +#define GC_RBOX_CHECK_STATE2_OFFSET 0x68 #define GC_RBOX_CHECK_STATE2_DEFAULT 0x0 -#define GC_RBOX_CONFIG_DEBOUNCE_OFFSET 0x64 +#define GC_RBOX_CONFIG_DEBOUNCE_OFFSET 0x6c #define GC_RBOX_CONFIG_DEBOUNCE_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO0_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO0_OFFSET 0x70 #define GC_RBOX_CONFIG_KEY_COMBO0_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO1_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO1_OFFSET 0x74 #define GC_RBOX_CONFIG_KEY_COMBO1_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO2_OFFSET 0x70 +#define GC_RBOX_CONFIG_KEY_COMBO2_OFFSET 0x78 #define GC_RBOX_CONFIG_KEY_COMBO2_DEFAULT 0x0 -#define GC_RBOX_CONFIG_BLOCK_KEY_OFFSET 0x74 -#define GC_RBOX_CONFIG_BLOCK_KEY_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_OFFSET 0x78 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_DEFAULT 0x1 -#define GC_RBOX_CONFIG_TERM_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_DEFAULT 0x0 -#define GC_RBOX_CONFIG_DRIVE_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_OFFSET 0x88 #define GC_RBOX_CONFIG_DRIVE_DEFAULT 0x0 -#define GC_RBOX_CONFIG_CLK10HZ_COUNT_OFFSET 0x84 +#define GC_RBOX_CONFIG_CLK10HZ_COUNT_OFFSET 0x8c #define GC_RBOX_CONFIG_CLK10HZ_COUNT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_SHORT_DELAY_COUNT_OFFSET 0x88 +#define GC_RBOX_CONFIG_SHORT_DELAY_COUNT_OFFSET 0x90 #define GC_RBOX_CONFIG_SHORT_DELAY_COUNT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_LONG_DELAY_COUNT_OFFSET 0x8c +#define GC_RBOX_CONFIG_LONG_DELAY_COUNT_OFFSET 0x94 #define GC_RBOX_CONFIG_LONG_DELAY_COUNT_DEFAULT 0x0 -#define GC_RBOX_VERSION_OFFSET 0x90 -#define GC_RBOX_VERSION_DEFAULT 0x2a011174 +#define GC_RBOX_WAKEUP_OFFSET 0x98 +#define GC_RBOX_WAKEUP_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_DEFAULT 0x0 +#define GC_RBOX_VERSION_OFFSET 0xa0 +#define GC_RBOX_VERSION_DEFAULT 0x36011ae4 #define GC_RDD_VERSION_OFFSET 0x0 -#define GC_RDD_VERSION_DEFAULT 0x500f210 +#define GC_RDD_VERSION_DEFAULT 0x24011f09 #define GC_RDD_INT_ENABLE_OFFSET 0x4 #define GC_RDD_INT_ENABLE_DEFAULT 0x0 #define GC_RDD_INT_STATE_OFFSET 0x8 #define GC_RDD_INT_STATE_DEFAULT 0x0 #define GC_RDD_INT_TEST_OFFSET 0xc #define GC_RDD_INT_TEST_DEFAULT 0x0 -#define GC_RDD_MAX_WAIT_TIME_COUNTER_OFFSET 0x10 +#define GC_RDD_POWER_DOWN_B_OFFSET 0x10 +#define GC_RDD_POWER_DOWN_B_DEFAULT 0x0 +#define GC_RDD_ANTEST_OFFSET 0x14 +#define GC_RDD_ANTEST_DEFAULT 0x0 +#define GC_RDD_MAX_WAIT_TIME_COUNTER_OFFSET 0x18 #define GC_RDD_MAX_WAIT_TIME_COUNTER_DEFAULT 0xc80 -#define GC_RDD_CUR_WAIT_TIME_COUNTER_OFFSET 0x14 +#define GC_RDD_CUR_WAIT_TIME_COUNTER_OFFSET 0x1c #define GC_RDD_CUR_WAIT_TIME_COUNTER_DEFAULT 0x0 -#define GC_RDD_THRESHOLD_COMPARATOR_OFFSET 0x18 -#define GC_RDD_THRESHOLD_COMPARATOR_DEFAULT 0x0 -#define GC_RDD_CUR_STABLE_STATE_OFFSET 0x1c -#define GC_RDD_CUR_STABLE_STATE_DEFAULT 0x4 +#define GC_RDD_REF_ADJ_OFFSET 0x20 +#define GC_RDD_REF_ADJ_DEFAULT 0x15 +#define GC_RDD_INPUT_PIN_VALUES_OFFSET 0x24 +#define GC_RDD_INPUT_PIN_VALUES_DEFAULT 0x18 +#define GC_RDD_PROG_DEBUG_STATE_MAP_OFFSET 0x28 +#define GC_RDD_PROG_DEBUG_STATE_MAP_DEFAULT 0x420 +#define GC_RDD_CUR_STABLE_STATE_OFFSET 0x2c +#define GC_RDD_CUR_STABLE_STATE_DEFAULT 0x2 #define GC_RTC_CTRL_OFFSET 0x0 #define GC_RTC_CTRL_DEFAULT 0x0 #define GC_RTC_PINMUX_EN_OFFSET 0x4 @@ -3800,11 +4098,11 @@ #define GC_SPS_ICTRL_OFFSET 0x64 #define GC_SPS_ICTRL_DEFAULT 0x0 #define GC_SPS_EEPROM_CTRL_OFFSET 0x400 -#define GC_SPS_EEPROM_CTRL_DEFAULT 0x80 +#define GC_SPS_EEPROM_CTRL_DEFAULT 0x480 #define GC_SPS_MAILBOX_RD_OPCODE_OFFSET 0x404 #define GC_SPS_MAILBOX_RD_OPCODE_DEFAULT 0x0 #define GC_SPS_FAST_DUAL_RD_OPCODE_OFFSET 0x408 -#define GC_SPS_FAST_DUAL_RD_OPCODE_DEFAULT 0x0 +#define GC_SPS_FAST_DUAL_RD_OPCODE_DEFAULT 0x3b #define GC_SPS_BUSY_OPCODE0_OFFSET 0x40c #define GC_SPS_BUSY_OPCODE0_DEFAULT 0x0 #define GC_SPS_BUSY_OPCODE1_OFFSET 0x410 @@ -4009,17 +4307,17 @@ #define GC_SWDP_HEADER_MD5SUM_OFFSET 0x28 #define GC_SWDP_HEADER_MD5SUM_DEFAULT 0x0 #define GC_SWDP_P4_LAST_SYNC_OFFSET 0x2c -#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x11205 +#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x12019 #define GC_SWDP_BUILD_DATE_OFFSET 0x30 -#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337a24 +#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337a8d #define GC_SWDP_BUILD_TIME_OFFSET 0x34 -#define GC_SWDP_BUILD_TIME_DEFAULT 0xa110 +#define GC_SWDP_BUILD_TIME_DEFAULT 0x54d3 #define GC_SWDP_A1_DIO8_OFFSET 0x38 #define GC_SWDP_A1_DIO8_DEFAULT 0x0 #define GC_SWDP_A1_CHANNEL_SEL_OFFSET 0x3c #define GC_SWDP_A1_CHANNEL_SEL_DEFAULT 0x0 #define GC_TEMP_VERSION_OFFSET 0x0 -#define GC_TEMP_VERSION_DEFAULT 0x5010a2c +#define GC_TEMP_VERSION_DEFAULT 0x8011f6d #define GC_TEMP_ADC_INT_ENABLE_OFFSET 0x4 #define GC_TEMP_ADC_INT_ENABLE_DEFAULT 0x0 #define GC_TEMP_ADC_INT_STATE_OFFSET 0x8 @@ -4060,17 +4358,19 @@ #define GC_TEMP_METRIC_DEFAULT 0x0 #define GC_TEMP_SAMPLE_CTR_STATE_OFFSET 0x50 #define GC_TEMP_SAMPLE_CTR_STATE_DEFAULT 0x0 -#define GC_TEMP_FPGA_MODEL_TEMP_OFFSET 0x54 +#define GC_TEMP_ANTEST_EN_OFFSET 0x54 +#define GC_TEMP_ANTEST_EN_DEFAULT 0x0 +#define GC_TEMP_FPGA_MODEL_TEMP_OFFSET 0x58 #define GC_TEMP_FPGA_MODEL_TEMP_DEFAULT 0x8000 -#define GC_TEMP_FPGA_MODEL_DRIFT_PERIOD_OFFSET 0x58 +#define GC_TEMP_FPGA_MODEL_DRIFT_PERIOD_OFFSET 0x5c #define GC_TEMP_FPGA_MODEL_DRIFT_PERIOD_DEFAULT 0x100 -#define GC_TEMP_FPGA_MODEL_DRIFT_AMOUNT_OFFSET 0x5c +#define GC_TEMP_FPGA_MODEL_DRIFT_AMOUNT_OFFSET 0x60 #define GC_TEMP_FPGA_MODEL_DRIFT_AMOUNT_DEFAULT 0x0 -#define GC_TEMP_FPGA_MODEL_TEMP_MAX_OFFSET 0x60 +#define GC_TEMP_FPGA_MODEL_TEMP_MAX_OFFSET 0x64 #define GC_TEMP_FPGA_MODEL_TEMP_MAX_DEFAULT 0xc000 -#define GC_TEMP_FPGA_MODEL_TEMP_MIN_OFFSET 0x64 +#define GC_TEMP_FPGA_MODEL_TEMP_MIN_OFFSET 0x68 #define GC_TEMP_FPGA_MODEL_TEMP_MIN_DEFAULT 0x4000 -#define GC_TEMP_FPGA_MODEL_STAT_CALLS_OFFSET 0x68 +#define GC_TEMP_FPGA_MODEL_STAT_CALLS_OFFSET 0x6c #define GC_TEMP_FPGA_MODEL_STAT_CALLS_DEFAULT 0x0 #define GC_TIMEHS_TIMER1LOAD_OFFSET 0x0 #define GC_TIMEHS_TIMER1LOAD_DEFAULT 0x0 @@ -4241,19 +4541,19 @@ #define GC_TIMEUS_CUR_MINOR_CNTR3_OFFSET 0x418 #define GC_TIMEUS_CUR_MINOR_CNTR3_DEFAULT 0x0 #define GC_TRNG_VERSION_OFFSET 0x0 -#define GC_TRNG_VERSION_DEFAULT 0x16010f59 +#define GC_TRNG_VERSION_DEFAULT 0x24011f6d #define GC_TRNG_INT_ENABLE_OFFSET 0x4 #define GC_TRNG_INT_ENABLE_DEFAULT 0x0 #define GC_TRNG_INT_STATE_OFFSET 0x8 #define GC_TRNG_INT_STATE_DEFAULT 0x0 #define GC_TRNG_INT_TEST_OFFSET 0xc #define GC_TRNG_INT_TEST_DEFAULT 0x0 -#define GC_TRNG_POST_PROCESSING_CTRL_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_DEFAULT 0x3f -#define GC_TRNG_GO_EVENT_OFFSET 0x14 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_OFFSET 0x10 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_DEFAULT 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_OFFSET 0x14 +#define GC_TRNG_POST_PROCESSING_CTRL_DEFAULT 0xf +#define GC_TRNG_GO_EVENT_OFFSET 0x18 #define GC_TRNG_GO_EVENT_DEFAULT 0x0 -#define GC_TRNG_RO_CALIBRATION_MODE_OFFSET 0x18 -#define GC_TRNG_RO_CALIBRATION_MODE_DEFAULT 0x0 #define GC_TRNG_TIMEOUT_COUNTER_OFFSET 0x1c #define GC_TRNG_TIMEOUT_COUNTER_DEFAULT 0x7d0 #define GC_TRNG_TIMEOUT_MAX_TRY_NUM_OFFSET 0x20 @@ -4277,32 +4577,42 @@ #define GC_TRNG_MIN_VALUE_OFFSET 0x44 #define GC_TRNG_MIN_VALUE_DEFAULT 0x0 #define GC_TRNG_LDO_CTRL_OFFSET 0x48 -#define GC_TRNG_LDO_CTRL_DEFAULT 0xb -#define GC_TRNG_DIV_EN_OFFSET 0x4c -#define GC_TRNG_DIV_EN_DEFAULT 0x0 -#define GC_TRNG_ONE_SHOT_MODE_OFFSET 0x50 +#define GC_TRNG_LDO_CTRL_DEFAULT 0x9 +#define GC_TRNG_POWER_DOWN_B_OFFSET 0x4c +#define GC_TRNG_POWER_DOWN_B_DEFAULT 0x0 +#define GC_TRNG_ANTEST_OFFSET 0x50 +#define GC_TRNG_ANTEST_DEFAULT 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DEFAULT 0xb +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OFFSET 0x58 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_DEFAULT 0x0 +#define GC_TRNG_ANALOG_TEST_OFFSET 0x5c +#define GC_TRNG_ANALOG_TEST_DEFAULT 0x0 +#define GC_TRNG_ANALOG_CTRL_OFFSET 0x60 +#define GC_TRNG_ANALOG_CTRL_DEFAULT 0x0 +#define GC_TRNG_ONE_SHOT_MODE_OFFSET 0x64 #define GC_TRNG_ONE_SHOT_MODE_DEFAULT 0x0 -#define GC_TRNG_ONE_SHOT_REG_OFFSET 0x54 +#define GC_TRNG_ONE_SHOT_REG_OFFSET 0x68 #define GC_TRNG_ONE_SHOT_REG_DEFAULT 0x0 -#define GC_TRNG_READ_DATA_OFFSET 0x58 +#define GC_TRNG_READ_DATA_OFFSET 0x70 #define GC_TRNG_READ_DATA_DEFAULT 0x0 -#define GC_TRNG_FREQUENCY_CALLS_OFFSET 0x5c +#define GC_TRNG_FREQUENCY_CALLS_OFFSET 0x74 #define GC_TRNG_FREQUENCY_CALLS_DEFAULT 0x0 -#define GC_TRNG_CUR_NUM_ONES_OFFSET 0x60 +#define GC_TRNG_CUR_NUM_ONES_OFFSET 0x78 #define GC_TRNG_CUR_NUM_ONES_DEFAULT 0x0 -#define GC_TRNG_EMPTY_OFFSET 0x64 -#define GC_TRNG_EMPTY_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_MEAN_OFFSET 0x68 +#define GC_TRNG_EMPTY_OFFSET 0x7c +#define GC_TRNG_EMPTY_DEFAULT 0x1 +#define GC_TRNG_FPGA_MODEL_MEAN_OFFSET 0x80 #define GC_TRNG_FPGA_MODEL_MEAN_DEFAULT 0x400 -#define GC_TRNG_FPGA_MODEL_DIST_MASK_OFFSET 0x6c +#define GC_TRNG_FPGA_MODEL_DIST_MASK_OFFSET 0x84 #define GC_TRNG_FPGA_MODEL_DIST_MASK_DEFAULT 0x3ff -#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_OFFSET 0x70 +#define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_OFFSET 0x88 #define GC_TRNG_FPGA_MODEL_PPM_TIMEOUT_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_CALLS_OFFSET 0x74 +#define GC_TRNG_FPGA_MODEL_STAT_CALLS_OFFSET 0x8c #define GC_TRNG_FPGA_MODEL_STAT_CALLS_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_OFFSET 0x78 +#define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_OFFSET 0x90 #define GC_TRNG_FPGA_MODEL_STAT_TIMEOUTS_DEFAULT 0x0 -#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_OFFSET 0x7c +#define GC_TRNG_FPGA_MODEL_STAT_ABORTS_OFFSET 0x94 #define GC_TRNG_FPGA_MODEL_STAT_ABORTS_DEFAULT 0x0 #define GC_UART_RDATA_OFFSET 0x0 #define GC_UART_RDATA_DEFAULT 0x0 @@ -4780,13 +5090,15 @@ #define GC_USB_DOEPDMAB15_DEFAULT 0x0 #define GC_USB_DFIFO_OFFSET 0x20000 #define GC_VOLT_VERSION_OFFSET 0x0 -#define GC_VOLT_VERSION_DEFAULT 0x2010ae0 +#define GC_VOLT_VERSION_DEFAULT 0x4011f6d #define GC_VOLT_ANALOG_CONTROL_OFFSET 0x4 #define GC_VOLT_ANALOG_CONTROL_DEFAULT 0xb916 #define GC_VOLT_CONFIG_OFFSET 0x8 #define GC_VOLT_CONFIG_DEFAULT 0x0 -#define GC_VOLT_ERRS_CTR_STATE_OFFSET 0xc -#define GC_VOLT_ERRS_CTR_STATE_DEFAULT 0x0 +#define GC_VOLT_GLITCH_DET_CTR_STATE_OFFSET 0xc +#define GC_VOLT_GLITCH_DET_CTR_STATE_DEFAULT 0x0 +#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_OFFSET 0x10 +#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_DEFAULT 0x0 #define GC_WATCHDOG_WDOGLOAD_OFFSET 0x0 #define GC_WATCHDOG_WDOGLOAD_DEFAULT 0xffffffff #define GC_WATCHDOG_WDOGVALUE_OFFSET 0x4 @@ -4830,271 +5142,273 @@ #define GC_WATCHDOG_WDOGPCELLID3_OFFSET 0xffc #define GC_WATCHDOG_WDOGPCELLID3_DEFAULT 0xb1 #define GC_XO_VERSION_OFFSET 0x0 -#define GC_XO_VERSION_DEFAULT 0x14010370 -#define GC_XO_CLK_JTR_CTRL_OFFSET 0x4 +#define GC_XO_VERSION_DEFAULT 0x15011e43 +#define GC_XO_CFG_WR_EN_OFFSET 0x4 +#define GC_XO_CFG_WR_EN_DEFAULT 0x1 +#define GC_XO_CLK_JTR_CTRL_OFFSET 0x8 #define GC_XO_CLK_JTR_CTRL_DEFAULT 0x3 -#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET 0x8 +#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET 0xc #define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET 0xc +#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET 0x10 #define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_OFFSET 0x10 +#define GC_XO_CLK_JTR_CURRENT_OFFSET 0x14 #define GC_XO_CLK_JTR_CURRENT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET 0x14 +#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET 0x18 #define GC_XO_CLK_JTR_SYNC_CONTENTS_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET 0x1c #define GC_XO_CLK_JTR_TRIM_CTRL_DEFAULT 0x1e -#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET 0x1c +#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET 0x20 #define GC_XO_CLK_JTR_JITTERY_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x20 +#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x24 #define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x24 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x28 #define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_DEFAULT 0xff -#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x28 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x2c #define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET 0x2c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET 0x30 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET 0x30 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET 0x34 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET 0x34 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET 0x38 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET 0x38 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET 0x3c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET 0x3c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET 0x40 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET 0x40 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET 0x44 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET 0x44 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET 0x48 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET 0x48 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET 0x4c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET 0x4c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET 0x50 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET 0x50 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET 0x54 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x54 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x58 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x58 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x5c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x5c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x60 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x60 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x64 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x64 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x68 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x68 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x6c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET 0x70 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET 0x74 +#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET 0x78 #define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET 0x78 +#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET 0x7c #define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET 0x7c +#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET 0x80 #define GC_XO_CLK_JTR_FAST_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET 0x84 #define GC_XO_CLK_JTR_FAST_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET 0x88 #define GC_XO_CLK_JTR_FAST_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET 0x8c #define GC_XO_CLK_JTR_FAST_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET 0x90 #define GC_XO_CLK_JTR_FAST_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET 0x94 #define GC_XO_CLK_JTR_FAST_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET 0x98 #define GC_XO_CLK_JTR_FAST_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET 0x9c #define GC_XO_CLK_JTR_FAST_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET 0xa0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET 0xc0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET 0xc0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET 0xc4 #define GC_XO_CLK_JTR_SLOW_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET 0xc8 #define GC_XO_CLK_JTR_SLOW_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET 0xcc #define GC_XO_CLK_JTR_SLOW_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET 0xd0 #define GC_XO_CLK_JTR_SLOW_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET 0xd4 #define GC_XO_CLK_JTR_SLOW_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET 0xd8 #define GC_XO_CLK_JTR_SLOW_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET 0xdc #define GC_XO_CLK_JTR_SLOW_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET 0xe0 #define GC_XO_CLK_JTR_SLOW_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET 0xe4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET 0x104 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET 0x104 +#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET 0x108 #define GC_XO_CLK_JTR_ENABLE_SW_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET 0x108 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET 0x10c #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CTRL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CTRL_OFFSET 0x110 #define GC_XO_CLK_TIMER_CTRL_DEFAULT 0x3 -#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x110 +#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x114 #define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET 0x114 +#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET 0x118 #define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_OFFSET 0x118 +#define GC_XO_CLK_TIMER_CURRENT_OFFSET 0x11c #define GC_XO_CLK_TIMER_CURRENT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET 0x11c +#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET 0x120 #define GC_XO_CLK_TIMER_SYNC_CONTENTS_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET 0x124 #define GC_XO_CLK_TIMER_TRIM_CTRL_DEFAULT 0x1e -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x12c +#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x130 #define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x130 +#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x134 #define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET 0x134 +#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET 0x138 #define GC_XO_CLK_TIMER_FAST_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET 0x13c #define GC_XO_CLK_TIMER_FAST_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET 0x140 #define GC_XO_CLK_TIMER_FAST_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET 0x144 #define GC_XO_CLK_TIMER_FAST_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET 0x148 #define GC_XO_CLK_TIMER_FAST_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET 0x14c #define GC_XO_CLK_TIMER_FAST_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET 0x150 #define GC_XO_CLK_TIMER_FAST_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET 0x154 #define GC_XO_CLK_TIMER_FAST_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET 0x158 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET 0x178 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET 0x178 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET 0x17c #define GC_XO_CLK_TIMER_SLOW_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET 0x180 #define GC_XO_CLK_TIMER_SLOW_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET 0x184 #define GC_XO_CLK_TIMER_SLOW_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET 0x188 #define GC_XO_CLK_TIMER_SLOW_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET 0x18c #define GC_XO_CLK_TIMER_SLOW_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET 0x190 #define GC_XO_CLK_TIMER_SLOW_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET 0x194 #define GC_XO_CLK_TIMER_SLOW_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET 0x198 #define GC_XO_CLK_TIMER_SLOW_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET 0x19c #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET 0x1bc +#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET 0x1c0 #define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET 0x1c4 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_OFFSET 0x1c8 #define GC_XO_OSC_XTL_FREQ2X_DEFAULT 0x6 -#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_STAT_DEFAULT 0x6 -#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x1cc +#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x1d0 #define GC_XO_OSC_XTL_TRIMD_DEFAULT 0x40 -#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x1d0 +#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x1d4 #define GC_XO_OSC_XTL_TRIMG_DEFAULT 0x40 -#define GC_XO_OSC_XTL_CTRL_OFFSET 0x1d4 +#define GC_XO_OSC_XTL_CTRL_OFFSET 0x1d8 #define GC_XO_OSC_XTL_CTRL_DEFAULT 0x0 -#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x1d8 +#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x1dc #define GC_XO_OSC_XTL_RC_FLTR_DEFAULT 0x15 -#define GC_XO_OSC_XTL_OVRD_OFFSET 0x1dc +#define GC_XO_OSC_XTL_OVRD_OFFSET 0x1e0 #define GC_XO_OSC_XTL_OVRD_DEFAULT 0x17 -#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x1e0 +#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x1e4 #define GC_XO_OSC_XTL_OVRD_HOLDB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_TRIM_OFFSET 0x1e4 +#define GC_XO_OSC_XTL_TRIM_OFFSET 0x1e8 #define GC_XO_OSC_XTL_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x1ec #define GC_XO_OSC_XTL_TRIM_STAT_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x1ec +#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x1f0 #define GC_XO_OSC_XTL_FSM_EN_DEFAULT 0x0 #define GC_XO_OSC_XTL_FSM_EN_KEY 0x60221413 -#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET 0x1f0 +#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_RESETB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_DEFAULT 0xd7488 -#define GC_XO_OSC_SETHOLD_OFFSET 0x1fc +#define GC_XO_OSC_SETHOLD_OFFSET 0x200 #define GC_XO_OSC_SETHOLD_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_OFFSET 0x200 +#define GC_XO_OSC_CLRHOLD_OFFSET 0x204 #define GC_XO_OSC_CLRHOLD_DEFAULT 0x0 -#define GC_XO_OSC_TEST_OFFSET 0x204 +#define GC_XO_OSC_TEST_OFFSET 0x208 #define GC_XO_OSC_TEST_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_DEFAULT 0x0 #define GC_M3_ITM_STIM0_OFFSET 0x0 #define GC_M3_ITM_STIM0_DEFAULT 0x0 @@ -5160,24 +5474,50 @@ #define GC_M3_ITM_STIM30_DEFAULT 0x0 #define GC_M3_ITM_STIM31_OFFSET 0x7c #define GC_M3_ITM_STIM31_DEFAULT 0x0 +#define GC_M3_ITM_STIM32_OFFSET 0x80 +#define GC_M3_ITM_STIM32_DEFAULT 0x0 #define GC_M3_ITM_TER_OFFSET 0xe00 #define GC_M3_ITM_TER_DEFAULT 0x0 #define GC_M3_ITM_TPR_OFFSET 0xe40 #define GC_M3_ITM_TPR_DEFAULT 0x0 #define GC_M3_ITM_TCR_OFFSET 0xe80 #define GC_M3_ITM_TCR_DEFAULT 0x0 -#define GC_M3_ITM_INTRREG_OFFSET 0xef0 -#define GC_M3_ITM_INTRREG_DEFAULT 0x0 #define GC_M3_ITM_INTWREG_OFFSET 0xef8 #define GC_M3_ITM_INTWREG_DEFAULT 0x0 +#define GC_M3_ITM_INTRREG_OFFSET 0xefc +#define GC_M3_ITM_INTRREG_DEFAULT 0x0 #define GC_M3_ITM_INTMREG_OFFSET 0xf00 #define GC_M3_ITM_INTMREG_DEFAULT 0x0 #define GC_M3_ITM_LOCKCREG_OFFSET 0xfb0 #define GC_M3_ITM_LOCKCREG_DEFAULT 0x0 #define GC_M3_ITM_LOCKSREG_OFFSET 0xfb4 #define GC_M3_ITM_LOCKSREG_DEFAULT 0x0 +#define GC_M3_FP_PID4_OFFSET 0xfd0 +#define GC_M3_FP_PID4_DEFAULT 0x4 +#define GC_M3_FP_PID5_OFFSET 0xfd4 +#define GC_M3_FP_PID5_DEFAULT 0x0 +#define GC_M3_FP_PID6_OFFSET 0xfd8 +#define GC_M3_FP_PID6_DEFAULT 0x0 +#define GC_M3_FP_PID7_OFFSET 0xfdc +#define GC_M3_FP_PID7_DEFAULT 0x0 +#define GC_M3_FP_PID0_OFFSET 0xfe0 +#define GC_M3_FP_PID0_DEFAULT 0x3 +#define GC_M3_FP_PID1_OFFSET 0xfe4 +#define GC_M3_FP_PID1_DEFAULT 0xb0 +#define GC_M3_FP_PID2_OFFSET 0xfe8 +#define GC_M3_FP_PID2_DEFAULT 0xb +#define GC_M3_FP_PID3_OFFSET 0xfec +#define GC_M3_FP_PID3_DEFAULT 0x0 +#define GC_M3_FP_CID0_OFFSET 0xff0 +#define GC_M3_FP_CID0_DEFAULT 0xd +#define GC_M3_FP_CID1_OFFSET 0xff4 +#define GC_M3_FP_CID1_DEFAULT 0xe0 +#define GC_M3_FP_CID2_OFFSET 0xff8 +#define GC_M3_FP_CID2_DEFAULT 0x5 +#define GC_M3_FP_CID3_OFFSET 0xffc +#define GC_M3_FP_CID3_DEFAULT 0xb1 #define GC_M3_DWT_CTRL_OFFSET 0x1000 -#define GC_M3_DWT_CTRL_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_DEFAULT 0x40000000 #define GC_M3_DWT_CYCCNT_OFFSET 0x1004 #define GC_M3_DWT_CYCCNT_DEFAULT 0x0 #define GC_M3_DWT_CPICNT_OFFSET 0x1008 @@ -5342,108 +5682,6 @@ #define GC_M3_NVIC_IPR6_DEFAULT 0x0 #define GC_M3_NVIC_IPR7_OFFSET 0xe41c #define GC_M3_NVIC_IPR7_DEFAULT 0x0 -#define GC_M3_NVIC_IPR8_OFFSET 0xe420 -#define GC_M3_NVIC_IPR8_DEFAULT 0x0 -#define GC_M3_NVIC_IPR9_OFFSET 0xe424 -#define GC_M3_NVIC_IPR9_DEFAULT 0x0 -#define GC_M3_NVIC_IPR10_OFFSET 0xe428 -#define GC_M3_NVIC_IPR10_DEFAULT 0x0 -#define GC_M3_NVIC_IPR11_OFFSET 0xe42c -#define GC_M3_NVIC_IPR11_DEFAULT 0x0 -#define GC_M3_NVIC_IPR12_OFFSET 0xe430 -#define GC_M3_NVIC_IPR12_DEFAULT 0x0 -#define GC_M3_NVIC_IPR13_OFFSET 0xe434 -#define GC_M3_NVIC_IPR13_DEFAULT 0x0 -#define GC_M3_NVIC_IPR14_OFFSET 0xe438 -#define GC_M3_NVIC_IPR14_DEFAULT 0x0 -#define GC_M3_NVIC_IPR15_OFFSET 0xe43c -#define GC_M3_NVIC_IPR15_DEFAULT 0x0 -#define GC_M3_NVIC_IPR16_OFFSET 0xe440 -#define GC_M3_NVIC_IPR16_DEFAULT 0x0 -#define GC_M3_NVIC_IPR17_OFFSET 0xe444 -#define GC_M3_NVIC_IPR17_DEFAULT 0x0 -#define GC_M3_NVIC_IPR18_OFFSET 0xe448 -#define GC_M3_NVIC_IPR18_DEFAULT 0x0 -#define GC_M3_NVIC_IPR19_OFFSET 0xe44c -#define GC_M3_NVIC_IPR19_DEFAULT 0x0 -#define GC_M3_NVIC_IPR20_OFFSET 0xe450 -#define GC_M3_NVIC_IPR20_DEFAULT 0x0 -#define GC_M3_NVIC_IPR21_OFFSET 0xe454 -#define GC_M3_NVIC_IPR21_DEFAULT 0x0 -#define GC_M3_NVIC_IPR22_OFFSET 0xe458 -#define GC_M3_NVIC_IPR22_DEFAULT 0x0 -#define GC_M3_NVIC_IPR23_OFFSET 0xe45c -#define GC_M3_NVIC_IPR23_DEFAULT 0x0 -#define GC_M3_NVIC_IPR24_OFFSET 0xe460 -#define GC_M3_NVIC_IPR24_DEFAULT 0x0 -#define GC_M3_NVIC_IPR25_OFFSET 0xe464 -#define GC_M3_NVIC_IPR25_DEFAULT 0x0 -#define GC_M3_NVIC_IPR26_OFFSET 0xe468 -#define GC_M3_NVIC_IPR26_DEFAULT 0x0 -#define GC_M3_NVIC_IPR27_OFFSET 0xe46c -#define GC_M3_NVIC_IPR27_DEFAULT 0x0 -#define GC_M3_NVIC_IPR28_OFFSET 0xe470 -#define GC_M3_NVIC_IPR28_DEFAULT 0x0 -#define GC_M3_NVIC_IPR29_OFFSET 0xe474 -#define GC_M3_NVIC_IPR29_DEFAULT 0x0 -#define GC_M3_NVIC_IPR30_OFFSET 0xe478 -#define GC_M3_NVIC_IPR30_DEFAULT 0x0 -#define GC_M3_NVIC_IPR31_OFFSET 0xe47c -#define GC_M3_NVIC_IPR31_DEFAULT 0x0 -#define GC_M3_NVIC_IPR32_OFFSET 0xe480 -#define GC_M3_NVIC_IPR32_DEFAULT 0x0 -#define GC_M3_NVIC_IPR33_OFFSET 0xe484 -#define GC_M3_NVIC_IPR33_DEFAULT 0x0 -#define GC_M3_NVIC_IPR34_OFFSET 0xe488 -#define GC_M3_NVIC_IPR34_DEFAULT 0x0 -#define GC_M3_NVIC_IPR35_OFFSET 0xe48c -#define GC_M3_NVIC_IPR35_DEFAULT 0x0 -#define GC_M3_NVIC_IPR36_OFFSET 0xe490 -#define GC_M3_NVIC_IPR36_DEFAULT 0x0 -#define GC_M3_NVIC_IPR37_OFFSET 0xe494 -#define GC_M3_NVIC_IPR37_DEFAULT 0x0 -#define GC_M3_NVIC_IPR38_OFFSET 0xe498 -#define GC_M3_NVIC_IPR38_DEFAULT 0x0 -#define GC_M3_NVIC_IPR39_OFFSET 0xe49c -#define GC_M3_NVIC_IPR39_DEFAULT 0x0 -#define GC_M3_NVIC_IPR40_OFFSET 0xe4a0 -#define GC_M3_NVIC_IPR40_DEFAULT 0x0 -#define GC_M3_NVIC_IPR41_OFFSET 0xe4a4 -#define GC_M3_NVIC_IPR41_DEFAULT 0x0 -#define GC_M3_NVIC_IPR42_OFFSET 0xe4a8 -#define GC_M3_NVIC_IPR42_DEFAULT 0x0 -#define GC_M3_NVIC_IPR43_OFFSET 0xe4ac -#define GC_M3_NVIC_IPR43_DEFAULT 0x0 -#define GC_M3_NVIC_IPR44_OFFSET 0xe4b0 -#define GC_M3_NVIC_IPR44_DEFAULT 0x0 -#define GC_M3_NVIC_IPR45_OFFSET 0xe4b4 -#define GC_M3_NVIC_IPR45_DEFAULT 0x0 -#define GC_M3_NVIC_IPR46_OFFSET 0xe4b8 -#define GC_M3_NVIC_IPR46_DEFAULT 0x0 -#define GC_M3_NVIC_IPR47_OFFSET 0xe4bc -#define GC_M3_NVIC_IPR47_DEFAULT 0x0 -#define GC_M3_NVIC_IPR48_OFFSET 0xe4c0 -#define GC_M3_NVIC_IPR48_DEFAULT 0x0 -#define GC_M3_NVIC_IPR49_OFFSET 0xe4c4 -#define GC_M3_NVIC_IPR49_DEFAULT 0x0 -#define GC_M3_NVIC_IPR50_OFFSET 0xe4c8 -#define GC_M3_NVIC_IPR50_DEFAULT 0x0 -#define GC_M3_NVIC_IPR51_OFFSET 0xe4cc -#define GC_M3_NVIC_IPR51_DEFAULT 0x0 -#define GC_M3_NVIC_IPR52_OFFSET 0xe4d0 -#define GC_M3_NVIC_IPR52_DEFAULT 0x0 -#define GC_M3_NVIC_IPR53_OFFSET 0xe4d4 -#define GC_M3_NVIC_IPR53_DEFAULT 0x0 -#define GC_M3_NVIC_IPR54_OFFSET 0xe4d8 -#define GC_M3_NVIC_IPR54_DEFAULT 0x0 -#define GC_M3_NVIC_IPR55_OFFSET 0xe4dc -#define GC_M3_NVIC_IPR55_DEFAULT 0x0 -#define GC_M3_NVIC_IPR56_OFFSET 0xe4e0 -#define GC_M3_NVIC_IPR56_DEFAULT 0x0 -#define GC_M3_NVIC_IPR57_OFFSET 0xe4e4 -#define GC_M3_NVIC_IPR57_DEFAULT 0x0 -#define GC_M3_NVIC_IPR58_OFFSET 0xe4e8 -#define GC_M3_NVIC_IPR58_DEFAULT 0x0 #define GC_M3_CPUID_OFFSET 0xed00 #define GC_M3_CPUID_DEFAULT 0x412fc231 #define GC_M3_ICSR_OFFSET 0xed04 @@ -5520,26 +5758,32 @@ #define GC_M3_TPIU_FFCR_DEFAULT 0x0 #define GC_M3_TPIU_FSCR_OFFSET 0x40308 #define GC_M3_TPIU_FSCR_DEFAULT 0x0 -#define GC_M3_TRIGGER_OFFSET 0x40ee8 +#define GC_M3_TRIGGER_OFFSET 0x41ee8 #define GC_M3_TRIGGER_DEFAULT 0x0 -#define GC_M3_FIFO_DATA0_OFFSET 0x40eec -#define GC_M3_FIFO_DATA0_DEFAULT 0x0 -#define GC_M3_ITATBCTR2_OFFSET 0x40ef0 +#define GC_M3_ITATBCTR2_OFFSET 0x41ef0 #define GC_M3_ITATBCTR2_DEFAULT 0x0 -#define GC_M3_ITATBCTR0_OFFSET 0x40ef8 +#define GC_M3_ITATBCTR0_OFFSET 0x41ef8 #define GC_M3_ITATBCTR0_DEFAULT 0x0 -#define GC_M3_FIFO_DATA1_OFFSET 0x40efc -#define GC_M3_FIFO_DATA1_DEFAULT 0x0 -#define GC_M3_ITCTRL_OFFSET 0x40f00 +#define GC_M3_ITCTRL_OFFSET 0x41f00 #define GC_M3_ITCTRL_DEFAULT 0x0 -#define GC_M3_CLAIMSET_OFFSET 0x40fa0 +#define GC_M3_CLAIMSET_OFFSET 0x41fa0 #define GC_M3_CLAIMSET_DEFAULT 0x0 -#define GC_M3_CLAIMCLR_OFFSET 0x40fa4 +#define GC_M3_CLAIMCLR_OFFSET 0x41fa4 #define GC_M3_CLAIMCLR_DEFAULT 0x0 -#define GC_M3_DEVID_OFFSET 0x40fc8 +#define GC_M3_DEVID_OFFSET 0x41fc8 #define GC_M3_DEVID_DEFAULT 0xca0 -#define GC_M3_DEVTYPE_OFFSET 0x40fcc +#define GC_M3_DEVTYPE_OFFSET 0x41fcc #define GC_M3_DEVTYPE_DEFAULT 0x11 +#define GC_M3_HASHER_LOAD_OFFSET 0xaa008 +#define GC_M3_HASHER_LOAD_DEFAULT 0x0 +#define GC_M3_HASHER_START_OFFSET 0xaa010 +#define GC_M3_HASHER_START_DEFAULT 0x0 +#define GC_M3_HASHER_STOP_OFFSET 0xaa018 +#define GC_M3_HASHER_STOP_DEFAULT 0x0 +#define GC_M3_HASHER_CHECK_OFFSET 0xaa020 +#define GC_M3_HASHER_CHECK_DEFAULT 0x0 +#define GC_M3_HASHER_VALUE_OFFSET 0xaa028 +#define GC_M3_HASHER_VALUE_DEFAULT 0x0 #define GC_M3_ITM_STIM0_ADDR 0xe0000000 #define GC_M3_ITM_STIM1_ADDR 0xe0000004 #define GC_M3_ITM_STIM2_ADDR 0xe0000008 @@ -5572,14 +5816,27 @@ #define GC_M3_ITM_STIM29_ADDR 0xe0000074 #define GC_M3_ITM_STIM30_ADDR 0xe0000078 #define GC_M3_ITM_STIM31_ADDR 0xe000007c +#define GC_M3_ITM_STIM32_ADDR 0xe0000080 #define GC_M3_ITM_TER_ADDR 0xe0000e00 #define GC_M3_ITM_TPR_ADDR 0xe0000e40 #define GC_M3_ITM_TCR_ADDR 0xe0000e80 -#define GC_M3_ITM_INTRREG_ADDR 0xe0000ef0 #define GC_M3_ITM_INTWREG_ADDR 0xe0000ef8 +#define GC_M3_ITM_INTRREG_ADDR 0xe0000efc #define GC_M3_ITM_INTMREG_ADDR 0xe0000f00 #define GC_M3_ITM_LOCKCREG_ADDR 0xe0000fb0 #define GC_M3_ITM_LOCKSREG_ADDR 0xe0000fb4 +#define GC_M3_FP_PID4_ADDR 0xe0000fd0 +#define GC_M3_FP_PID5_ADDR 0xe0000fd4 +#define GC_M3_FP_PID6_ADDR 0xe0000fd8 +#define GC_M3_FP_PID7_ADDR 0xe0000fdc +#define GC_M3_FP_PID0_ADDR 0xe0000fe0 +#define GC_M3_FP_PID1_ADDR 0xe0000fe4 +#define GC_M3_FP_PID2_ADDR 0xe0000fe8 +#define GC_M3_FP_PID3_ADDR 0xe0000fec +#define GC_M3_FP_CID0_ADDR 0xe0000ff0 +#define GC_M3_FP_CID1_ADDR 0xe0000ff4 +#define GC_M3_FP_CID2_ADDR 0xe0000ff8 +#define GC_M3_FP_CID3_ADDR 0xe0000ffc #define GC_M3_DWT_CTRL_ADDR 0xe0001000 #define GC_M3_DWT_CYCCNT_ADDR 0xe0001004 #define GC_M3_DWT_CPICNT_ADDR 0xe0001008 @@ -5663,57 +5920,6 @@ #define GC_M3_NVIC_IPR5_ADDR 0xe000e414 #define GC_M3_NVIC_IPR6_ADDR 0xe000e418 #define GC_M3_NVIC_IPR7_ADDR 0xe000e41c -#define GC_M3_NVIC_IPR8_ADDR 0xe000e420 -#define GC_M3_NVIC_IPR9_ADDR 0xe000e424 -#define GC_M3_NVIC_IPR10_ADDR 0xe000e428 -#define GC_M3_NVIC_IPR11_ADDR 0xe000e42c -#define GC_M3_NVIC_IPR12_ADDR 0xe000e430 -#define GC_M3_NVIC_IPR13_ADDR 0xe000e434 -#define GC_M3_NVIC_IPR14_ADDR 0xe000e438 -#define GC_M3_NVIC_IPR15_ADDR 0xe000e43c -#define GC_M3_NVIC_IPR16_ADDR 0xe000e440 -#define GC_M3_NVIC_IPR17_ADDR 0xe000e444 -#define GC_M3_NVIC_IPR18_ADDR 0xe000e448 -#define GC_M3_NVIC_IPR19_ADDR 0xe000e44c -#define GC_M3_NVIC_IPR20_ADDR 0xe000e450 -#define GC_M3_NVIC_IPR21_ADDR 0xe000e454 -#define GC_M3_NVIC_IPR22_ADDR 0xe000e458 -#define GC_M3_NVIC_IPR23_ADDR 0xe000e45c -#define GC_M3_NVIC_IPR24_ADDR 0xe000e460 -#define GC_M3_NVIC_IPR25_ADDR 0xe000e464 -#define GC_M3_NVIC_IPR26_ADDR 0xe000e468 -#define GC_M3_NVIC_IPR27_ADDR 0xe000e46c -#define GC_M3_NVIC_IPR28_ADDR 0xe000e470 -#define GC_M3_NVIC_IPR29_ADDR 0xe000e474 -#define GC_M3_NVIC_IPR30_ADDR 0xe000e478 -#define GC_M3_NVIC_IPR31_ADDR 0xe000e47c -#define GC_M3_NVIC_IPR32_ADDR 0xe000e480 -#define GC_M3_NVIC_IPR33_ADDR 0xe000e484 -#define GC_M3_NVIC_IPR34_ADDR 0xe000e488 -#define GC_M3_NVIC_IPR35_ADDR 0xe000e48c -#define GC_M3_NVIC_IPR36_ADDR 0xe000e490 -#define GC_M3_NVIC_IPR37_ADDR 0xe000e494 -#define GC_M3_NVIC_IPR38_ADDR 0xe000e498 -#define GC_M3_NVIC_IPR39_ADDR 0xe000e49c -#define GC_M3_NVIC_IPR40_ADDR 0xe000e4a0 -#define GC_M3_NVIC_IPR41_ADDR 0xe000e4a4 -#define GC_M3_NVIC_IPR42_ADDR 0xe000e4a8 -#define GC_M3_NVIC_IPR43_ADDR 0xe000e4ac -#define GC_M3_NVIC_IPR44_ADDR 0xe000e4b0 -#define GC_M3_NVIC_IPR45_ADDR 0xe000e4b4 -#define GC_M3_NVIC_IPR46_ADDR 0xe000e4b8 -#define GC_M3_NVIC_IPR47_ADDR 0xe000e4bc -#define GC_M3_NVIC_IPR48_ADDR 0xe000e4c0 -#define GC_M3_NVIC_IPR49_ADDR 0xe000e4c4 -#define GC_M3_NVIC_IPR50_ADDR 0xe000e4c8 -#define GC_M3_NVIC_IPR51_ADDR 0xe000e4cc -#define GC_M3_NVIC_IPR52_ADDR 0xe000e4d0 -#define GC_M3_NVIC_IPR53_ADDR 0xe000e4d4 -#define GC_M3_NVIC_IPR54_ADDR 0xe000e4d8 -#define GC_M3_NVIC_IPR55_ADDR 0xe000e4dc -#define GC_M3_NVIC_IPR56_ADDR 0xe000e4e0 -#define GC_M3_NVIC_IPR57_ADDR 0xe000e4e4 -#define GC_M3_NVIC_IPR58_ADDR 0xe000e4e8 #define GC_M3_CPUID_ADDR 0xe000ed00 #define GC_M3_ICSR_ADDR 0xe000ed04 #define GC_M3_VTOR_ADDR 0xe000ed08 @@ -5752,35 +5958,38 @@ #define GC_M3_TPIU_FFSR_ADDR 0xe0040300 #define GC_M3_TPIU_FFCR_ADDR 0xe0040304 #define GC_M3_TPIU_FSCR_ADDR 0xe0040308 -#define GC_M3_TRIGGER_ADDR 0xe0040ee8 -#define GC_M3_FIFO_DATA0_ADDR 0xe0040eec -#define GC_M3_ITATBCTR2_ADDR 0xe0040ef0 -#define GC_M3_ITATBCTR0_ADDR 0xe0040ef8 -#define GC_M3_FIFO_DATA1_ADDR 0xe0040efc -#define GC_M3_ITCTRL_ADDR 0xe0040f00 -#define GC_M3_CLAIMSET_ADDR 0xe0040fa0 -#define GC_M3_CLAIMCLR_ADDR 0xe0040fa4 -#define GC_M3_DEVID_ADDR 0xe0040fc8 -#define GC_M3_DEVTYPE_ADDR 0xe0040fcc +#define GC_M3_TRIGGER_ADDR 0xe0041ee8 +#define GC_M3_ITATBCTR2_ADDR 0xe0041ef0 +#define GC_M3_ITATBCTR0_ADDR 0xe0041ef8 +#define GC_M3_ITCTRL_ADDR 0xe0041f00 +#define GC_M3_CLAIMSET_ADDR 0xe0041fa0 +#define GC_M3_CLAIMCLR_ADDR 0xe0041fa4 +#define GC_M3_DEVID_ADDR 0xe0041fc8 +#define GC_M3_DEVTYPE_ADDR 0xe0041fcc +#define GC_M3_HASHER_LOAD_ADDR 0xe00aa008 +#define GC_M3_HASHER_START_ADDR 0xe00aa010 +#define GC_M3_HASHER_STOP_ADDR 0xe00aa018 +#define GC_M3_HASHER_CHECK_ADDR 0xe00aa020 +#define GC_M3_HASHER_VALUE_ADDR 0xe00aa028 #define GC_CAMO_VERSION_CHANGE_LSB 0x0 #define GC_CAMO_VERSION_CHANGE_MASK 0xffffff #define GC_CAMO_VERSION_CHANGE_SIZE 0x18 -#define GC_CAMO_VERSION_CHANGE_DEFAULT 0xe1a1 -#define GC_CAMO_VERSION_CHANGE_OFFSET 0x10 +#define GC_CAMO_VERSION_CHANGE_DEFAULT 0x11319 +#define GC_CAMO_VERSION_CHANGE_OFFSET 0x8 #define GC_CAMO_VERSION_REVISION_LSB 0x18 #define GC_CAMO_VERSION_REVISION_MASK 0xff000000 #define GC_CAMO_VERSION_REVISION_SIZE 0x8 -#define GC_CAMO_VERSION_REVISION_DEFAULT 0x2 -#define GC_CAMO_VERSION_REVISION_OFFSET 0x10 +#define GC_CAMO_VERSION_REVISION_DEFAULT 0x3 +#define GC_CAMO_VERSION_REVISION_OFFSET 0x8 #define GC_CRYPTO_VERSION_CHANGE_LSB 0x0 #define GC_CRYPTO_VERSION_CHANGE_MASK 0xffffff #define GC_CRYPTO_VERSION_CHANGE_SIZE 0x18 -#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x10ed8 +#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x11ed5 #define GC_CRYPTO_VERSION_CHANGE_OFFSET 0x0 #define GC_CRYPTO_VERSION_REVISION_LSB 0x18 #define GC_CRYPTO_VERSION_REVISION_MASK 0xff000000 #define GC_CRYPTO_VERSION_REVISION_SIZE 0x8 -#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x24 +#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x28 #define GC_CRYPTO_VERSION_REVISION_OFFSET 0x0 #define GC_CRYPTO_CONTROL_RESET_LSB 0x0 #define GC_CRYPTO_CONTROL_RESET_MASK 0x1 @@ -5797,46 +6006,46 @@ #define GC_CRYPTO_CONTROL_RESUME_SIZE 0x1 #define GC_CRYPTO_CONTROL_RESUME_DEFAULT 0x0 #define GC_CRYPTO_CONTROL_RESUME_OFFSET 0x4 -#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_LSB 0x0 -#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_MASK 0x1 -#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_SIZE 0x1 -#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_IMEM_SCRUB_EN_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_LSB 0x1 -#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_MASK 0x2 -#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_SIZE 0x1 -#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_DMEM_SCRUB_EN_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_LSB 0x2 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_MASK 0x4 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_SIZE 0x1 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_INV_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_LSB 0x3 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_MASK 0x8 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_SIZE 0x1 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_INV_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_SCRUB_FREQ_LSB 0x4 -#define GC_CRYPTO_CONFIG_SCRUB_FREQ_MASK 0x30 -#define GC_CRYPTO_CONFIG_SCRUB_FREQ_SIZE 0x2 -#define GC_CRYPTO_CONFIG_SCRUB_FREQ_DEFAULT 0x1 -#define GC_CRYPTO_CONFIG_SCRUB_FREQ_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_LSB 0x6 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_MASK 0x40 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_SIZE 0x1 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_DMEM_PARITY_ALERT_EN_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_LSB 0x7 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_MASK 0x80 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_SIZE 0x1 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_IMEM_PARITY_ALERT_EN_OFFSET 0x8 -#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_LSB 0x8 -#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_MASK 0x100 -#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_SIZE 0x1 -#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_DEFAULT 0x0 -#define GC_CRYPTO_CONFIG_DRF_PARITY_ALERT_EN_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_LSB 0x0 +#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_MASK 0x1 +#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_LSB 0x1 +#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_MASK 0x2 +#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_IMEM_INV_LSB 0x2 +#define GC_CRYPTO_PARITY_CFG_IMEM_INV_MASK 0x4 +#define GC_CRYPTO_PARITY_CFG_IMEM_INV_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_IMEM_INV_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_IMEM_INV_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_DMEM_INV_LSB 0x3 +#define GC_CRYPTO_PARITY_CFG_DMEM_INV_MASK 0x8 +#define GC_CRYPTO_PARITY_CFG_DMEM_INV_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_DMEM_INV_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_DMEM_INV_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_LSB 0x4 +#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_MASK 0x30 +#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_SIZE 0x2 +#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_DEFAULT 0x1 +#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_DMEM_EN_LSB 0x6 +#define GC_CRYPTO_PARITY_CFG_DMEM_EN_MASK 0x40 +#define GC_CRYPTO_PARITY_CFG_DMEM_EN_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_DMEM_EN_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_DMEM_EN_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_IMEM_EN_LSB 0x7 +#define GC_CRYPTO_PARITY_CFG_IMEM_EN_MASK 0x80 +#define GC_CRYPTO_PARITY_CFG_IMEM_EN_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_IMEM_EN_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_IMEM_EN_OFFSET 0x8 +#define GC_CRYPTO_PARITY_CFG_DRF_EN_LSB 0x8 +#define GC_CRYPTO_PARITY_CFG_DRF_EN_MASK 0x100 +#define GC_CRYPTO_PARITY_CFG_DRF_EN_SIZE 0x1 +#define GC_CRYPTO_PARITY_CFG_DRF_EN_DEFAULT 0x0 +#define GC_CRYPTO_PARITY_CFG_DRF_EN_OFFSET 0x8 #define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_LSB 0x0 #define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_MASK 0x3ff #define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_SIZE 0xa @@ -6087,55 +6296,40 @@ #define GC_CRYPTO_RAND_STALL_CTL_FREQ_SIZE 0x2 #define GC_CRYPTO_RAND_STALL_CTL_FREQ_DEFAULT 0x2 #define GC_CRYPTO_RAND_STALL_CTL_FREQ_OFFSET 0x30 -#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_LSB 0x0 -#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_MASK 0xffff -#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_SIZE 0x10 -#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_DEFAULT 0x0 -#define GC_CRYPTO_IMEM_PARITY_CFG_THRESH_OFFSET 0x40 -#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_LSB 0x0 -#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_MASK 0xffff -#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_SIZE 0x10 -#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_DEFAULT 0x0 -#define GC_CRYPTO_DMEM_PARITY_CFG_THRESH_OFFSET 0x44 -#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_LSB 0x0 -#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_MASK 0xffff -#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_SIZE 0x10 -#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_DEFAULT 0x0 -#define GC_CRYPTO_DRF_PARITY_CFG_THRESH_OFFSET 0x48 #define GC_CRYPTO_PGM_LFSR_SIG_LSB 0x0 #define GC_CRYPTO_PGM_LFSR_SIG_MASK 0xffffff #define GC_CRYPTO_PGM_LFSR_SIG_SIZE 0x18 #define GC_CRYPTO_PGM_LFSR_SIG_DEFAULT 0x0 -#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET 0x4c +#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET 0x40 #define GC_CRYPTO_DEBUG_BRKPT0_PC_LSB 0x0 #define GC_CRYPTO_DEBUG_BRKPT0_PC_MASK 0x3ff #define GC_CRYPTO_DEBUG_BRKPT0_PC_SIZE 0xa #define GC_CRYPTO_DEBUG_BRKPT0_PC_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET 0x44 #define GC_CRYPTO_DEBUG_BRKPT0_EN_LSB 0x1f #define GC_CRYPTO_DEBUG_BRKPT0_EN_MASK 0x80000000 #define GC_CRYPTO_DEBUG_BRKPT0_EN_SIZE 0x1 #define GC_CRYPTO_DEBUG_BRKPT0_EN_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET 0x50 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET 0x44 #define GC_CRYPTO_DEBUG_BRKPT1_PC_LSB 0x0 #define GC_CRYPTO_DEBUG_BRKPT1_PC_MASK 0x3ff #define GC_CRYPTO_DEBUG_BRKPT1_PC_SIZE 0xa #define GC_CRYPTO_DEBUG_BRKPT1_PC_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET 0x54 +#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET 0x48 #define GC_CRYPTO_DEBUG_BRKPT1_EN_LSB 0x1f #define GC_CRYPTO_DEBUG_BRKPT1_EN_MASK 0x80000000 #define GC_CRYPTO_DEBUG_BRKPT1_EN_SIZE 0x1 #define GC_CRYPTO_DEBUG_BRKPT1_EN_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET 0x54 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET 0x48 #define GC_DMA_VERSION_CHANGE_LSB 0x0 #define GC_DMA_VERSION_CHANGE_MASK 0xffffff #define GC_DMA_VERSION_CHANGE_SIZE 0x18 -#define GC_DMA_VERSION_CHANGE_DEFAULT 0x10532 +#define GC_DMA_VERSION_CHANGE_DEFAULT 0x11d58 #define GC_DMA_VERSION_CHANGE_OFFSET 0x0 #define GC_DMA_VERSION_REVISION_LSB 0x18 #define GC_DMA_VERSION_REVISION_MASK 0xff000000 #define GC_DMA_VERSION_REVISION_SIZE 0x8 -#define GC_DMA_VERSION_REVISION_DEFAULT 0xf +#define GC_DMA_VERSION_REVISION_DEFAULT 0x12 #define GC_DMA_VERSION_REVISION_OFFSET 0x0 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_LSB 0x0 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_MASK 0xff @@ -6197,806 +6391,686 @@ #define GC_DMA_INT_TEST_INTR_ERROR_CHAN_SIZE 0x8 #define GC_DMA_INT_TEST_INTR_ERROR_CHAN_DEFAULT 0x0 #define GC_DMA_INT_TEST_INTR_ERROR_CHAN_OFFSET 0xc -#define GC_DMA_CTRL_CHAN0_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN0_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN0_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN0_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_ENABLE_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN0_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN0_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN0_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_STOP_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN0_CLR_ERROR_MASK 0x4 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN0_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_CLR_ERROR_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN0_CLR_ERROR_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN0_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN0_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_WRAP_MODE_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN0_WRAP_MODE_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN0_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN0_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN0_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_NCHK_FULL_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN0_NCHK_FULL_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_OFFSET 0x100 -#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_OFFSET 0x108 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_OFFSET 0x100 +#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_OFFSET 0x108 #define GC_DMA_FSM_STATE_CHAN0_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN0_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN0_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN0_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN0_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN0_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_WAIT_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN0_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN0_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN0_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN0_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN0_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN0_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET 0x120 -#define GC_DMA_FSM_STATE_CHAN0_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN0_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN0_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET 0x120 -#define GC_DMA_CTRL_CHAN1_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN1_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN1_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN1_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_ENABLE_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN1_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN1_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN1_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_STOP_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN1_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET 0x124 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN1_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_CLR_ERROR_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN1_CLR_ERROR_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN1_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN1_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_WRAP_MODE_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN1_WRAP_MODE_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN1_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN1_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN1_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_NCHK_FULL_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN1_NCHK_FULL_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_OFFSET 0x200 -#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_OFFSET 0x208 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_OFFSET 0x200 +#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_OFFSET 0x208 #define GC_DMA_FSM_STATE_CHAN1_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN1_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN1_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN1_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN1_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN1_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_WAIT_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN1_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN1_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN1_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN1_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN1_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN1_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET 0x220 -#define GC_DMA_FSM_STATE_CHAN1_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN1_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN1_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET 0x220 -#define GC_DMA_CTRL_CHAN2_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN2_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN2_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN2_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_ENABLE_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN2_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN2_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN2_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_STOP_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN2_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET 0x224 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN2_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_CLR_ERROR_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN2_CLR_ERROR_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN2_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN2_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_WRAP_MODE_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN2_WRAP_MODE_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN2_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN2_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN2_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_NCHK_FULL_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN2_NCHK_FULL_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_OFFSET 0x300 -#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_OFFSET 0x308 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_OFFSET 0x300 +#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_OFFSET 0x308 #define GC_DMA_FSM_STATE_CHAN2_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN2_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN2_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN2_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN2_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN2_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_WAIT_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN2_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN2_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN2_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN2_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN2_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN2_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET 0x320 -#define GC_DMA_FSM_STATE_CHAN2_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN2_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN2_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET 0x320 -#define GC_DMA_CTRL_CHAN3_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN3_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN3_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN3_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_ENABLE_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN3_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN3_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN3_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_STOP_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN3_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET 0x324 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN3_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_CLR_ERROR_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN3_CLR_ERROR_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN3_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN3_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_WRAP_MODE_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN3_WRAP_MODE_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN3_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN3_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN3_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_NCHK_FULL_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN3_NCHK_FULL_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_OFFSET 0x400 -#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_OFFSET 0x408 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_OFFSET 0x400 +#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_OFFSET 0x408 #define GC_DMA_FSM_STATE_CHAN3_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN3_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN3_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN3_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN3_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN3_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_WAIT_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN3_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN3_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN3_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN3_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN3_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN3_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET 0x420 -#define GC_DMA_FSM_STATE_CHAN3_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN3_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN3_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET 0x420 -#define GC_DMA_CTRL_CHAN4_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN4_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN4_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN4_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_ENABLE_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN4_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN4_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN4_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_STOP_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN4_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET 0x424 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN4_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_CLR_ERROR_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN4_CLR_ERROR_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN4_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN4_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_WRAP_MODE_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN4_WRAP_MODE_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN4_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN4_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN4_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_NCHK_FULL_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN4_NCHK_FULL_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_OFFSET 0x500 -#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_OFFSET 0x508 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_OFFSET 0x500 +#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_OFFSET 0x508 #define GC_DMA_FSM_STATE_CHAN4_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN4_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN4_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN4_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN4_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN4_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_WAIT_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN4_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN4_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN4_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN4_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN4_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN4_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET 0x520 -#define GC_DMA_FSM_STATE_CHAN4_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN4_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN4_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET 0x520 -#define GC_DMA_CTRL_CHAN5_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN5_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN5_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN5_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_ENABLE_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN5_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN5_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN5_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_STOP_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN5_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET 0x524 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN5_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_CLR_ERROR_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN5_CLR_ERROR_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN5_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN5_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_WRAP_MODE_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN5_WRAP_MODE_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN5_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN5_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN5_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_NCHK_FULL_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN5_NCHK_FULL_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_OFFSET 0x600 -#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_OFFSET 0x608 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_OFFSET 0x600 +#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_OFFSET 0x608 #define GC_DMA_FSM_STATE_CHAN5_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN5_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN5_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN5_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN5_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN5_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_WAIT_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN5_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN5_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN5_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN5_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN5_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN5_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET 0x620 -#define GC_DMA_FSM_STATE_CHAN5_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN5_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN5_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET 0x620 -#define GC_DMA_CTRL_CHAN6_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN6_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN6_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN6_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_ENABLE_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN6_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN6_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN6_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_STOP_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN6_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET 0x624 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN6_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_CLR_ERROR_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN6_CLR_ERROR_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN6_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN6_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_WRAP_MODE_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN6_WRAP_MODE_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN6_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN6_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN6_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_NCHK_FULL_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN6_NCHK_FULL_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_OFFSET 0x700 -#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_OFFSET 0x708 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_OFFSET 0x700 +#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_OFFSET 0x708 #define GC_DMA_FSM_STATE_CHAN6_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN6_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN6_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN6_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN6_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN6_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_WAIT_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN6_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN6_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN6_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN6_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN6_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN6_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET 0x720 -#define GC_DMA_FSM_STATE_CHAN6_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN6_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN6_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET 0x720 -#define GC_DMA_CTRL_CHAN7_ENABLE_LSB 0x0 -#define GC_DMA_CTRL_CHAN7_ENABLE_MASK 0x1 -#define GC_DMA_CTRL_CHAN7_ENABLE_SIZE 0x1 -#define GC_DMA_CTRL_CHAN7_ENABLE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_ENABLE_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_STOP_LSB 0x1 -#define GC_DMA_CTRL_CHAN7_STOP_MASK 0x2 -#define GC_DMA_CTRL_CHAN7_STOP_SIZE 0x1 -#define GC_DMA_CTRL_CHAN7_STOP_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_STOP_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_CLR_ERROR_LSB 0x2 -#define GC_DMA_CTRL_CHAN7_CLR_ERROR_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET 0x724 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_LSB 0x0 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN7_CLR_ERROR_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_CLR_ERROR_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_CLR_ERROR_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_LSB 0x3 -#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_MASK 0x8 +#define GC_DMA_CTRL_CHAN7_CLR_ERROR_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_LSB 0x1 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_MASK 0x2 #define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_WRAP_MODE_LSB 0x4 -#define GC_DMA_CTRL_CHAN7_WRAP_MODE_MASK 0x10 +#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_LSB 0x2 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_MASK 0x4 #define GC_DMA_CTRL_CHAN7_WRAP_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_WRAP_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_WRAP_MODE_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_LSB 0x5 -#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_MASK 0x20 +#define GC_DMA_CTRL_CHAN7_WRAP_MODE_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_LSB 0x3 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_MASK 0x8 #define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_DEFAULT 0x1 -#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_LSB 0x6 -#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_MASK 0x40 +#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_LSB 0x4 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_MASK 0x10 #define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_LSB 0x7 -#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_MASK 0x80 +#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_LSB 0x5 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_MASK 0x20 #define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_NCHK_FULL_LSB 0x8 -#define GC_DMA_CTRL_CHAN7_NCHK_FULL_MASK 0x100 +#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_LSB 0x6 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_MASK 0x40 #define GC_DMA_CTRL_CHAN7_NCHK_FULL_SIZE 0x1 #define GC_DMA_CTRL_CHAN7_NCHK_FULL_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_NCHK_FULL_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_LSB 0x9 -#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_MASK 0xe00 +#define GC_DMA_CTRL_CHAN7_NCHK_FULL_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_LSB 0x7 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_MASK 0x380 #define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_OFFSET 0x800 -#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_LSB 0xc -#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_MASK 0x7000 +#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_OFFSET 0x808 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_LSB 0xa +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_MASK 0x1c00 #define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_SIZE 0x3 #define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_DEFAULT 0x0 -#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_OFFSET 0x800 +#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_OFFSET 0x808 #define GC_DMA_FSM_STATE_CHAN7_IDLE_LSB 0x0 #define GC_DMA_FSM_STATE_CHAN7_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN7_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_WAIT_LSB 0x1 -#define GC_DMA_FSM_STATE_CHAN7_WAIT_MASK 0x2 -#define GC_DMA_FSM_STATE_CHAN7_WAIT_SIZE 0x1 -#define GC_DMA_FSM_STATE_CHAN7_WAIT_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_WAIT_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_BID_READ_LSB 0x2 -#define GC_DMA_FSM_STATE_CHAN7_BID_READ_MASK 0x4 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_LSB 0x1 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_LSB 0x3 -#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_MASK 0x8 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_LSB 0x2 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_LSB 0x4 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_MASK 0x10 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_LSB 0x3 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_LSB 0x5 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_MASK 0x20 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_LSB 0x4 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_READ_LSB 0x6 -#define GC_DMA_FSM_STATE_CHAN7_READ_MASK 0x40 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_READ_LSB 0x5 +#define GC_DMA_FSM_STATE_CHAN7_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN7_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_WRITE_LSB 0x7 -#define GC_DMA_FSM_STATE_CHAN7_WRITE_MASK 0x80 +#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_LSB 0x6 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN7_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET 0x820 -#define GC_DMA_FSM_STATE_CHAN7_ERROR_LSB 0x8 -#define GC_DMA_FSM_STATE_CHAN7_ERROR_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_LSB 0x7 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN7_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET 0x820 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET 0x824 #define GC_FLASH_FSH_TRANS_OFFSET_LSB 0x0 #define GC_FLASH_FSH_TRANS_OFFSET_MASK 0xffff #define GC_FLASH_FSH_TRANS_OFFSET_SIZE 0x10 @@ -7012,196 +7086,246 @@ #define GC_FLASH_FSH_TRANS_SIZE_SIZE 0x5 #define GC_FLASH_FSH_TRANS_SIZE_DEFAULT 0x0 #define GC_FLASH_FSH_TRANS_SIZE_OFFSET 0x8 +#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_LSB 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_MASK 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_LSB 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_MASK 0x2 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_LSB 0x2 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_MASK 0x4 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_LSB 0x3 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_MASK 0x8 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_LSB 0x4 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_MASK 0x10 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_LSB 0x5 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_MASK 0x20 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_LSB 0x6 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_MASK 0x40 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_LSB 0x7 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_MASK 0x80 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_OFFSET 0xc +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_LSB 0x8 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_MASK 0x100 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_SIZE 0x1 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_DEFAULT 0x0 +#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_OFFSET 0xc #define GC_FLASH_FSH_ICTRL_EDONE_LSB 0x0 #define GC_FLASH_FSH_ICTRL_EDONE_MASK 0x1 #define GC_FLASH_FSH_ICTRL_EDONE_SIZE 0x1 #define GC_FLASH_FSH_ICTRL_EDONE_DEFAULT 0x0 -#define GC_FLASH_FSH_ICTRL_EDONE_OFFSET 0x10 +#define GC_FLASH_FSH_ICTRL_EDONE_OFFSET 0x14 #define GC_FLASH_FSH_ICTRL_PDONE_LSB 0x1 #define GC_FLASH_FSH_ICTRL_PDONE_MASK 0x2 #define GC_FLASH_FSH_ICTRL_PDONE_SIZE 0x1 #define GC_FLASH_FSH_ICTRL_PDONE_DEFAULT 0x0 -#define GC_FLASH_FSH_ICTRL_PDONE_OFFSET 0x10 +#define GC_FLASH_FSH_ICTRL_PDONE_OFFSET 0x14 #define GC_FLASH_FSH_ISTATE_EDONE_LSB 0x0 #define GC_FLASH_FSH_ISTATE_EDONE_MASK 0x1 #define GC_FLASH_FSH_ISTATE_EDONE_SIZE 0x1 #define GC_FLASH_FSH_ISTATE_EDONE_DEFAULT 0x0 -#define GC_FLASH_FSH_ISTATE_EDONE_OFFSET 0x14 +#define GC_FLASH_FSH_ISTATE_EDONE_OFFSET 0x18 #define GC_FLASH_FSH_ISTATE_PDONE_LSB 0x1 #define GC_FLASH_FSH_ISTATE_PDONE_MASK 0x2 #define GC_FLASH_FSH_ISTATE_PDONE_SIZE 0x1 #define GC_FLASH_FSH_ISTATE_PDONE_DEFAULT 0x0 -#define GC_FLASH_FSH_ISTATE_PDONE_OFFSET 0x14 +#define GC_FLASH_FSH_ISTATE_PDONE_OFFSET 0x18 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_LSB 0x0 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_MASK 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_LSB 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_MASK 0x2 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_LSB 0x2 #define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_MASK 0x4 #define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_TMR_LSB 0x3 #define GC_FLASH_FSH_OVRD_SIGVAL_TMR_MASK 0x8 #define GC_FLASH_FSH_OVRD_SIGVAL_TMR_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_TMR_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_XE_LSB 0x4 #define GC_FLASH_FSH_OVRD_SIGVAL_XE_MASK 0x10 #define GC_FLASH_FSH_OVRD_SIGVAL_XE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_XE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_XE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_XE_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_YE_LSB 0x5 #define GC_FLASH_FSH_OVRD_SIGVAL_YE_MASK 0x20 #define GC_FLASH_FSH_OVRD_SIGVAL_YE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_YE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_YE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_YE_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_SE_LSB 0x6 #define GC_FLASH_FSH_OVRD_SIGVAL_SE_MASK 0x40 #define GC_FLASH_FSH_OVRD_SIGVAL_SE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_SE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_SE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_SE_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_LSB 0x7 #define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_MASK 0x80 #define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_PROG_LSB 0x8 #define GC_FLASH_FSH_OVRD_SIGVAL_PROG_MASK 0x100 #define GC_FLASH_FSH_OVRD_SIGVAL_PROG_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_PROG_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_LSB 0x9 #define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_MASK 0x200 #define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_LSB 0xa #define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_MASK 0x400 #define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_PV_LSB 0xb #define GC_FLASH_FSH_OVRD_SIGVAL_PV_MASK 0x800 #define GC_FLASH_FSH_OVRD_SIGVAL_PV_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_PV_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_PV_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_PV_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGVAL_EV_LSB 0xc #define GC_FLASH_FSH_OVRD_SIGVAL_EV_MASK 0x1000 #define GC_FLASH_FSH_OVRD_SIGVAL_EV_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGVAL_EV_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGVAL_EV_OFFSET 0x28 +#define GC_FLASH_FSH_OVRD_SIGVAL_EV_OFFSET 0x2c #define GC_FLASH_FSH_OVRD_SIGEN_IFREN_LSB 0x0 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN_MASK 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_LSB 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_MASK 0x2 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_REDEN_LSB 0x2 #define GC_FLASH_FSH_OVRD_SIGEN_REDEN_MASK 0x4 #define GC_FLASH_FSH_OVRD_SIGEN_REDEN_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_REDEN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_TMR_LSB 0x3 #define GC_FLASH_FSH_OVRD_SIGEN_TMR_MASK 0x8 #define GC_FLASH_FSH_OVRD_SIGEN_TMR_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_TMR_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_TMR_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_TMR_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_XE_LSB 0x4 #define GC_FLASH_FSH_OVRD_SIGEN_XE_MASK 0x10 #define GC_FLASH_FSH_OVRD_SIGEN_XE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_XE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_XE_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_XE_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_YE_LSB 0x5 #define GC_FLASH_FSH_OVRD_SIGEN_YE_MASK 0x20 #define GC_FLASH_FSH_OVRD_SIGEN_YE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_YE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_YE_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_YE_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_SE_LSB 0x6 #define GC_FLASH_FSH_OVRD_SIGEN_SE_MASK 0x40 #define GC_FLASH_FSH_OVRD_SIGEN_SE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_SE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_SE_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_SE_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_ERASE_LSB 0x7 #define GC_FLASH_FSH_OVRD_SIGEN_ERASE_MASK 0x80 #define GC_FLASH_FSH_OVRD_SIGEN_ERASE_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_ERASE_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_PROG_LSB 0x8 #define GC_FLASH_FSH_OVRD_SIGEN_PROG_MASK 0x100 #define GC_FLASH_FSH_OVRD_SIGEN_PROG_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_PROG_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_PROG_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_PROG_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_MAS1_LSB 0x9 #define GC_FLASH_FSH_OVRD_SIGEN_MAS1_MASK 0x200 #define GC_FLASH_FSH_OVRD_SIGEN_MAS1_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_MAS1_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_LSB 0xa #define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_MASK 0x400 #define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_PV_LSB 0xb #define GC_FLASH_FSH_OVRD_SIGEN_PV_MASK 0x800 #define GC_FLASH_FSH_OVRD_SIGEN_PV_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_PV_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_PV_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_PV_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_EV_LSB 0xc #define GC_FLASH_FSH_OVRD_SIGEN_EV_MASK 0x1000 #define GC_FLASH_FSH_OVRD_SIGEN_EV_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_EV_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_EV_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_EV_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_DIN_LSB 0xd #define GC_FLASH_FSH_OVRD_SIGEN_DIN_MASK 0x2000 #define GC_FLASH_FSH_OVRD_SIGEN_DIN_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_DIN_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_DIN_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_DIN_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_LSB 0xe #define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_MASK 0x4000 #define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_OFFSET 0x30 #define GC_FLASH_FSH_OVRD_SIGEN_DOUT_LSB 0xf #define GC_FLASH_FSH_OVRD_SIGEN_DOUT_MASK 0x8000 #define GC_FLASH_FSH_OVRD_SIGEN_DOUT_SIZE 0x1 #define GC_FLASH_FSH_OVRD_SIGEN_DOUT_DEFAULT 0x0 -#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_OFFSET 0x2c +#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_OFFSET 0x30 +#define GC_FLASH_FSH_OVRD_SIGEN_TC_LSB 0x10 +#define GC_FLASH_FSH_OVRD_SIGEN_TC_MASK 0x10000 +#define GC_FLASH_FSH_OVRD_SIGEN_TC_SIZE 0x1 +#define GC_FLASH_FSH_OVRD_SIGEN_TC_DEFAULT 0x0 +#define GC_FLASH_FSH_OVRD_SIGEN_TC_OFFSET 0x30 #define GC_FLASH_FSH_REDUN0_EN_LSB 0x0 #define GC_FLASH_FSH_REDUN0_EN_MASK 0x1 #define GC_FLASH_FSH_REDUN0_EN_SIZE 0x1 #define GC_FLASH_FSH_REDUN0_EN_DEFAULT 0x0 -#define GC_FLASH_FSH_REDUN0_EN_OFFSET 0xc0 +#define GC_FLASH_FSH_REDUN0_EN_OFFSET 0xcc #define GC_FLASH_FSH_REDUN0_REMAP_LSB 0x1 #define GC_FLASH_FSH_REDUN0_REMAP_MASK 0xfe #define GC_FLASH_FSH_REDUN0_REMAP_SIZE 0x7 #define GC_FLASH_FSH_REDUN0_REMAP_DEFAULT 0x0 -#define GC_FLASH_FSH_REDUN0_REMAP_OFFSET 0xc0 +#define GC_FLASH_FSH_REDUN0_REMAP_OFFSET 0xcc #define GC_FLASH_FSH_REDUN1_EN_LSB 0x0 #define GC_FLASH_FSH_REDUN1_EN_MASK 0x1 #define GC_FLASH_FSH_REDUN1_EN_SIZE 0x1 #define GC_FLASH_FSH_REDUN1_EN_DEFAULT 0x0 -#define GC_FLASH_FSH_REDUN1_EN_OFFSET 0xc4 +#define GC_FLASH_FSH_REDUN1_EN_OFFSET 0xd0 #define GC_FLASH_FSH_REDUN1_REMAP_LSB 0x1 #define GC_FLASH_FSH_REDUN1_REMAP_MASK 0xfe #define GC_FLASH_FSH_REDUN1_REMAP_SIZE 0x7 #define GC_FLASH_FSH_REDUN1_REMAP_DEFAULT 0x0 -#define GC_FLASH_FSH_REDUN1_REMAP_OFFSET 0xc4 +#define GC_FLASH_FSH_REDUN1_REMAP_OFFSET 0xd0 #define GC_FLASH_FSH_DBG_STATE_LSB 0x0 #define GC_FLASH_FSH_DBG_STATE_MASK 0xf #define GC_FLASH_FSH_DBG_STATE_SIZE 0x4 #define GC_FLASH_FSH_DBG_STATE_DEFAULT 0x0 -#define GC_FLASH_FSH_DBG_STATE_OFFSET 0x170 +#define GC_FLASH_FSH_DBG_STATE_OFFSET 0x17c #define GC_FLASH_FSH_ITOP_PDONEINT_LSB 0x0 #define GC_FLASH_FSH_ITOP_PDONEINT_MASK 0x1 #define GC_FLASH_FSH_ITOP_PDONEINT_SIZE 0x1 @@ -7212,728 +7336,1931 @@ #define GC_FLASH_FSH_ITOP_EDONEINT_SIZE 0x1 #define GC_FLASH_FSH_ITOP_EDONEINT_DEFAULT 0x0 #define GC_FLASH_FSH_ITOP_EDONEINT_OFFSET 0xf04 -#define GC_FUSE_STATUS_READ_DONE_LSB 0x0 -#define GC_FUSE_STATUS_READ_DONE_MASK 0x1 +#define GC_FUSE_STATUS_VALID_LSB 0x0 +#define GC_FUSE_STATUS_VALID_MASK 0x1 +#define GC_FUSE_STATUS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_DEFAULTS_VALID_LSB 0x1 +#define GC_FUSE_STATUS_DEFAULTS_VALID_MASK 0x2 +#define GC_FUSE_STATUS_DEFAULTS_VALID_SIZE 0x1 +#define GC_FUSE_STATUS_DEFAULTS_VALID_DEFAULT 0x0 +#define GC_FUSE_STATUS_DEFAULTS_VALID_OFFSET 0x0 +#define GC_FUSE_STATUS_READ_DONE_LSB 0x2 +#define GC_FUSE_STATUS_READ_DONE_MASK 0x4 #define GC_FUSE_STATUS_READ_DONE_SIZE 0x1 #define GC_FUSE_STATUS_READ_DONE_DEFAULT 0x0 #define GC_FUSE_STATUS_READ_DONE_OFFSET 0x0 -#define GC_FUSE_STATUS_B0_VALID_LSB 0x1 -#define GC_FUSE_STATUS_B0_VALID_MASK 0x2 -#define GC_FUSE_STATUS_B0_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B0_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B0_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B1_VALID_LSB 0x2 -#define GC_FUSE_STATUS_B1_VALID_MASK 0x4 -#define GC_FUSE_STATUS_B1_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B1_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B1_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B2_VALID_LSB 0x3 -#define GC_FUSE_STATUS_B2_VALID_MASK 0x8 -#define GC_FUSE_STATUS_B2_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B2_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B2_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B3_VALID_LSB 0x4 -#define GC_FUSE_STATUS_B3_VALID_MASK 0x10 -#define GC_FUSE_STATUS_B3_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B3_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B3_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_LSB 0x5 -#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_MASK 0x20 -#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B0_DEFAULTS_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_LSB 0x6 -#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_MASK 0x40 -#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B1_DEFAULTS_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_LSB 0x7 -#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_MASK 0x80 -#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B2_DEFAULTS_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_LSB 0x8 -#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_MASK 0x100 -#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_SIZE 0x1 -#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_DEFAULT 0x0 -#define GC_FUSE_STATUS_B3_DEFAULTS_VALID_OFFSET 0x0 -#define GC_FUSE_STATUS_WRITE_DONE_LSB 0x10 -#define GC_FUSE_STATUS_WRITE_DONE_MASK 0x10000 -#define GC_FUSE_STATUS_WRITE_DONE_SIZE 0x1 -#define GC_FUSE_STATUS_WRITE_DONE_DEFAULT 0x0 -#define GC_FUSE_STATUS_WRITE_DONE_OFFSET 0x0 -#define GC_FUSE_STATUS_SCRUB_BUSY_LSB 0x1c -#define GC_FUSE_STATUS_SCRUB_BUSY_MASK 0x10000000 -#define GC_FUSE_STATUS_SCRUB_BUSY_SIZE 0x1 -#define GC_FUSE_STATUS_SCRUB_BUSY_DEFAULT 0x0 -#define GC_FUSE_STATUS_SCRUB_BUSY_OFFSET 0x0 -#define GC_FUSE_STATUS_READ_BUSY_LSB 0x1d -#define GC_FUSE_STATUS_READ_BUSY_MASK 0x20000000 -#define GC_FUSE_STATUS_READ_BUSY_SIZE 0x1 -#define GC_FUSE_STATUS_READ_BUSY_DEFAULT 0x0 -#define GC_FUSE_STATUS_READ_BUSY_OFFSET 0x0 -#define GC_FUSE_STATUS_WRITE_BUSY_LSB 0x1e -#define GC_FUSE_STATUS_WRITE_BUSY_MASK 0x40000000 -#define GC_FUSE_STATUS_WRITE_BUSY_SIZE 0x1 -#define GC_FUSE_STATUS_WRITE_BUSY_DEFAULT 0x0 -#define GC_FUSE_STATUS_WRITE_BUSY_OFFSET 0x0 -#define GC_FUSE_STATUS_BUSY_LSB 0x1f -#define GC_FUSE_STATUS_BUSY_MASK 0x80000000 +#define GC_FUSE_STATUS_READ_DONE_ERR_LSB 0x3 +#define GC_FUSE_STATUS_READ_DONE_ERR_MASK 0x8 +#define GC_FUSE_STATUS_READ_DONE_ERR_SIZE 0x1 +#define GC_FUSE_STATUS_READ_DONE_ERR_DEFAULT 0x0 +#define GC_FUSE_STATUS_READ_DONE_ERR_OFFSET 0x0 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_LSB 0x4 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_MASK 0x10 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_SIZE 0x1 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_DEFAULT 0x0 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_OFFSET 0x0 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_LSB 0x5 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_MASK 0x20 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_SIZE 0x1 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_DEFAULT 0x0 +#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_OFFSET 0x0 +#define GC_FUSE_STATUS_OVERRIDE_DONE_LSB 0x6 +#define GC_FUSE_STATUS_OVERRIDE_DONE_MASK 0x40 +#define GC_FUSE_STATUS_OVERRIDE_DONE_SIZE 0x1 +#define GC_FUSE_STATUS_OVERRIDE_DONE_DEFAULT 0x0 +#define GC_FUSE_STATUS_OVERRIDE_DONE_OFFSET 0x0 +#define GC_FUSE_STATUS_BUSY_LSB 0x7 +#define GC_FUSE_STATUS_BUSY_MASK 0x80 #define GC_FUSE_STATUS_BUSY_SIZE 0x1 #define GC_FUSE_STATUS_BUSY_DEFAULT 0x0 #define GC_FUSE_STATUS_BUSY_OFFSET 0x0 -#define GC_FUSE_STATUS_CLR_CLR_DONE_LSB 0x0 -#define GC_FUSE_STATUS_CLR_CLR_DONE_MASK 0x1 -#define GC_FUSE_STATUS_CLR_CLR_DONE_SIZE 0x1 -#define GC_FUSE_STATUS_CLR_CLR_DONE_DEFAULT 0x0 -#define GC_FUSE_STATUS_CLR_CLR_DONE_OFFSET 0x4 -#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_LSB 0x0 -#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_MASK 0xffffff -#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_SIZE 0x18 -#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_DEFAULT 0xffff -#define GC_FUSE_SCRUB_CTRL_IDLE_TIMING_OFFSET 0x14 -#define GC_FUSE_SCRUB_CTRL_DISABLE_LSB 0x1c -#define GC_FUSE_SCRUB_CTRL_DISABLE_MASK 0xf0000000 -#define GC_FUSE_SCRUB_CTRL_DISABLE_SIZE 0x4 -#define GC_FUSE_SCRUB_CTRL_DISABLE_DEFAULT 0x0 -#define GC_FUSE_SCRUB_CTRL_DISABLE_OFFSET 0x14 -#define GC_FUSE_SCRUB_CTRL_DISABLE_ENABLE 0x0 -#define GC_FUSE_SCRUB_CTRL_DISABLE_DISABLE 0x0 -#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_LSB 0x0 -#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_MASK 0x1 -#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_SIZE 0x1 -#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_DEFAULT 0x0 -#define GC_FUSE_ERROR_INJECTION_INJECT_CRC_ERR_OFFSET 0x18 -#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_LSB 0x1 -#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_MASK 0x2 -#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_SIZE 0x1 -#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_DEFAULT 0x0 -#define GC_FUSE_ERROR_INJECTION_INJECT_COMP_ERR_OFFSET 0x18 +#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_LSB 0x0 +#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_MASK 0x1 +#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_SIZE 0x1 +#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_DEFAULT 0x0 +#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_OFFSET 0x10 #define GC_FUSE_VERSION_CHANGE_LSB 0x0 #define GC_FUSE_VERSION_CHANGE_MASK 0xffffff #define GC_FUSE_VERSION_CHANGE_SIZE 0x18 -#define GC_FUSE_VERSION_CHANGE_DEFAULT 0x10240 -#define GC_FUSE_VERSION_CHANGE_OFFSET 0x20 +#define GC_FUSE_VERSION_CHANGE_DEFAULT 0x11cd4 +#define GC_FUSE_VERSION_CHANGE_OFFSET 0x28 #define GC_FUSE_VERSION_REVISION_LSB 0x18 #define GC_FUSE_VERSION_REVISION_MASK 0xff000000 #define GC_FUSE_VERSION_REVISION_SIZE 0x8 -#define GC_FUSE_VERSION_REVISION_DEFAULT 0x3 -#define GC_FUSE_VERSION_REVISION_OFFSET 0x20 -#define GC_FUSE_INT_ENABLE_READ_FINISHED_LSB 0x0 -#define GC_FUSE_INT_ENABLE_READ_FINISHED_MASK 0x1 -#define GC_FUSE_INT_ENABLE_READ_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_ENABLE_READ_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_ENABLE_READ_FINISHED_OFFSET 0x24 -#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_LSB 0x1 -#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_MASK 0x2 -#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_ENABLE_WRITE_FINISHED_OFFSET 0x24 -#define GC_FUSE_INT_STATE_READ_FINISHED_LSB 0x0 -#define GC_FUSE_INT_STATE_READ_FINISHED_MASK 0x1 -#define GC_FUSE_INT_STATE_READ_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_STATE_READ_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_STATE_READ_FINISHED_OFFSET 0x28 -#define GC_FUSE_INT_STATE_WRITE_FINISHED_LSB 0x1 -#define GC_FUSE_INT_STATE_WRITE_FINISHED_MASK 0x2 -#define GC_FUSE_INT_STATE_WRITE_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_STATE_WRITE_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_STATE_WRITE_FINISHED_OFFSET 0x28 -#define GC_FUSE_INT_TEST_READ_FINISHED_LSB 0x0 -#define GC_FUSE_INT_TEST_READ_FINISHED_MASK 0x1 -#define GC_FUSE_INT_TEST_READ_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_TEST_READ_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_TEST_READ_FINISHED_OFFSET 0x2c -#define GC_FUSE_INT_TEST_WRITE_FINISHED_LSB 0x1 -#define GC_FUSE_INT_TEST_WRITE_FINISHED_MASK 0x2 -#define GC_FUSE_INT_TEST_WRITE_FINISHED_SIZE 0x1 -#define GC_FUSE_INT_TEST_WRITE_FINISHED_DEFAULT 0x0 -#define GC_FUSE_INT_TEST_WRITE_FINISHED_OFFSET 0x2c -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_CPU0_I_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_DDMA0_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_ROM0_REGION0_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_ROM0_REGION0_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_DFLASH0_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_DSPS0_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_ROM0_REGION0_DUSB0_CTRL_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_LOCK_LSB 0xe -#define GC_GLOBALSEC_ROM0_REGION0_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_ROM0_REGION0_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_ROM0_REGION0_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_LOCK_OFFSET 0x0 -#define GC_GLOBALSEC_ROM0_REGION0_EN_LSB 0xf -#define GC_GLOBALSEC_ROM0_REGION0_EN_MASK 0x8000 -#define GC_GLOBALSEC_ROM0_REGION0_EN_SIZE 0x1 -#define GC_GLOBALSEC_ROM0_REGION0_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_ROM0_REGION0_EN_OFFSET 0x0 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_CPU0_I_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_DDMA0_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_SRAM0_REGION0_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_SRAM0_REGION0_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_DFLASH0_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_DSPS0_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION0_DUSB0_CTRL_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_LSB 0xe -#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM0_REGION0_LOCK_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION0_EN_LSB 0xf -#define GC_GLOBALSEC_SRAM0_REGION0_EN_MASK 0x8000 -#define GC_GLOBALSEC_SRAM0_REGION0_EN_SIZE 0x1 -#define GC_GLOBALSEC_SRAM0_REGION0_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_SRAM0_REGION0_EN_OFFSET 0x4 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_CPU0_I_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_DDMA0_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_SRAM0_REGION1_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_DFLASH0_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_DSPS0_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM0_REGION1_DUSB0_CTRL_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_LSB 0xe -#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM0_REGION1_LOCK_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM0_REGION1_EN_LSB 0xf -#define GC_GLOBALSEC_SRAM0_REGION1_EN_MASK 0x8000 -#define GC_GLOBALSEC_SRAM0_REGION1_EN_SIZE 0x1 -#define GC_GLOBALSEC_SRAM0_REGION1_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_SRAM0_REGION1_EN_OFFSET 0x8 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_D_DAP_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_CPU0_I_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_DDMA0_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_SRAM1_REGION0_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_SRAM1_REGION0_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_DFLASH0_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_DSPS0_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION0_DUSB0_CTRL_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_LSB 0xe -#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM1_REGION0_LOCK_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION0_EN_LSB 0xf -#define GC_GLOBALSEC_SRAM1_REGION0_EN_MASK 0x8000 -#define GC_GLOBALSEC_SRAM1_REGION0_EN_SIZE 0x1 -#define GC_GLOBALSEC_SRAM1_REGION0_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_SRAM1_REGION0_EN_OFFSET 0xc -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_CPU0_I_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_DDMA0_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_SRAM1_REGION1_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_SRAM1_REGION1_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_DFLASH0_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_DSPS0_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_SRAM1_REGION1_DUSB0_CTRL_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_LSB 0xe -#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_SRAM1_REGION1_LOCK_OFFSET 0x10 -#define GC_GLOBALSEC_SRAM1_REGION1_EN_LSB 0xf -#define GC_GLOBALSEC_SRAM1_REGION1_EN_MASK 0x8000 -#define GC_GLOBALSEC_SRAM1_REGION1_EN_SIZE 0x1 -#define GC_GLOBALSEC_SRAM1_REGION1_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_SRAM1_REGION1_EN_OFFSET 0x10 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_CPU0_I_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_DDMA0_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH0_REGION0_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH0_REGION0_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_DFLASH0_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_DSPS0_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION0_DUSB0_CTRL_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION0_LOCK_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION0_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH0_REGION0_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH0_REGION0_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION0_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH0_REGION0_EN_OFFSET 0x14 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_CPU0_I_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_DDMA0_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH0_REGION1_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH0_REGION1_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_DFLASH0_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_DSPS0_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION1_DUSB0_CTRL_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION1_LOCK_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION1_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH0_REGION1_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH0_REGION1_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION1_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH0_REGION1_EN_OFFSET 0x18 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_D_DAP_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_CPU0_I_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_DDMA0_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH0_REGION2_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH0_REGION2_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_DFLASH0_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_DSPS0_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION2_DUSB0_CTRL_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION2_LOCK_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION2_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH0_REGION2_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH0_REGION2_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION2_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH0_REGION2_EN_OFFSET 0x1c -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_D_DAP_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_CPU0_I_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_DDMA0_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH0_REGION3_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH0_REGION3_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_DFLASH0_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_DSPS0_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH0_REGION3_DUSB0_CTRL_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH0_REGION3_LOCK_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH0_REGION3_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH0_REGION3_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH0_REGION3_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH0_REGION3_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH0_REGION3_EN_OFFSET 0x20 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_D_DAP_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_CPU0_I_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_DDMA0_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH1_REGION0_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH1_REGION0_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_DFLASH0_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_DSPS0_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION0_DUSB0_CTRL_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION0_LOCK_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION0_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH1_REGION0_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH1_REGION0_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION0_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH1_REGION0_EN_OFFSET 0x24 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_D_DAP_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_CPU0_I_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_DDMA0_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH1_REGION1_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH1_REGION1_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_DFLASH0_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_DSPS0_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION1_DUSB0_CTRL_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION1_LOCK_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION1_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH1_REGION1_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH1_REGION1_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION1_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH1_REGION1_EN_OFFSET 0x28 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_D_DAP_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_CPU0_I_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_DDMA0_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH1_REGION2_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH1_REGION2_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_DFLASH0_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_DSPS0_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION2_DUSB0_CTRL_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION2_LOCK_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION2_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH1_REGION2_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH1_REGION2_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION2_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH1_REGION2_EN_OFFSET 0x2c -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_LSB 0x0 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_MASK 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_LSB 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_MASK 0xc -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_D_DAP_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_LSB 0x4 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_MASK 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_CPU0_I_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_LSB 0x6 -#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_MASK 0xc0 -#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_DDMA0_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_DFLASH0_CTRL_LSB 0x8 -#define GC_GLOBALSEC_FLASH1_REGION3_DFLASH0_CTRL_MASK 0x300 -#define GC_GLOBALSEC_FLASH1_REGION3_DFLASH0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_DFLASH0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_DFLASH0_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_LSB 0xa -#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_MASK 0xc00 -#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_DSPS0_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_LSB 0xc -#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_MASK 0x3000 -#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_SIZE 0x2 -#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_DEFAULT 0x3 -#define GC_GLOBALSEC_FLASH1_REGION3_DUSB0_CTRL_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_LSB 0xe -#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_MASK 0x4000 -#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_DEFAULT 0x0 -#define GC_GLOBALSEC_FLASH1_REGION3_LOCK_OFFSET 0x30 -#define GC_GLOBALSEC_FLASH1_REGION3_EN_LSB 0xf -#define GC_GLOBALSEC_FLASH1_REGION3_EN_MASK 0x8000 -#define GC_GLOBALSEC_FLASH1_REGION3_EN_SIZE 0x1 -#define GC_GLOBALSEC_FLASH1_REGION3_EN_DEFAULT 0x1 -#define GC_GLOBALSEC_FLASH1_REGION3_EN_OFFSET 0x30 +#define GC_FUSE_VERSION_REVISION_DEFAULT 0xf +#define GC_FUSE_VERSION_REVISION_OFFSET 0x28 +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_OFFSET 0x2c +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_OFFSET 0x30 +#define GC_FUSE_DS_GRP0_VAL_LSB 0x0 +#define GC_FUSE_DS_GRP0_VAL_MASK 0x1ff +#define GC_FUSE_DS_GRP0_VAL_SIZE 0x9 +#define GC_FUSE_DS_GRP0_VAL_DEFAULT 0x0 +#define GC_FUSE_DS_GRP0_VAL_OFFSET 0x34 +#define GC_FUSE_DS_GRP1_VAL_LSB 0x0 +#define GC_FUSE_DS_GRP1_VAL_MASK 0x1ff +#define GC_FUSE_DS_GRP1_VAL_SIZE 0x9 +#define GC_FUSE_DS_GRP1_VAL_DEFAULT 0x0 +#define GC_FUSE_DS_GRP1_VAL_OFFSET 0x38 +#define GC_FUSE_DS_GRP2_VAL_LSB 0x0 +#define GC_FUSE_DS_GRP2_VAL_MASK 0x1ff +#define GC_FUSE_DS_GRP2_VAL_SIZE 0x9 +#define GC_FUSE_DS_GRP2_VAL_DEFAULT 0x0 +#define GC_FUSE_DS_GRP2_VAL_OFFSET 0x3c +#define GC_FUSE_DEV_ID0_VAL_LSB 0x0 +#define GC_FUSE_DEV_ID0_VAL_MASK 0xffffffff +#define GC_FUSE_DEV_ID0_VAL_SIZE 0x20 +#define GC_FUSE_DEV_ID0_VAL_DEFAULT 0x0 +#define GC_FUSE_DEV_ID0_VAL_OFFSET 0x40 +#define GC_FUSE_DEV_ID1_VAL_LSB 0x0 +#define GC_FUSE_DEV_ID1_VAL_MASK 0xffffffff +#define GC_FUSE_DEV_ID1_VAL_SIZE 0x20 +#define GC_FUSE_DEV_ID1_VAL_DEFAULT 0x0 +#define GC_FUSE_DEV_ID1_VAL_OFFSET 0x44 +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_OFFSET 0x48 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_OFFSET 0x4c +#define GC_FUSE_LB0_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB0_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB0_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB0_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_OVRD_VAL_OFFSET 0x50 +#define GC_FUSE_LB0_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_LB0_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_LB0_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_LB0_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_PATCNT_VAL_OFFSET 0x54 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x58 +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x5c +#define GC_FUSE_LB1_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB1_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB1_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB1_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_OVRD_VAL_OFFSET 0x60 +#define GC_FUSE_LB1_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_LB1_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_LB1_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_LB1_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_PATCNT_VAL_OFFSET 0x64 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x68 +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x6c +#define GC_FUSE_LB2_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB2_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB2_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB2_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_OVRD_VAL_OFFSET 0x70 +#define GC_FUSE_LB2_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_LB2_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_LB2_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_LB2_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_PATCNT_VAL_OFFSET 0x74 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x78 +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x7c +#define GC_FUSE_LB3_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB3_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB3_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB3_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_OVRD_VAL_OFFSET 0x80 +#define GC_FUSE_LB3_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_LB3_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_LB3_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_LB3_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_PATCNT_VAL_OFFSET 0x84 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x88 +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x8c +#define GC_FUSE_MBIST_POST_SEQ_VAL_LSB 0x0 +#define GC_FUSE_MBIST_POST_SEQ_VAL_MASK 0x1ffffff +#define GC_FUSE_MBIST_POST_SEQ_VAL_SIZE 0x19 +#define GC_FUSE_MBIST_POST_SEQ_VAL_DEFAULT 0x0 +#define GC_FUSE_MBIST_POST_SEQ_VAL_OFFSET 0x90 +#define GC_FUSE_LBIST_POST_SEQ_VAL_LSB 0x0 +#define GC_FUSE_LBIST_POST_SEQ_VAL_MASK 0xffff +#define GC_FUSE_LBIST_POST_SEQ_VAL_SIZE 0x10 +#define GC_FUSE_LBIST_POST_SEQ_VAL_DEFAULT 0x0 +#define GC_FUSE_LBIST_POST_SEQ_VAL_OFFSET 0x94 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_LSB 0x0 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_MASK 0x7 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_SIZE 0x3 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x98 +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_LSB 0x0 +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_MASK 0x7 +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_SIZE 0x3 +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x9c +#define GC_FUSE_TAP_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_TAP_DISABLE_VAL_MASK 0x7 +#define GC_FUSE_TAP_DISABLE_VAL_SIZE 0x3 +#define GC_FUSE_TAP_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_TAP_DISABLE_VAL_OFFSET 0xa0 +#define GC_FUSE_RNGBIST_AR_EN_VAL_LSB 0x0 +#define GC_FUSE_RNGBIST_AR_EN_VAL_MASK 0x7 +#define GC_FUSE_RNGBIST_AR_EN_VAL_SIZE 0x3 +#define GC_FUSE_RNGBIST_AR_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RNGBIST_AR_EN_VAL_OFFSET 0xa4 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_LSB 0x0 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_MASK 0x7 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_SIZE 0x3 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_OFFSET 0xa8 +#define GC_FUSE_PKG_ID_VAL_LSB 0x0 +#define GC_FUSE_PKG_ID_VAL_MASK 0x7 +#define GC_FUSE_PKG_ID_VAL_SIZE 0x3 +#define GC_FUSE_PKG_ID_VAL_DEFAULT 0x0 +#define GC_FUSE_PKG_ID_VAL_OFFSET 0xac +#define GC_FUSE_BIN_ID_VAL_LSB 0x0 +#define GC_FUSE_BIN_ID_VAL_MASK 0x7 +#define GC_FUSE_BIN_ID_VAL_SIZE 0x3 +#define GC_FUSE_BIN_ID_VAL_DEFAULT 0x0 +#define GC_FUSE_BIN_ID_VAL_OFFSET 0xb0 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0xb4 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0xb8 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0xbc +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0xc0 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0xc4 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0xc8 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_MASK 0x1f +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE 0x5 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0xcc +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_LSB 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_MASK 0x7 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_SIZE 0x3 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0xd0 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0xd4 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0xd8 +#define GC_FUSE_SEL_VREG_REG_EN_VAL_LSB 0x0 +#define GC_FUSE_SEL_VREG_REG_EN_VAL_MASK 0x7 +#define GC_FUSE_SEL_VREG_REG_EN_VAL_SIZE 0x3 +#define GC_FUSE_SEL_VREG_REG_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_SEL_VREG_REG_EN_VAL_OFFSET 0xdc +#define GC_FUSE_SEL_VREF_REG_VAL_LSB 0x0 +#define GC_FUSE_SEL_VREF_REG_VAL_MASK 0xf +#define GC_FUSE_SEL_VREF_REG_VAL_SIZE 0x4 +#define GC_FUSE_SEL_VREF_REG_VAL_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_REG_VAL_OFFSET 0xe0 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_LSB 0x0 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_MASK 0x7 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_SIZE 0x3 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_OFFSET 0xe4 +#define GC_FUSE_SEL_VREF_BATMON_VAL_LSB 0x0 +#define GC_FUSE_SEL_VREF_BATMON_VAL_MASK 0x7 +#define GC_FUSE_SEL_VREF_BATMON_VAL_SIZE 0x3 +#define GC_FUSE_SEL_VREF_BATMON_VAL_DEFAULT 0x0 +#define GC_FUSE_SEL_VREF_BATMON_VAL_OFFSET 0xe8 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_LSB 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_MASK 0x7 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_SIZE 0x3 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0xec +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_LSB 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_MASK 0xf +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_SIZE 0x4 +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_DEFAULT 0x0 +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_OFFSET 0xf0 +#define GC_FUSE_EXT_XTAL_PDB_VAL_LSB 0x0 +#define GC_FUSE_EXT_XTAL_PDB_VAL_MASK 0x3 +#define GC_FUSE_EXT_XTAL_PDB_VAL_SIZE 0x2 +#define GC_FUSE_EXT_XTAL_PDB_VAL_DEFAULT 0x0 +#define GC_FUSE_EXT_XTAL_PDB_VAL_OFFSET 0xf4 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_LSB 0x0 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_MASK 0x7 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE 0x3 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0xf8 +#define GC_FUSE_OBFUSCATION_EN_VAL_LSB 0x0 +#define GC_FUSE_OBFUSCATION_EN_VAL_MASK 0x7 +#define GC_FUSE_OBFUSCATION_EN_VAL_SIZE 0x3 +#define GC_FUSE_OBFUSCATION_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_OBFUSCATION_EN_VAL_OFFSET 0xfc +#define GC_FUSE_JITTER_CLK_EN_VAL_LSB 0x0 +#define GC_FUSE_JITTER_CLK_EN_VAL_MASK 0x7 +#define GC_FUSE_JITTER_CLK_EN_VAL_SIZE 0x3 +#define GC_FUSE_JITTER_CLK_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_JITTER_CLK_EN_VAL_OFFSET 0x100 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_LSB 0x0 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_MASK 0x7 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_OFFSET 0x104 +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_OFFSET 0x108 +#define GC_FUSE_BNK2_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK2_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK2_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK2_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK2_INTG_LOCK_VAL_OFFSET 0x10c +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_LSB 0x0 +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_MASK 0x7 +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_SIZE 0x3 +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_OFFSET 0x110 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_LSB 0x0 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_MASK 0x7 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_SIZE 0x3 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x114 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_LSB 0x0 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_MASK 0x7 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x118 +#define GC_FUSE_ALERT_RSP_CFG_VAL_LSB 0x0 +#define GC_FUSE_ALERT_RSP_CFG_VAL_MASK 0xff +#define GC_FUSE_ALERT_RSP_CFG_VAL_SIZE 0x8 +#define GC_FUSE_ALERT_RSP_CFG_VAL_DEFAULT 0x0 +#define GC_FUSE_ALERT_RSP_CFG_VAL_OFFSET 0x11c +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_OFFSET 0x120 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_OFFSET 0x124 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x128 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x12c +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x130 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x134 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x138 +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x13c +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x140 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x144 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x148 +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x14c +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x150 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x154 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB 0x0 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK 0x1 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x158 +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0 +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7 +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x15c +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_MASK 0xffff +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_SIZE 0x10 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x160 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_MASK 0xffff +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_SIZE 0x10 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x164 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_MASK 0xff +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x168 +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_MASK 0xffff +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_SIZE 0x10 +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x16c +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x170 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x174 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x178 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x17c +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x180 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x184 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x188 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x18c +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_LSB 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_MASK 0xff +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x190 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_MASK 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x194 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_MASK 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x198 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_MASK 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x19c +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_LSB 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_MASK 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x1a0 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x1a4 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_OFFSET 0x1a8 +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x1ac +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_OFFSET 0x1b0 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x1b4 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_OFFSET 0x1b8 +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x1bc +#define GC_FUSE_RBOX_POL_EC_RST_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_EC_RST_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_EC_RST_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_EC_RST_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_EC_RST_VAL_OFFSET 0x1c0 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_MASK 0x1 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_SIZE 0x1 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x1c4 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x1c8 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x1cc +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x1d0 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x1d4 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x1d8 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x1dc +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x1e0 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x1e4 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x1e8 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x1ec +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_MASK 0x3 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x1f0 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_MASK 0x3 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x1f4 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x1f8 +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_OFFSET 0x1fc +#define GC_FUSE_BNK4_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK4_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK4_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK4_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK4_INTG_LOCK_VAL_OFFSET 0x200 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x204 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x208 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x20c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x210 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x214 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x218 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x21c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x220 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x224 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_MASK 0xff +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_SIZE 0x8 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x228 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_LSB 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_MASK 0x7f +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_SIZE 0x7 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_DEFAULT 0x0 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x22c +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_OFFSET 0x230 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_OFFSET 0x234 +#define GC_FUSE_PROG_DS_GRP0_VAL_LSB 0x0 +#define GC_FUSE_PROG_DS_GRP0_VAL_MASK 0x1ff +#define GC_FUSE_PROG_DS_GRP0_VAL_SIZE 0x9 +#define GC_FUSE_PROG_DS_GRP0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP0_VAL_OFFSET 0x238 +#define GC_FUSE_PROG_DS_GRP1_VAL_LSB 0x0 +#define GC_FUSE_PROG_DS_GRP1_VAL_MASK 0x1ff +#define GC_FUSE_PROG_DS_GRP1_VAL_SIZE 0x9 +#define GC_FUSE_PROG_DS_GRP1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP1_VAL_OFFSET 0x23c +#define GC_FUSE_PROG_DS_GRP2_VAL_LSB 0x0 +#define GC_FUSE_PROG_DS_GRP2_VAL_MASK 0x1ff +#define GC_FUSE_PROG_DS_GRP2_VAL_SIZE 0x9 +#define GC_FUSE_PROG_DS_GRP2_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP2_VAL_OFFSET 0x240 +#define GC_FUSE_PROG_DEV_ID0_VAL_LSB 0x0 +#define GC_FUSE_PROG_DEV_ID0_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_DEV_ID0_VAL_SIZE 0x20 +#define GC_FUSE_PROG_DEV_ID0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DEV_ID0_VAL_OFFSET 0x244 +#define GC_FUSE_PROG_DEV_ID1_VAL_LSB 0x0 +#define GC_FUSE_PROG_DEV_ID1_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_DEV_ID1_VAL_SIZE 0x20 +#define GC_FUSE_PROG_DEV_ID1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DEV_ID1_VAL_OFFSET 0x248 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_OFFSET 0x24c +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_OFFSET 0x250 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_OFFSET 0x254 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_OFFSET 0x258 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x25c +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x260 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_OFFSET 0x264 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_OFFSET 0x268 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x26c +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x270 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_OFFSET 0x274 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_OFFSET 0x278 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x27c +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x280 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_OFFSET 0x284 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_OFFSET 0x288 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_MASK 0x7 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x28c +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_MASK 0x3 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x290 +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_LSB 0x0 +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_MASK 0x1ffffff +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_SIZE 0x19 +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_OFFSET 0x294 +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_LSB 0x0 +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_MASK 0xffff +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_SIZE 0x10 +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_OFFSET 0x298 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_LSB 0x0 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_MASK 0x7 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_SIZE 0x3 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x29c +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_LSB 0x0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_MASK 0x7 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_SIZE 0x3 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a0 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_MASK 0x7 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_SIZE 0x3 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_OFFSET 0x2a4 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_OFFSET 0x2a8 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_OFFSET 0x2ac +#define GC_FUSE_PROG_PKG_ID_VAL_LSB 0x0 +#define GC_FUSE_PROG_PKG_ID_VAL_MASK 0x7 +#define GC_FUSE_PROG_PKG_ID_VAL_SIZE 0x3 +#define GC_FUSE_PROG_PKG_ID_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_PKG_ID_VAL_OFFSET 0x2b0 +#define GC_FUSE_PROG_BIN_ID_VAL_LSB 0x0 +#define GC_FUSE_PROG_BIN_ID_VAL_MASK 0x7 +#define GC_FUSE_PROG_BIN_ID_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BIN_ID_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BIN_ID_VAL_OFFSET 0x2b4 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0x2b8 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0x2bc +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0x2c0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0x2c4 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0x2c8 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0x2cc +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_MASK 0x1f +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE 0x5 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0x2d0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0x2d4 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_MASK 0xff +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0x2d8 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0x2dc +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_OFFSET 0x2e0 +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_LSB 0x0 +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_MASK 0xf +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_SIZE 0x4 +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_OFFSET 0x2e4 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_OFFSET 0x2e8 +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_LSB 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_MASK 0x7 +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_SIZE 0x3 +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_OFFSET 0x2ec +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0x2f0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_LSB 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_MASK 0xf +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_SIZE 0x4 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_OFFSET 0x2f4 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_LSB 0x0 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_MASK 0x3 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_SIZE 0x2 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_OFFSET 0x2f8 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_LSB 0x0 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_MASK 0x7 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE 0x3 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0x2fc +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_OFFSET 0x300 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_OFFSET 0x304 +#define GC_FUSE_PROG_OBS0_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS0_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS0_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS0_VAL_OFFSET 0x308 +#define GC_FUSE_PROG_OBS1_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS1_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS1_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS1_VAL_OFFSET 0x30c +#define GC_FUSE_PROG_OBS2_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS2_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS2_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS2_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS2_VAL_OFFSET 0x310 +#define GC_FUSE_PROG_OBS3_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS3_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS3_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS3_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS3_VAL_OFFSET 0x314 +#define GC_FUSE_PROG_OBS4_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS4_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS4_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS4_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS4_VAL_OFFSET 0x318 +#define GC_FUSE_PROG_OBS5_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS5_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS5_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS5_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS5_VAL_OFFSET 0x31c +#define GC_FUSE_PROG_OBS6_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS6_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS6_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS6_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS6_VAL_OFFSET 0x320 +#define GC_FUSE_PROG_OBS7_VAL_LSB 0x0 +#define GC_FUSE_PROG_OBS7_VAL_MASK 0xffffffff +#define GC_FUSE_PROG_OBS7_VAL_SIZE 0x20 +#define GC_FUSE_PROG_OBS7_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_OBS7_VAL_OFFSET 0x324 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_OFFSET 0x328 +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_OFFSET 0x32c +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_OFFSET 0x330 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_LSB 0x0 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_MASK 0x7 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_SIZE 0x3 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_OFFSET 0x334 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_LSB 0x0 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_MASK 0x7 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_SIZE 0x3 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x338 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x33c +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_LSB 0x0 +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_MASK 0xff +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_SIZE 0x8 +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_OFFSET 0x340 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_OFFSET 0x344 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_OFFSET 0x348 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x34c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x350 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x354 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x358 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x35c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x360 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x364 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x368 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x36c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x370 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x374 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x378 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x37c +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x380 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_MASK 0xffff +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_SIZE 0x10 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x384 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_MASK 0xffff +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_SIZE 0x10 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x388 +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x38c +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_MASK 0xffff +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_SIZE 0x10 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x390 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x394 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x398 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x39c +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x3a0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x3a4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x3a8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x3ac +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x3b0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_MASK 0xff +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_SIZE 0x8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x3b4 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x3b8 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x3bc +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x3c0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x3c4 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x3c8 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_OFFSET 0x3cc +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x3d0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_OFFSET 0x3d4 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x3d8 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_OFFSET 0x3dc +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x3e0 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_OFFSET 0x3e4 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_MASK 0x1 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_SIZE 0x1 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x3e8 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x3ec +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x3f0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x3f4 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x3f8 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x3fc +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x400 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x404 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x408 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x40c +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x410 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x414 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x418 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_LSB 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x41c +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_MASK 0xffffff +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_SIZE 0x18 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_OFFSET 0x420 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_OFFSET 0x424 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x428 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x42c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x430 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x434 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x438 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x43c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x440 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x444 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x448 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_MASK 0xff +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_SIZE 0x8 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x44c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_LSB 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_MASK 0x7f +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_SIZE 0x7 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x450 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_OFFSET 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_OFFSET 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_OFFSET 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_OFFSET 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_OFFSET 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_OFFSET 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_OFFSET 0x8 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_OFFSET 0x8 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_OFFSET 0x8 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_OFFSET 0xc +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_OFFSET 0xc +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_OFFSET 0xc +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_OFFSET 0x10 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_OFFSET 0x10 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_OFFSET 0x10 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_OFFSET 0x14 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_OFFSET 0x14 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_OFFSET 0x14 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_OFFSET 0x18 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_OFFSET 0x18 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_OFFSET 0x18 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_OFFSET 0x1c +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_OFFSET 0x1c +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_DEFAULT 0x1 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_OFFSET 0x1c +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_OFFSET 0x20 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_OFFSET 0x20 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_OFFSET 0x20 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_OFFSET 0x24 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_OFFSET 0x24 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_OFFSET 0x24 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_OFFSET 0x28 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_OFFSET 0x28 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_OFFSET 0x28 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_OFFSET 0x2c +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_OFFSET 0x2c +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_OFFSET 0x2c +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_OFFSET 0x30 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_OFFSET 0x30 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_OFFSET 0x30 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_OFFSET 0x34 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_OFFSET 0x34 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_OFFSET 0x34 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_OFFSET 0x38 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_OFFSET 0x38 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_OFFSET 0x38 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_OFFSET 0x3c +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_OFFSET 0x3c +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_OFFSET 0x3c +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_OFFSET 0x40 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_OFFSET 0x40 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_OFFSET 0x40 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_OFFSET 0x44 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_OFFSET 0x44 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_OFFSET 0x44 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_OFFSET 0x48 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_OFFSET 0x48 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_OFFSET 0x48 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_OFFSET 0x4c +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_OFFSET 0x4c +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_OFFSET 0x4c +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_OFFSET 0x50 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_OFFSET 0x50 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_OFFSET 0x50 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_OFFSET 0x54 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_OFFSET 0x54 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_OFFSET 0x54 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_OFFSET 0x58 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_OFFSET 0x58 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_OFFSET 0x58 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_OFFSET 0x5c +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_OFFSET 0x5c +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_OFFSET 0x5c +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_OFFSET 0x60 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_OFFSET 0x60 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_OFFSET 0x60 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_OFFSET 0x64 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_OFFSET 0x64 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_OFFSET 0x64 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_OFFSET 0x68 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_OFFSET 0x68 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_OFFSET 0x68 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_OFFSET 0x6c +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_OFFSET 0x6c +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_OFFSET 0x6c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_OFFSET 0x1a4 #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_LSB 0x0 #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_MASK 0x1 #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_SIZE 0x1 @@ -7943,7 +9270,7 @@ #define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_MASK 0x1000000 #define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_SIZE 0x1 #define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_DEFAULT 0x0 -#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_OFFSET 0x1024 +#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_OFFSET 0x1028 #define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_LSB 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_MASK 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_SIZE 0x1 @@ -8029,103 +9356,138 @@ #define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_INTR_STS0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4004 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4004 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4008 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4008 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4008 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4008 -#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4008 -#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4008 @@ -8214,103 +9576,138 @@ #define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_NMI_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x400c -#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x400c +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4010 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4010 -#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4010 -#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4010 -#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4010 -#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4010 @@ -8399,103 +9796,138 @@ #define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPA_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4014 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4014 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4018 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4018 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4018 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4018 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4018 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4018 @@ -8584,103 +10016,138 @@ #define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPB_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x401c -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x401c +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4020 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4020 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4020 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4020 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4020 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4020 @@ -8769,103 +10236,138 @@ #define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4024 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4024 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_GROUPC_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4024 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4024 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4028 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4028 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4028 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4028 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4028 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4028 @@ -8954,103 +10456,138 @@ #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x402c +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x402c +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x402c -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x402c +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4030 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4030 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4030 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4030 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4030 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4030 @@ -9139,103 +10676,138 @@ #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4034 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4034 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4034 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4034 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4038 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4038 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4038 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4038 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4038 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4038 @@ -9324,103 +10896,138 @@ #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x11 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_LSB 0x12 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_LSB 0x13 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_LSB 0x14 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_LSB 0x15 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x16 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x400000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x17 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x800000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x18 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x1000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x19 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x2000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1a -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x4000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1b -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x8000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_LSB 0x1c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_MASK 0x10000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_LSB 0x1e +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1d -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_HKEY_ALERT_MASK 0x20000000 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_LSB 0x1e -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_MASK 0x40000000 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x1f -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x80000000 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x403c -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x0 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x403c +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4040 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4040 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x1 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x2 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4040 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x2 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x4 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4040 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0x3 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x8 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4040 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0x4 -#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x10 +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb +#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4040 @@ -9514,6 +11121,66 @@ #define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_SIZE 0x1 #define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0 #define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_LSB 0x12 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_MASK 0x40000 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_LSB 0x13 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_MASK 0x80000 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_LSB 0x14 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_MASK 0x100000 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_LSB 0x15 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_MASK 0x200000 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_SIZE 0x1 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_OFFSET 0x405c +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_LSB 0x0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_MASK 0x3 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_SIZE 0x2 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_DEFAULT 0x3 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_LSB 0x2 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_MASK 0xc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_SIZE 0x2 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_DEFAULT 0x3 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_LSB 0x4 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_MASK 0x10 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_SIZE 0x1 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_DEFAULT 0x0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_LSB 0x5 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_MASK 0x20 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_SIZE 0x1 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_DEFAULT 0x1 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_LSB 0x6 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_MASK 0x40 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_SIZE 0x1 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_DEFAULT 0x0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_OFFSET 0x40cc +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_LSB 0x7 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_MASK 0x380 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_SIZE 0x3 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_DEFAULT 0x0 +#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_OFFSET 0x40cc +#define GC_GLOBALSEC_VERSION_CHANGE_LSB 0x0 +#define GC_GLOBALSEC_VERSION_CHANGE_MASK 0xffffff +#define GC_GLOBALSEC_VERSION_CHANGE_SIZE 0x18 +#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT 0x11ff3 +#define GC_GLOBALSEC_VERSION_CHANGE_OFFSET 0x40d4 +#define GC_GLOBALSEC_VERSION_REVISION_LSB 0x18 +#define GC_GLOBALSEC_VERSION_REVISION_MASK 0xff000000 +#define GC_GLOBALSEC_VERSION_REVISION_SIZE 0x8 +#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT 0x26 +#define GC_GLOBALSEC_VERSION_REVISION_OFFSET 0x40d4 #define GC_I2C_CTRL_PHASESTEPS_P0_LSB 0x0 #define GC_I2C_CTRL_PHASESTEPS_P0_MASK 0x3f #define GC_I2C_CTRL_PHASESTEPS_P0_SIZE 0x6 @@ -10269,11 +11936,6 @@ #define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_SIZE 0x2 #define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_DEFAULT 0x3 #define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_OFFSET 0x60 -#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_VAL_LSB 0x0 -#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_VAL_MASK 0xffffffff -#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_VAL_SIZE 0x20 -#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_VAL_DEFAULT 0x0 -#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_VAL_OFFSET 0x78 #define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_LSB 0x0 #define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_MASK 0x1 #define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_SIZE 0x1 @@ -10413,22 +12075,22 @@ #define GC_KEYMGR_SHA_TRIG_TRIG_GO_MASK 0x1 #define GC_KEYMGR_SHA_TRIG_TRIG_GO_SIZE 0x1 #define GC_KEYMGR_SHA_TRIG_TRIG_GO_DEFAULT 0x0 -#define GC_KEYMGR_SHA_TRIG_TRIG_GO_OFFSET 0x40c -#define GC_KEYMGR_SHA_TRIG_TRIG_RESETN_LSB 0x1 -#define GC_KEYMGR_SHA_TRIG_TRIG_RESETN_MASK 0x2 -#define GC_KEYMGR_SHA_TRIG_TRIG_RESETN_SIZE 0x1 -#define GC_KEYMGR_SHA_TRIG_TRIG_RESETN_DEFAULT 0x1 -#define GC_KEYMGR_SHA_TRIG_TRIG_RESETN_OFFSET 0x40c -#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_LSB 0x3 -#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_MASK 0x8 +#define GC_KEYMGR_SHA_TRIG_TRIG_GO_OFFSET 0x410 +#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_LSB 0x1 +#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_MASK 0x2 +#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_SIZE 0x1 +#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_DEFAULT 0x0 +#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_OFFSET 0x410 +#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_LSB 0x2 +#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_MASK 0x4 #define GC_KEYMGR_SHA_TRIG_TRIG_STEP_SIZE 0x1 #define GC_KEYMGR_SHA_TRIG_TRIG_STEP_DEFAULT 0x0 -#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_OFFSET 0x40c -#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_LSB 0x4 -#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK 0x10 +#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_OFFSET 0x410 +#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_LSB 0x3 +#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK 0x8 #define GC_KEYMGR_SHA_TRIG_TRIG_STOP_SIZE 0x1 #define GC_KEYMGR_SHA_TRIG_TRIG_STOP_DEFAULT 0x0 -#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_OFFSET 0x40c +#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_OFFSET 0x410 #define GC_KEYMGR_SHA_STS_FIFO_EMPTY_LSB 0x0 #define GC_KEYMGR_SHA_STS_FIFO_EMPTY_MASK 0x1 #define GC_KEYMGR_SHA_STS_FIFO_EMPTY_SIZE 0x1 @@ -10489,6 +12151,206 @@ #define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_SIZE 0x2 #define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_DEFAULT 0x3 #define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_OFFSET 0x49c +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_LSB 0x0 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_MASK 0x3 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_LSB 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_MASK 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_LSB 0x4 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_MASK 0x30 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_LSB 0x6 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_MASK 0xc0 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_LSB 0x8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_MASK 0x300 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_LSB 0xa +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_MASK 0xc00 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_LSB 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_MASK 0x3000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_LSB 0xe +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_MASK 0xc000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_LSB 0x10 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_MASK 0x30000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_LSB 0x12 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_MASK 0xc0000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_LSB 0x14 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_MASK 0x300000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_LSB 0x16 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_MASK 0xc00000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_LSB 0x18 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_MASK 0x3000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_LSB 0x1a +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_MASK 0xc000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_LSB 0x1c +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_MASK 0x30000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_LSB 0x1e +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_MASK 0xc0000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_OFFSET 0x4a8 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_LSB 0x0 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_MASK 0x3 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_LSB 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_MASK 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_LSB 0x4 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_MASK 0x30 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_LSB 0x6 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_MASK 0xc0 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_LSB 0x8 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_MASK 0x300 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_LSB 0xa +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_MASK 0xc00 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_LSB 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_MASK 0x3000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_LSB 0xe +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_MASK 0xc000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_LSB 0x10 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_MASK 0x30000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_LSB 0x12 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_MASK 0xc0000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_LSB 0x14 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_MASK 0x300000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_LSB 0x16 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_MASK 0xc00000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_LSB 0x18 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_MASK 0x3000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_LSB 0x1a +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_MASK 0xc000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_LSB 0x1c +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_MASK 0x30000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_LSB 0x1e +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_MASK 0xc0000000 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_OFFSET 0x4ac +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_LSB 0x0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_MASK 0x3 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_LSB 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_MASK 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_LSB 0x4 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_MASK 0x30 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_LSB 0x6 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_MASK 0xc0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_LSB 0x8 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_MASK 0x300 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_LSB 0xa +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_MASK 0xc00 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_LSB 0xc +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_MASK 0x3000 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_OFFSET 0x4b0 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_LSB 0xe +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_MASK 0xc000 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_SIZE 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_DEFAULT 0x2 +#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_OFFSET 0x4b0 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_LSB 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_MASK 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_SIZE 0x1 @@ -10519,61 +12381,86 @@ #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_LSB 0x6 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_MASK 0x40 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_LSB 0x6 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_MASK 0x40 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_SIZE 0x1 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_LSB 0x7 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_MASK 0x80 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_LSB 0x7 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_MASK 0x80 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_LSB 0x8 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_MASK 0x100 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_LSB 0x8 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_MASK 0x100 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_LSB 0x9 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_MASK 0x200 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_LSB 0x9 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_MASK 0x200 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_LSB 0xa +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_MASK 0x400 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_LSB 0xa -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_MASK 0x400 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_LSB 0xb +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_MASK 0x800 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_LSB 0xb -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_MASK 0x800 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_LSB 0xc +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_MASK 0x1000 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_LSB 0xc -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_MASK 0x1000 +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_LSB 0xd +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_MASK 0x2000 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_LSB 0xd -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_MASK 0x2000 +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_LSB 0xe +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_MASK 0x4000 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_LSB 0xe -#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_MASK 0x4000 +#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_LSB 0xf +#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_MASK 0x8000 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_LSB 0xf -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_MASK 0x8000 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_LSB 0x10 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_MASK 0x10000 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_OFFSET 0x3320 -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_LSB 0x10 -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_MASK 0x10000 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_LSB 0x11 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_MASK 0x20000 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_LSB 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_MASK 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_SIZE 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_LSB 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_MASK 0x2 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_SIZE 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_LSB 0x2 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_MASK 0x4 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_SIZE 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_LSB 0x3 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_MASK 0x8 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_SIZE 0x1 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_OFFSET 0x3324 #define GC_MAU_EN_SYSIBUS_LSB 0x0 #define GC_MAU_EN_SYSIBUS_MASK 0x1 #define GC_MAU_EN_SYSIBUS_SIZE 0x1 @@ -11379,736 +13266,536 @@ #define GC_PINMUX_RESETB_CTL_INV_SIZE 0x1 #define GC_PINMUX_RESETB_CTL_INV_DEFAULT 0x0 #define GC_PINMUX_RESETB_CTL_INV_OFFSET 0xf4 -#define GC_PINMUX_TRSTN_CTL_DS_LSB 0x0 -#define GC_PINMUX_TRSTN_CTL_DS_MASK 0x3 -#define GC_PINMUX_TRSTN_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TRSTN_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TRSTN_CTL_DS_OFFSET 0xfc -#define GC_PINMUX_TRSTN_CTL_IE_LSB 0x2 -#define GC_PINMUX_TRSTN_CTL_IE_MASK 0x4 -#define GC_PINMUX_TRSTN_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TRSTN_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TRSTN_CTL_IE_OFFSET 0xfc -#define GC_PINMUX_TRSTN_CTL_PD_LSB 0x3 -#define GC_PINMUX_TRSTN_CTL_PD_MASK 0x8 -#define GC_PINMUX_TRSTN_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TRSTN_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TRSTN_CTL_PD_OFFSET 0xfc -#define GC_PINMUX_TRSTN_CTL_PU_LSB 0x4 -#define GC_PINMUX_TRSTN_CTL_PU_MASK 0x10 -#define GC_PINMUX_TRSTN_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TRSTN_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TRSTN_CTL_PU_OFFSET 0xfc -#define GC_PINMUX_TRSTN_CTL_INV_LSB 0x5 -#define GC_PINMUX_TRSTN_CTL_INV_MASK 0x20 -#define GC_PINMUX_TRSTN_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TRSTN_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TRSTN_CTL_INV_OFFSET 0xfc -#define GC_PINMUX_TDI_CTL_DS_LSB 0x0 -#define GC_PINMUX_TDI_CTL_DS_MASK 0x3 -#define GC_PINMUX_TDI_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TDI_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TDI_CTL_DS_OFFSET 0x104 -#define GC_PINMUX_TDI_CTL_IE_LSB 0x2 -#define GC_PINMUX_TDI_CTL_IE_MASK 0x4 -#define GC_PINMUX_TDI_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TDI_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_IE_OFFSET 0x104 -#define GC_PINMUX_TDI_CTL_PD_LSB 0x3 -#define GC_PINMUX_TDI_CTL_PD_MASK 0x8 -#define GC_PINMUX_TDI_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TDI_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_PD_OFFSET 0x104 -#define GC_PINMUX_TDI_CTL_PU_LSB 0x4 -#define GC_PINMUX_TDI_CTL_PU_MASK 0x10 -#define GC_PINMUX_TDI_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TDI_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_PU_OFFSET 0x104 -#define GC_PINMUX_TDI_CTL_INV_LSB 0x5 -#define GC_PINMUX_TDI_CTL_INV_MASK 0x20 -#define GC_PINMUX_TDI_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TDI_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TDI_CTL_INV_OFFSET 0x104 -#define GC_PINMUX_TMS_CTL_DS_LSB 0x0 -#define GC_PINMUX_TMS_CTL_DS_MASK 0x3 -#define GC_PINMUX_TMS_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TMS_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TMS_CTL_DS_OFFSET 0x10c -#define GC_PINMUX_TMS_CTL_IE_LSB 0x2 -#define GC_PINMUX_TMS_CTL_IE_MASK 0x4 -#define GC_PINMUX_TMS_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TMS_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_IE_OFFSET 0x10c -#define GC_PINMUX_TMS_CTL_PD_LSB 0x3 -#define GC_PINMUX_TMS_CTL_PD_MASK 0x8 -#define GC_PINMUX_TMS_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TMS_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_PD_OFFSET 0x10c -#define GC_PINMUX_TMS_CTL_PU_LSB 0x4 -#define GC_PINMUX_TMS_CTL_PU_MASK 0x10 -#define GC_PINMUX_TMS_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TMS_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_PU_OFFSET 0x10c -#define GC_PINMUX_TMS_CTL_INV_LSB 0x5 -#define GC_PINMUX_TMS_CTL_INV_MASK 0x20 -#define GC_PINMUX_TMS_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TMS_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TMS_CTL_INV_OFFSET 0x10c -#define GC_PINMUX_TCK_CTL_DS_LSB 0x0 -#define GC_PINMUX_TCK_CTL_DS_MASK 0x3 -#define GC_PINMUX_TCK_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TCK_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TCK_CTL_DS_OFFSET 0x114 -#define GC_PINMUX_TCK_CTL_IE_LSB 0x2 -#define GC_PINMUX_TCK_CTL_IE_MASK 0x4 -#define GC_PINMUX_TCK_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TCK_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_IE_OFFSET 0x114 -#define GC_PINMUX_TCK_CTL_PD_LSB 0x3 -#define GC_PINMUX_TCK_CTL_PD_MASK 0x8 -#define GC_PINMUX_TCK_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TCK_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_PD_OFFSET 0x114 -#define GC_PINMUX_TCK_CTL_PU_LSB 0x4 -#define GC_PINMUX_TCK_CTL_PU_MASK 0x10 -#define GC_PINMUX_TCK_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TCK_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_PU_OFFSET 0x114 -#define GC_PINMUX_TCK_CTL_INV_LSB 0x5 -#define GC_PINMUX_TCK_CTL_INV_MASK 0x20 -#define GC_PINMUX_TCK_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TCK_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TCK_CTL_INV_OFFSET 0x114 -#define GC_PINMUX_TDO_CTL_DS_LSB 0x0 -#define GC_PINMUX_TDO_CTL_DS_MASK 0x3 -#define GC_PINMUX_TDO_CTL_DS_SIZE 0x2 -#define GC_PINMUX_TDO_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_TDO_CTL_DS_OFFSET 0x11c -#define GC_PINMUX_TDO_CTL_IE_LSB 0x2 -#define GC_PINMUX_TDO_CTL_IE_MASK 0x4 -#define GC_PINMUX_TDO_CTL_IE_SIZE 0x1 -#define GC_PINMUX_TDO_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_IE_OFFSET 0x11c -#define GC_PINMUX_TDO_CTL_PD_LSB 0x3 -#define GC_PINMUX_TDO_CTL_PD_MASK 0x8 -#define GC_PINMUX_TDO_CTL_PD_SIZE 0x1 -#define GC_PINMUX_TDO_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_PD_OFFSET 0x11c -#define GC_PINMUX_TDO_CTL_PU_LSB 0x4 -#define GC_PINMUX_TDO_CTL_PU_MASK 0x10 -#define GC_PINMUX_TDO_CTL_PU_SIZE 0x1 -#define GC_PINMUX_TDO_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_PU_OFFSET 0x11c -#define GC_PINMUX_TDO_CTL_INV_LSB 0x5 -#define GC_PINMUX_TDO_CTL_INV_MASK 0x20 -#define GC_PINMUX_TDO_CTL_INV_SIZE 0x1 -#define GC_PINMUX_TDO_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_TDO_CTL_INV_OFFSET 0x11c #define GC_PINMUX_VIO0_CTL_DS_LSB 0x0 #define GC_PINMUX_VIO0_CTL_DS_MASK 0x3 #define GC_PINMUX_VIO0_CTL_DS_SIZE 0x2 #define GC_PINMUX_VIO0_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_VIO0_CTL_DS_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_DS_OFFSET 0xfc #define GC_PINMUX_VIO0_CTL_IE_LSB 0x2 #define GC_PINMUX_VIO0_CTL_IE_MASK 0x4 #define GC_PINMUX_VIO0_CTL_IE_SIZE 0x1 #define GC_PINMUX_VIO0_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_IE_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_IE_OFFSET 0xfc #define GC_PINMUX_VIO0_CTL_PD_LSB 0x3 #define GC_PINMUX_VIO0_CTL_PD_MASK 0x8 #define GC_PINMUX_VIO0_CTL_PD_SIZE 0x1 #define GC_PINMUX_VIO0_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_PD_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_PD_OFFSET 0xfc #define GC_PINMUX_VIO0_CTL_PU_LSB 0x4 #define GC_PINMUX_VIO0_CTL_PU_MASK 0x10 #define GC_PINMUX_VIO0_CTL_PU_SIZE 0x1 #define GC_PINMUX_VIO0_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_PU_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_PU_OFFSET 0xfc #define GC_PINMUX_VIO0_CTL_INV_LSB 0x5 #define GC_PINMUX_VIO0_CTL_INV_MASK 0x20 #define GC_PINMUX_VIO0_CTL_INV_SIZE 0x1 #define GC_PINMUX_VIO0_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_VIO0_CTL_INV_OFFSET 0x124 +#define GC_PINMUX_VIO0_CTL_INV_OFFSET 0xfc #define GC_PINMUX_VIO1_CTL_DS_LSB 0x0 #define GC_PINMUX_VIO1_CTL_DS_MASK 0x3 #define GC_PINMUX_VIO1_CTL_DS_SIZE 0x2 #define GC_PINMUX_VIO1_CTL_DS_DEFAULT 0x3 -#define GC_PINMUX_VIO1_CTL_DS_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_DS_OFFSET 0x104 #define GC_PINMUX_VIO1_CTL_IE_LSB 0x2 #define GC_PINMUX_VIO1_CTL_IE_MASK 0x4 #define GC_PINMUX_VIO1_CTL_IE_SIZE 0x1 #define GC_PINMUX_VIO1_CTL_IE_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_IE_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_IE_OFFSET 0x104 #define GC_PINMUX_VIO1_CTL_PD_LSB 0x3 #define GC_PINMUX_VIO1_CTL_PD_MASK 0x8 #define GC_PINMUX_VIO1_CTL_PD_SIZE 0x1 #define GC_PINMUX_VIO1_CTL_PD_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_PD_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_PD_OFFSET 0x104 #define GC_PINMUX_VIO1_CTL_PU_LSB 0x4 #define GC_PINMUX_VIO1_CTL_PU_MASK 0x10 #define GC_PINMUX_VIO1_CTL_PU_SIZE 0x1 #define GC_PINMUX_VIO1_CTL_PU_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_PU_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_PU_OFFSET 0x104 #define GC_PINMUX_VIO1_CTL_INV_LSB 0x5 #define GC_PINMUX_VIO1_CTL_INV_MASK 0x20 #define GC_PINMUX_VIO1_CTL_INV_SIZE 0x1 #define GC_PINMUX_VIO1_CTL_INV_DEFAULT 0x0 -#define GC_PINMUX_VIO1_CTL_INV_OFFSET 0x12c +#define GC_PINMUX_VIO1_CTL_INV_OFFSET 0x104 #define GC_PINMUX_EXITEN0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITEN0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEN0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEN0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEN0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEN0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEN0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEN0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEN0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEN0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEN0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEN0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEN0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEN0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEN0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEN0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEN0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEN0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEN0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEN0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEN0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEN0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEN0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEN0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEN0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEN0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEN0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEN0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEN0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEN0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEN0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEN0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEN0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEN0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEN0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEN0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEN0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEN0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEN0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEN0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEN0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEN0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEN0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEN0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEN0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEN0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEN0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEN0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEN0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEN0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEN0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEN0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEN0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEN0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEN0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x238 #define GC_PINMUX_EXITEN0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEN0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEN0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x238 #define GC_PINMUX_EXITEN0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITEN0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITEN0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITEN0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_SWDPTRACE_OFFSET 0x260 +#define GC_PINMUX_EXITEN0_SWDPTRACE_OFFSET 0x238 #define GC_PINMUX_EXITEN0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITEN0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITEN0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITEN0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_SWDPDATA_OFFSET 0x260 -#define GC_PINMUX_EXITEN0_TRSTN_LSB 0x1e -#define GC_PINMUX_EXITEN0_TRSTN_MASK 0x40000000 -#define GC_PINMUX_EXITEN0_TRSTN_SIZE 0x1 -#define GC_PINMUX_EXITEN0_TRSTN_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_TRSTN_OFFSET 0x260 -#define GC_PINMUX_EXITEN0_TDI_LSB 0x1f -#define GC_PINMUX_EXITEN0_TDI_MASK 0x80000000 -#define GC_PINMUX_EXITEN0_TDI_SIZE 0x1 -#define GC_PINMUX_EXITEN0_TDI_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_TDI_OFFSET 0x260 -#define GC_PINMUX_EXITEN1_TMS_LSB 0x0 -#define GC_PINMUX_EXITEN1_TMS_MASK 0x1 -#define GC_PINMUX_EXITEN1_TMS_SIZE 0x1 -#define GC_PINMUX_EXITEN1_TMS_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_TMS_OFFSET 0x264 -#define GC_PINMUX_EXITEN1_TCK_LSB 0x1 -#define GC_PINMUX_EXITEN1_TCK_MASK 0x2 -#define GC_PINMUX_EXITEN1_TCK_SIZE 0x1 -#define GC_PINMUX_EXITEN1_TCK_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_TCK_OFFSET 0x264 -#define GC_PINMUX_EXITEN1_TDO_LSB 0x2 -#define GC_PINMUX_EXITEN1_TDO_MASK 0x4 -#define GC_PINMUX_EXITEN1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITEN1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_TDO_OFFSET 0x264 +#define GC_PINMUX_EXITEN0_SWDPDATA_OFFSET 0x238 #define GC_PINMUX_EXITEN1_VIO0_LSB 0x3 #define GC_PINMUX_EXITEN1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEN1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x23c #define GC_PINMUX_EXITEN1_VIO1_LSB 0x4 #define GC_PINMUX_EXITEN1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEN1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x264 +#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITEDGE0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEDGE0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEDGE0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEDGE0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEDGE0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEDGE0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEDGE0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEDGE0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEDGE0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEDGE0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEDGE0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEDGE0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEDGE0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEDGE0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEDGE0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEDGE0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEDGE0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEDGE0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEDGE0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEDGE0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEDGE0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEDGE0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEDGE0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEDGE0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEDGE0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEDGE0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEDGE0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEDGE0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEDGE0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEDGE0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEDGE0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEDGE0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEDGE0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEDGE0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEDGE0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEDGE0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEDGE0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEDGE0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEDGE0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEDGE0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEDGE0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEDGE0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEDGE0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEDGE0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEDGE0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEDGE0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEDGE0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEDGE0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEDGE0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEDGE0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEDGE0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEDGE0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEDGE0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEDGE0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITEDGE0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITEDGE0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_SWDPTRACE_OFFSET 0x268 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_OFFSET 0x240 #define GC_PINMUX_EXITEDGE0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITEDGE0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITEDGE0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_SWDPDATA_OFFSET 0x268 -#define GC_PINMUX_EXITEDGE0_TRSTN_LSB 0x1e -#define GC_PINMUX_EXITEDGE0_TRSTN_MASK 0x40000000 -#define GC_PINMUX_EXITEDGE0_TRSTN_SIZE 0x1 -#define GC_PINMUX_EXITEDGE0_TRSTN_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_TRSTN_OFFSET 0x268 -#define GC_PINMUX_EXITEDGE0_TDI_LSB 0x1f -#define GC_PINMUX_EXITEDGE0_TDI_MASK 0x80000000 -#define GC_PINMUX_EXITEDGE0_TDI_SIZE 0x1 -#define GC_PINMUX_EXITEDGE0_TDI_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_TDI_OFFSET 0x268 -#define GC_PINMUX_EXITEDGE1_TMS_LSB 0x0 -#define GC_PINMUX_EXITEDGE1_TMS_MASK 0x1 -#define GC_PINMUX_EXITEDGE1_TMS_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_TMS_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_TMS_OFFSET 0x26c -#define GC_PINMUX_EXITEDGE1_TCK_LSB 0x1 -#define GC_PINMUX_EXITEDGE1_TCK_MASK 0x2 -#define GC_PINMUX_EXITEDGE1_TCK_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_TCK_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_TCK_OFFSET 0x26c -#define GC_PINMUX_EXITEDGE1_TDO_LSB 0x2 -#define GC_PINMUX_EXITEDGE1_TDO_MASK 0x4 -#define GC_PINMUX_EXITEDGE1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITEDGE1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_TDO_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE0_SWDPDATA_OFFSET 0x240 #define GC_PINMUX_EXITEDGE1_VIO0_LSB 0x3 #define GC_PINMUX_EXITEDGE1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEDGE1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x244 #define GC_PINMUX_EXITEDGE1_VIO1_LSB 0x4 #define GC_PINMUX_EXITEDGE1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEDGE1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x26c +#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITINV0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITINV0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITINV0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITINV0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITINV0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITINV0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITINV0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITINV0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITINV0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITINV0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITINV0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITINV0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITINV0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITINV0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITINV0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITINV0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITINV0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITINV0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITINV0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITINV0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA5_LSB 0xa #define GC_PINMUX_EXITINV0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITINV0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA6_LSB 0xb #define GC_PINMUX_EXITINV0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITINV0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA7_LSB 0xc #define GC_PINMUX_EXITINV0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITINV0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA8_LSB 0xd #define GC_PINMUX_EXITINV0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITINV0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA9_LSB 0xe #define GC_PINMUX_EXITINV0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITINV0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA10_LSB 0xf #define GC_PINMUX_EXITINV0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITINV0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITINV0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITINV0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITINV0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITINV0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITINV0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITINV0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITINV0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITINV0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITINV0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITINV0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITINV0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITINV0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITINV0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITINV0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITINV0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITINV0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITINV0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITINV0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITINV0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITINV0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITINV0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITINV0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x248 #define GC_PINMUX_EXITINV0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITINV0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITINV0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x248 #define GC_PINMUX_EXITINV0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITINV0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITINV0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITINV0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_SWDPTRACE_OFFSET 0x270 +#define GC_PINMUX_EXITINV0_SWDPTRACE_OFFSET 0x248 #define GC_PINMUX_EXITINV0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITINV0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITINV0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITINV0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_SWDPDATA_OFFSET 0x270 -#define GC_PINMUX_EXITINV0_TRSTN_LSB 0x1e -#define GC_PINMUX_EXITINV0_TRSTN_MASK 0x40000000 -#define GC_PINMUX_EXITINV0_TRSTN_SIZE 0x1 -#define GC_PINMUX_EXITINV0_TRSTN_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_TRSTN_OFFSET 0x270 -#define GC_PINMUX_EXITINV0_TDI_LSB 0x1f -#define GC_PINMUX_EXITINV0_TDI_MASK 0x80000000 -#define GC_PINMUX_EXITINV0_TDI_SIZE 0x1 -#define GC_PINMUX_EXITINV0_TDI_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_TDI_OFFSET 0x270 -#define GC_PINMUX_EXITINV1_TMS_LSB 0x0 -#define GC_PINMUX_EXITINV1_TMS_MASK 0x1 -#define GC_PINMUX_EXITINV1_TMS_SIZE 0x1 -#define GC_PINMUX_EXITINV1_TMS_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_TMS_OFFSET 0x274 -#define GC_PINMUX_EXITINV1_TCK_LSB 0x1 -#define GC_PINMUX_EXITINV1_TCK_MASK 0x2 -#define GC_PINMUX_EXITINV1_TCK_SIZE 0x1 -#define GC_PINMUX_EXITINV1_TCK_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_TCK_OFFSET 0x274 -#define GC_PINMUX_EXITINV1_TDO_LSB 0x2 -#define GC_PINMUX_EXITINV1_TDO_MASK 0x4 -#define GC_PINMUX_EXITINV1_TDO_SIZE 0x1 -#define GC_PINMUX_EXITINV1_TDO_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_TDO_OFFSET 0x274 +#define GC_PINMUX_EXITINV0_SWDPDATA_OFFSET 0x248 #define GC_PINMUX_EXITINV1_VIO0_LSB 0x3 #define GC_PINMUX_EXITINV1_VIO0_MASK 0x8 #define GC_PINMUX_EXITINV1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x24c #define GC_PINMUX_EXITINV1_VIO1_LSB 0x4 #define GC_PINMUX_EXITINV1_VIO1_MASK 0x10 #define GC_PINMUX_EXITINV1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x274 +#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x24c #define GC_PMU_RESET_PORESETB1_LSB 0x0 #define GC_PMU_RESET_PORESETB1_MASK 0x1 #define GC_PMU_RESET_PORESETB1_SIZE 0x1 @@ -12294,51 +13981,46 @@ #define GC_PMU_CLRWIC_PROC0_SIZE 0x1 #define GC_PMU_CLRWIC_PROC0_DEFAULT 0x0 #define GC_PMU_CLRWIC_PROC0_OFFSET 0x24 -#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_LSB 0x0 -#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_MASK 0x1 -#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_SIZE 0x1 -#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_DEFAULT 0x0 -#define GC_PMU_MODEL_FPGA_TRNG_LDO_PDB_3P3_OFFSET 0x30 #define GC_PMU_SW_PDB_TIMER_RC_LSB 0x0 #define GC_PMU_SW_PDB_TIMER_RC_MASK 0x1 #define GC_PMU_SW_PDB_TIMER_RC_SIZE 0x1 #define GC_PMU_SW_PDB_TIMER_RC_DEFAULT 0x0 -#define GC_PMU_SW_PDB_TIMER_RC_OFFSET 0x34 +#define GC_PMU_SW_PDB_TIMER_RC_OFFSET 0x30 #define GC_PMU_SW_PDB_FST_BRNOUT_PWR_LSB 0x1 #define GC_PMU_SW_PDB_FST_BRNOUT_PWR_MASK 0x2 #define GC_PMU_SW_PDB_FST_BRNOUT_PWR_SIZE 0x1 #define GC_PMU_SW_PDB_FST_BRNOUT_PWR_DEFAULT 0x0 -#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_OFFSET 0x34 +#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_OFFSET 0x30 #define GC_PMU_SW_PDB_FST_BRNOUT_LSB 0x2 #define GC_PMU_SW_PDB_FST_BRNOUT_MASK 0x4 #define GC_PMU_SW_PDB_FST_BRNOUT_SIZE 0x1 #define GC_PMU_SW_PDB_FST_BRNOUT_DEFAULT 0x0 -#define GC_PMU_SW_PDB_FST_BRNOUT_OFFSET 0x34 +#define GC_PMU_SW_PDB_FST_BRNOUT_OFFSET 0x30 #define GC_PMU_SW_PDB_SECURE_BATMON_LSB 0x0 #define GC_PMU_SW_PDB_SECURE_BATMON_MASK 0x1 #define GC_PMU_SW_PDB_SECURE_BATMON_SIZE 0x1 #define GC_PMU_SW_PDB_SECURE_BATMON_DEFAULT 0x0 -#define GC_PMU_SW_PDB_SECURE_BATMON_OFFSET 0x38 +#define GC_PMU_SW_PDB_SECURE_BATMON_OFFSET 0x34 #define GC_PMU_SW_PDB_SECURE_XTL_LSB 0x1 #define GC_PMU_SW_PDB_SECURE_XTL_MASK 0x2 #define GC_PMU_SW_PDB_SECURE_XTL_SIZE 0x1 #define GC_PMU_SW_PDB_SECURE_XTL_DEFAULT 0x0 -#define GC_PMU_SW_PDB_SECURE_XTL_OFFSET 0x38 +#define GC_PMU_SW_PDB_SECURE_XTL_OFFSET 0x34 #define GC_PMU_VREF_REG_LSB 0x0 #define GC_PMU_VREF_REG_MASK 0xf #define GC_PMU_VREF_REG_SIZE 0x4 #define GC_PMU_VREF_REG_DEFAULT 0xb -#define GC_PMU_VREF_REG_OFFSET 0x3c +#define GC_PMU_VREF_REG_OFFSET 0x38 #define GC_PMU_VREF_LDOXO_LSB 0x4 #define GC_PMU_VREF_LDOXO_MASK 0xf0 #define GC_PMU_VREF_LDOXO_SIZE 0x4 #define GC_PMU_VREF_LDOXO_DEFAULT 0xf -#define GC_PMU_VREF_LDOXO_OFFSET 0x3c +#define GC_PMU_VREF_LDOXO_OFFSET 0x38 #define GC_PMU_VREF_BATMON_LSB 0x8 #define GC_PMU_VREF_BATMON_MASK 0x700 #define GC_PMU_VREF_BATMON_SIZE 0x3 #define GC_PMU_VREF_BATMON_DEFAULT 0x0 -#define GC_PMU_VREF_BATMON_OFFSET 0x3c +#define GC_PMU_VREF_BATMON_OFFSET 0x38 #define GC_PMU_VREF_BATMON_V1P9 0x2 #define GC_PMU_VREF_BATMON_V1P8 0x1 #define GC_PMU_VREF_BATMON_V1P7 0x0 @@ -12527,1021 +14209,921 @@ #define GC_PMU_PERICLKSET0_DCAMO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DCAMO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DCAMO0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_LSB 0x1 -#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_MASK 0x2 -#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_DEFAULT 0x1 -#define GC_PMU_PERICLKSET0_DCAMO0_CLK_RTC_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_LSB 0x2 -#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_MASK 0x4 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_LSB 0x1 +#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_MASK 0x2 #define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DDMA0_CLK_LSB 0x3 -#define GC_PMU_PERICLKSET0_DDMA0_CLK_MASK 0x8 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_LSB 0x2 +#define GC_PMU_PERICLKSET0_DDMA0_CLK_MASK 0x4 #define GC_PMU_PERICLKSET0_DDMA0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DDMA0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DDMA0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DFLASH0_CLK_LSB 0x4 -#define GC_PMU_PERICLKSET0_DFLASH0_CLK_MASK 0x10 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_LSB 0x3 +#define GC_PMU_PERICLKSET0_DFLASH0_CLK_MASK 0x8 #define GC_PMU_PERICLKSET0_DFLASH0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DFLASH0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DFLASH0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DFUSE0_CLK_LSB 0x5 -#define GC_PMU_PERICLKSET0_DFUSE0_CLK_MASK 0x20 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_LSB 0x4 +#define GC_PMU_PERICLKSET0_DFUSE0_CLK_MASK 0x10 #define GC_PMU_PERICLKSET0_DFUSE0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DFUSE0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DFUSE0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_LSB 0x6 -#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_MASK 0x40 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_LSB 0x5 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_MASK 0x20 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_LSB 0x6 +#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB 0x8 -#define GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK 0x100 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB 0x7 +#define GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK 0x80 #define GC_PMU_PERICLKSET0_DGPIO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DGPIO0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DGPIO0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB 0x9 -#define GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK 0x200 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB 0x8 +#define GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK 0x100 #define GC_PMU_PERICLKSET0_DGPIO1_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DGPIO1_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DGPIO1_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_LSB 0xa -#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_MASK 0x400 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_MASK 0x200 #define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_LSB 0xb -#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_LSB 0xa +#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_MASK 0x400 #define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DI2CS0_CLK_LSB 0xc -#define GC_PMU_PERICLKSET0_DI2CS0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_LSB 0xb +#define GC_PMU_PERICLKSET0_DI2CS0_CLK_MASK 0x800 #define GC_PMU_PERICLKSET0_DI2CS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DI2CS0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DI2CS0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_LSB 0xd -#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_LSB 0xc +#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_MASK 0x1000 #define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DMAU_CLK_LSB 0xe -#define GC_PMU_PERICLKSET0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERICLKSET0_DMAU_CLK_LSB 0xd +#define GC_PMU_PERICLKSET0_DMAU_CLK_MASK 0x2000 #define GC_PMU_PERICLKSET0_DMAU_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DMAU_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DMAU_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_LSB 0xf -#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_LSB 0xe +#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_MASK 0x4000 #define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_LSB 0x10 -#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_LSB 0xf +#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_MASK 0x8000 #define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_LSB 0x11 -#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_LSB 0x10 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_MASK 0x10000 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_LSB 0x11 +#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPINMUX_CLK_LSB 0x13 -#define GC_PMU_PERICLKSET0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_LSB 0x12 +#define GC_PMU_PERICLKSET0_DPINMUX_CLK_MASK 0x40000 #define GC_PMU_PERICLKSET0_DPINMUX_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPINMUX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPINMUX_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DPMU_CLK_LSB 0x14 -#define GC_PMU_PERICLKSET0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERICLKSET0_DPMU_CLK_LSB 0x13 +#define GC_PMU_PERICLKSET0_DPMU_CLK_MASK 0x80000 #define GC_PMU_PERICLKSET0_DPMU_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DPMU_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DPMU_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_LSB 0x15 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_LSB 0x14 +#define GC_PMU_PERICLKSET0_DRBOX0_CLK_MASK 0x100000 #define GC_PMU_PERICLKSET0_DRBOX0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DRBOX0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DRBOX0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_LSB 0x16 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_MASK 0x400000 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERICLKSET0_DRBOX0_CLK_RTC_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DRDD0_CLK_LSB 0x17 -#define GC_PMU_PERICLKSET0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_LSB 0x15 +#define GC_PMU_PERICLKSET0_DRDD0_CLK_MASK 0x200000 #define GC_PMU_PERICLKSET0_DRDD0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DRDD0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET0_DRDD0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_LSB 0x18 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_LSB 0x16 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_MASK 0x400000 #define GC_PMU_PERICLKSET0_DRTC0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DRTC0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_LSB 0x19 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_LSB 0x17 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_MASK 0x800000 #define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_LSB 0x1a -#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_MASK 0x4000000 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_LSB 0x18 +#define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_MASK 0x1000000 #define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DSPI0_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_LSB 0x1b -#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_MASK 0x2000000 #define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DSPI1_CLK_TIMER_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DSPS0_CLK_LSB 0x1c -#define GC_PMU_PERICLKSET0_DSPS0_CLK_MASK 0x10000000 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_LSB 0x1a +#define GC_PMU_PERICLKSET0_DSPS0_CLK_MASK 0x4000000 #define GC_PMU_PERICLKSET0_DSPS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DSPS0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DSPS0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_LSB 0x1d -#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_LSB 0x1b +#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_MASK 0x8000000 #define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DSWDP0_CLK_LSB 0x1e -#define GC_PMU_PERICLKSET0_DSWDP0_CLK_MASK 0x40000000 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_LSB 0x1c +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_MASK 0x10000000 #define GC_PMU_PERICLKSET0_DSWDP0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DSWDP0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DSWDP0_CLK_OFFSET 0x60 -#define GC_PMU_PERICLKSET0_DTEMP0_CLK_LSB 0x1f -#define GC_PMU_PERICLKSET0_DTEMP0_CLK_MASK 0x80000000 +#define GC_PMU_PERICLKSET0_DTEMP0_CLK_LSB 0x1d +#define GC_PMU_PERICLKSET0_DTEMP0_CLK_MASK 0x20000000 #define GC_PMU_PERICLKSET0_DTEMP0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET0_DTEMP0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET0_DTEMP0_CLK_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DTIMEHS0_CLK_TIMER_LSB 0x1e +#define GC_PMU_PERICLKSET0_DTIMEHS0_CLK_TIMER_MASK 0x40000000 +#define GC_PMU_PERICLKSET0_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTIMEHS0_CLK_TIMER_OFFSET 0x60 +#define GC_PMU_PERICLKSET0_DTIMEHS1_CLK_TIMER_LSB 0x1f +#define GC_PMU_PERICLKSET0_DTIMEHS1_CLK_TIMER_MASK 0x80000000 +#define GC_PMU_PERICLKSET0_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKSET0_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET0_DTIMEHS1_CLK_TIMER_OFFSET 0x60 #define GC_PMU_PERICLKCLR0_DCAMO0_CLK_LSB 0x0 #define GC_PMU_PERICLKCLR0_DCAMO0_CLK_MASK 0x1 #define GC_PMU_PERICLKCLR0_DCAMO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DCAMO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DCAMO0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_LSB 0x1 -#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_MASK 0x2 -#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_RTC_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_LSB 0x2 -#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_MASK 0x4 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_LSB 0x1 +#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_MASK 0x2 #define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DDMA0_CLK_LSB 0x3 -#define GC_PMU_PERICLKCLR0_DDMA0_CLK_MASK 0x8 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_LSB 0x2 +#define GC_PMU_PERICLKCLR0_DDMA0_CLK_MASK 0x4 #define GC_PMU_PERICLKCLR0_DDMA0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DDMA0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DDMA0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_LSB 0x4 -#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_MASK 0x10 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_LSB 0x3 +#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_MASK 0x8 #define GC_PMU_PERICLKCLR0_DFLASH0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DFLASH0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DFLASH0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_LSB 0x5 -#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_MASK 0x20 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_LSB 0x4 +#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_MASK 0x10 #define GC_PMU_PERICLKCLR0_DFUSE0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DFUSE0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DFUSE0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_LSB 0x6 -#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_MASK 0x40 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_LSB 0x5 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_MASK 0x20 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x6 +#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_LSB 0x8 -#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_MASK 0x100 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_LSB 0x7 +#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_MASK 0x80 #define GC_PMU_PERICLKCLR0_DGPIO0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DGPIO0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DGPIO0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_LSB 0x9 -#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_MASK 0x200 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_LSB 0x8 +#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_MASK 0x100 #define GC_PMU_PERICLKCLR0_DGPIO1_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DGPIO1_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DGPIO1_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_LSB 0xa -#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_MASK 0x400 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_MASK 0x200 #define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_LSB 0xb -#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_LSB 0xa +#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_MASK 0x400 #define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_LSB 0xc -#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_LSB 0xb +#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_MASK 0x800 #define GC_PMU_PERICLKCLR0_DI2CS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DI2CS0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DI2CS0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_LSB 0xd -#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_LSB 0xc +#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_MASK 0x1000 #define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DMAU_CLK_LSB 0xe -#define GC_PMU_PERICLKCLR0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERICLKCLR0_DMAU_CLK_LSB 0xd +#define GC_PMU_PERICLKCLR0_DMAU_CLK_MASK 0x2000 #define GC_PMU_PERICLKCLR0_DMAU_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DMAU_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DMAU_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_LSB 0xf -#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_LSB 0xe +#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_MASK 0x4000 #define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_LSB 0x10 -#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_LSB 0xf +#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_MASK 0x8000 #define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_LSB 0x11 -#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_LSB 0x10 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_MASK 0x10000 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_LSB 0x11 +#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_LSB 0x13 -#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_LSB 0x12 +#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_MASK 0x40000 #define GC_PMU_PERICLKCLR0_DPINMUX_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPINMUX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPINMUX_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DPMU_CLK_LSB 0x14 -#define GC_PMU_PERICLKCLR0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_LSB 0x13 +#define GC_PMU_PERICLKCLR0_DPMU_CLK_MASK 0x80000 #define GC_PMU_PERICLKCLR0_DPMU_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DPMU_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DPMU_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_LSB 0x15 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_LSB 0x14 +#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_MASK 0x100000 #define GC_PMU_PERICLKCLR0_DRBOX0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DRBOX0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DRBOX0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_LSB 0x16 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_MASK 0x400000 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_RTC_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DRDD0_CLK_LSB 0x17 -#define GC_PMU_PERICLKCLR0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_LSB 0x15 +#define GC_PMU_PERICLKCLR0_DRDD0_CLK_MASK 0x200000 #define GC_PMU_PERICLKCLR0_DRDD0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DRDD0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR0_DRDD0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_LSB 0x18 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_LSB 0x16 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_MASK 0x400000 #define GC_PMU_PERICLKCLR0_DRTC0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DRTC0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_LSB 0x19 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_LSB 0x17 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_MASK 0x800000 #define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_LSB 0x1a -#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_MASK 0x4000000 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_LSB 0x18 +#define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_MASK 0x1000000 #define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DSPI0_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_LSB 0x1b -#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_MASK 0x2000000 #define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DSPI1_CLK_TIMER_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DSPS0_CLK_LSB 0x1c -#define GC_PMU_PERICLKCLR0_DSPS0_CLK_MASK 0x10000000 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_LSB 0x1a +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_MASK 0x4000000 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1d -#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1b +#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_MASK 0x8000000 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_LSB 0x1e -#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_MASK 0x40000000 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_LSB 0x1c +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_MASK 0x10000000 #define GC_PMU_PERICLKCLR0_DSWDP0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DSWDP0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_LSB 0x1f -#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_MASK 0x80000000 +#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_LSB 0x1d +#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_MASK 0x20000000 #define GC_PMU_PERICLKCLR0_DTEMP0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR0_DTEMP0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR0_DTEMP0_CLK_OFFSET 0x64 -#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_LSB 0x0 -#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_MASK 0x1 -#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_LSB 0x1 -#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_MASK 0x2 -#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_LSB 0x2 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_MASK 0x4 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_CLK_TIMER_LSB 0x1e +#define GC_PMU_PERICLKCLR0_DTIMEHS0_CLK_TIMER_MASK 0x40000000 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTIMEHS0_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_CLK_TIMER_LSB 0x1f +#define GC_PMU_PERICLKCLR0_DTIMEHS1_CLK_TIMER_MASK 0x80000000 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR0_DTIMEHS1_CLK_TIMER_OFFSET 0x64 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_LSB 0x0 +#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_MASK 0x1 #define GC_PMU_PERICLKSET1_DTIMELS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_DTIMELS0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DTIMELS0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_LSB 0x3 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_MASK 0x8 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_RTC_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_LSB 0x4 -#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_MASK 0x10 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_MASK 0x2 #define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DTRNG0_CLK_LSB 0x5 -#define GC_PMU_PERICLKSET1_DTRNG0_CLK_MASK 0x20 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_LSB 0x2 +#define GC_PMU_PERICLKSET1_DTRNG0_CLK_MASK 0x4 #define GC_PMU_PERICLKSET1_DTRNG0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_DTRNG0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DTRNG0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_LSB 0x6 -#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_MASK 0x40 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_LSB 0x3 +#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_MASK 0x8 #define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_LSB 0x4 +#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_MASK 0x10 #define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_LSB 0x8 -#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_MASK 0x20 #define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DUSB0_CLK_LSB 0x9 -#define GC_PMU_PERICLKSET1_DUSB0_CLK_MASK 0x200 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_LSB 0x6 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_MASK 0x40 #define GC_PMU_PERICLKSET1_DUSB0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_DUSB0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DUSB0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_LSB 0xa -#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_MASK 0x400 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_LSB 0x7 +#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_MASK 0x80 #define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DVOLT0_CLK_LSB 0xb -#define GC_PMU_PERICLKSET1_DVOLT0_CLK_MASK 0x800 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_LSB 0x8 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_MASK 0x100 #define GC_PMU_PERICLKSET1_DVOLT0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_DVOLT0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DVOLT0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_LSB 0xc -#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_LSB 0x9 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_MASK 0x200 #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DXO0_CLK_LSB 0xd -#define GC_PMU_PERICLKSET1_DXO0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKSET1_DXO0_CLK_LSB 0xa +#define GC_PMU_PERICLKSET1_DXO0_CLK_MASK 0x400 #define GC_PMU_PERICLKSET1_DXO0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DXO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DXO0_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_LSB 0xe -#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_MASK 0x4000 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_MASK 0x800 #define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_LSB 0xf -#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_MASK 0x8000 +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_LSB 0xc +#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_MASK 0x1000 #define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_LSB 0x10 -#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_LSB 0xd +#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_MASK 0x2000 #define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_LSB 0x11 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_MASK 0x20000 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_DEFAULT 0x1 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_OFFSET 0x68 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_MASK 0x40000 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x1 -#define GC_PMU_PERICLKSET1_SEC_FABRIC_CLK_TIMER_OFFSET 0x68 -#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_LSB 0x0 -#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_MASK 0x1 -#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_LSB 0x1 -#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_MASK 0x2 -#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_LSB 0x2 -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_MASK 0x4 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_LSB 0x0 +#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_MASK 0x1 #define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_LSB 0x3 -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_MASK 0x8 -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_RTC_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_LSB 0x4 -#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_MASK 0x10 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_MASK 0x2 #define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_LSB 0x5 -#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_MASK 0x20 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_LSB 0x2 +#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_MASK 0x4 #define GC_PMU_PERICLKCLR1_DTRNG0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DTRNG0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DTRNG0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_LSB 0x6 -#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_MASK 0x40 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_LSB 0x3 +#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_MASK 0x8 #define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_LSB 0x4 +#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_MASK 0x10 #define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_LSB 0x8 -#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_MASK 0x20 #define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DUSB0_CLK_LSB 0x9 -#define GC_PMU_PERICLKCLR1_DUSB0_CLK_MASK 0x200 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_LSB 0x6 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_MASK 0x40 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_LSB 0xa -#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_MASK 0x400 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_LSB 0x7 +#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_MASK 0x80 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_LSB 0xb -#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_MASK 0x800 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_LSB 0x8 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_MASK 0x100 #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_LSB 0xc -#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_MASK 0x1000 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_LSB 0x9 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_MASK 0x200 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_DEFAULT 0x0 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DXO0_CLK_LSB 0xd -#define GC_PMU_PERICLKCLR1_DXO0_CLK_MASK 0x2000 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_LSB 0xa +#define GC_PMU_PERICLKCLR1_DXO0_CLK_MASK 0x400 #define GC_PMU_PERICLKCLR1_DXO0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DXO0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DXO0_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_LSB 0xe -#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_MASK 0x4000 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_MASK 0x800 #define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xf -#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x8000 +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xc +#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x1000 #define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_LSB 0x10 -#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_LSB 0xd +#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_MASK 0x2000 #define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_LSB 0x11 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_MASK 0x20000 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_OFFSET 0x6c -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_MASK 0x40000 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x1 -#define GC_PMU_PERICLKCLR1_SEC_FABRIC_CLK_TIMER_OFFSET 0x6c #define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_LSB 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_MASK 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_RTC_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_MASK 0x2 #define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_MASK 0x4 #define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_MASK 0x8 #define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_MASK 0x10 #define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_MASK 0x20 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_MASK 0x80 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_MASK 0x100 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_MASK 0x200 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_MASK 0x400 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_MASK 0x800 #define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_MASK 0x1000 #define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_MASK 0x2000 #define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DMAU_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_MASK 0x4000 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_MASK 0x8000 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_MASK 0x10000 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_LSB 0x13 -#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_MASK 0x40000 #define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_LSB 0x14 -#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_MASK 0x80000 #define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_LSB 0x15 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_MASK 0x100000 #define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_LSB 0x16 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_MASK 0x400000 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_RTC_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_LSB 0x17 -#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_MASK 0x200000 #define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_LSB 0x18 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_MASK 0x400000 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_LSB 0x19 -#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_MASK 0x800000 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_LSB 0x1a -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_MASK 0x1000000 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_LSB 0x1b -#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_MASK 0x2000000 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_TIMER_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_LSB 0x1c -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_MASK 0x4000000 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_LSB 0x1d -#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_MASK 0x8000000 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_LSB 0x1e -#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_MASK 0x10000000 #define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_OFFSET 0x70 -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_LSB 0x1f -#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_MASK 0x20000000 #define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_CLK_TIMER_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_CLK_TIMER_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS0_CLK_TIMER_OFFSET 0x70 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_CLK_TIMER_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_CLK_TIMER_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPSET0_DTIMEHS1_CLK_TIMER_OFFSET 0x70 #define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_LSB 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_MASK 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_RTC_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_MASK 0x2 #define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_MASK 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_MASK 0x4 #define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_MASK 0x8 #define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_MASK 0x10 #define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_MASK 0x20 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_MASK 0x80 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_MASK 0x100 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_MASK 0x200 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_MASK 0x400 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_MASK 0x800 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_MASK 0x1000 #define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_MASK 0x2000 #define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DMAU_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_LSB 0xe +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_MASK 0x4000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_LSB 0xf +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_MASK 0x8000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_MASK 0x20000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_LSB 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_MASK 0x10000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_LSB 0x11 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_LSB 0x13 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_MASK 0x80000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_LSB 0x12 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_MASK 0x40000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_LSB 0x14 -#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_MASK 0x100000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_LSB 0x13 +#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_MASK 0x80000 #define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_LSB 0x15 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_MASK 0x200000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_LSB 0x14 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_MASK 0x100000 #define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_LSB 0x16 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_MASK 0x400000 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_RTC_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_LSB 0x17 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_MASK 0x800000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_LSB 0x15 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_MASK 0x200000 #define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_LSB 0x18 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_MASK 0x1000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_LSB 0x16 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_MASK 0x400000 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_LSB 0x19 -#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_MASK 0x2000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_LSB 0x17 +#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_MASK 0x800000 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_LSB 0x1a -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_MASK 0x4000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_LSB 0x18 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_MASK 0x1000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_LSB 0x1b -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_LSB 0x19 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_MASK 0x2000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_TIMER_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_LSB 0x1c -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_MASK 0x10000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_LSB 0x1a +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_MASK 0x4000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1d -#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1b +#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_MASK 0x8000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_LSB 0x1e -#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_LSB 0x1c +#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_MASK 0x10000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_LSB 0x1f -#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_LSB 0x1d +#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_MASK 0x20000000 #define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_OFFSET 0x74 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_CLK_TIMER_LSB 0x1e +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_CLK_TIMER_MASK 0x40000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS0_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_CLK_TIMER_LSB 0x1f +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_CLK_TIMER_MASK 0x80000000 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR0_DTIMEHS1_CLK_TIMER_OFFSET 0x74 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_MASK 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_MASK 0x8 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_RTC_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_MASK 0x2 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_MASK 0x4 #define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_MASK 0x8 #define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_MASK 0x10 #define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_MASK 0x20 #define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_MASK 0x40 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_MASK 0x80 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_MASK 0x100 #define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_MASK 0x200 #define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_MASK 0x400 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_MASK 0x800 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_MASK 0x1000 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_MASK 0x2000 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_MASK 0x20000 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_MASK 0x40000 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPSET1_SEC_FABRIC_CLK_TIMER_OFFSET 0x78 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_LSB 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_MASK 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_LSB 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_MASK 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_LSB 0x2 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_MASK 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_LSB 0x0 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_MASK 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_LSB 0x3 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_MASK 0x8 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_RTC_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_LSB 0x4 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_MASK 0x10 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_MASK 0x2 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_LSB 0x5 -#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_MASK 0x20 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_LSB 0x2 +#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_MASK 0x4 #define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_LSB 0x6 -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_MASK 0x40 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_LSB 0x3 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_MASK 0x8 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_LSB 0x7 -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_MASK 0x80 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_LSB 0x4 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_MASK 0x10 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_LSB 0x8 -#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_MASK 0x100 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_LSB 0x5 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_MASK 0x20 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_LSB 0x9 -#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_MASK 0x200 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_LSB 0x6 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_MASK 0x40 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_LSB 0xa -#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_MASK 0x400 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_LSB 0x7 +#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_MASK 0x80 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_LSB 0xb -#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_MASK 0x800 +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_LSB 0x8 +#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_MASK 0x100 #define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_LSB 0xc -#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_MASK 0x1000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_LSB 0x9 +#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_MASK 0x200 #define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_LSB 0xd -#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_MASK 0x2000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_LSB 0xa +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_MASK 0x400 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_LSB 0xe -#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_MASK 0x4000 +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_LSB 0xb +#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_MASK 0x800 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xf -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x8000 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xc +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x1000 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_LSB 0x10 -#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_MASK 0x10000 +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_LSB 0xd +#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_MASK 0x2000 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_SIZE 0x1 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_LSB 0x11 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_MASK 0x20000 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_OFFSET 0x7c -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_LSB 0x12 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_MASK 0x40000 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_PERIGATEONSLEEPCLR1_SEC_FABRIC_CLK_TIMER_OFFSET 0x7c #define GC_PMU_CLK0_HCLKGATEEN_LSB 0x0 #define GC_PMU_CLK0_HCLKGATEEN_MASK 0x1 #define GC_PMU_CLK0_HCLKGATEEN_SIZE 0x1 @@ -13577,268 +15159,253 @@ #define GC_PMU_CLK0_TRACECLKEN_SIZE 0x1 #define GC_PMU_CLK0_TRACECLKEN_DEFAULT 0x0 #define GC_PMU_CLK0_TRACECLKEN_OFFSET 0x80 -#define GC_PMU_RST0_DCAMO0_LSB 0x0 -#define GC_PMU_RST0_DCAMO0_MASK 0x1 -#define GC_PMU_RST0_DCAMO0_SIZE 0x1 -#define GC_PMU_RST0_DCAMO0_DEFAULT 0x0 -#define GC_PMU_RST0_DCAMO0_OFFSET 0x84 -#define GC_PMU_RST0_DCAMO0_CLK_RTC_LSB 0x1 -#define GC_PMU_RST0_DCAMO0_CLK_RTC_MASK 0x2 -#define GC_PMU_RST0_DCAMO0_CLK_RTC_SIZE 0x1 -#define GC_PMU_RST0_DCAMO0_CLK_RTC_DEFAULT 0x0 -#define GC_PMU_RST0_DCAMO0_CLK_RTC_OFFSET 0x84 -#define GC_PMU_RST0_DCRYPTO0_LSB 0x2 -#define GC_PMU_RST0_DCRYPTO0_MASK 0x4 +#define GC_PMU_RST0_DCAMO0_AON_LSB 0x0 +#define GC_PMU_RST0_DCAMO0_AON_MASK 0x1 +#define GC_PMU_RST0_DCAMO0_AON_SIZE 0x1 +#define GC_PMU_RST0_DCAMO0_AON_DEFAULT 0x0 +#define GC_PMU_RST0_DCAMO0_AON_OFFSET 0x84 +#define GC_PMU_RST0_DCRYPTO0_LSB 0x1 +#define GC_PMU_RST0_DCRYPTO0_MASK 0x2 #define GC_PMU_RST0_DCRYPTO0_SIZE 0x1 #define GC_PMU_RST0_DCRYPTO0_DEFAULT 0x0 #define GC_PMU_RST0_DCRYPTO0_OFFSET 0x84 -#define GC_PMU_RST0_DDMA0_LSB 0x3 -#define GC_PMU_RST0_DDMA0_MASK 0x8 +#define GC_PMU_RST0_DDMA0_LSB 0x2 +#define GC_PMU_RST0_DDMA0_MASK 0x4 #define GC_PMU_RST0_DDMA0_SIZE 0x1 #define GC_PMU_RST0_DDMA0_DEFAULT 0x0 #define GC_PMU_RST0_DDMA0_OFFSET 0x84 -#define GC_PMU_RST0_DFLASH0_LSB 0x4 -#define GC_PMU_RST0_DFLASH0_MASK 0x10 +#define GC_PMU_RST0_DFLASH0_LSB 0x3 +#define GC_PMU_RST0_DFLASH0_MASK 0x8 #define GC_PMU_RST0_DFLASH0_SIZE 0x1 #define GC_PMU_RST0_DFLASH0_DEFAULT 0x0 #define GC_PMU_RST0_DFLASH0_OFFSET 0x84 -#define GC_PMU_RST0_DFUSE0_LSB 0x5 -#define GC_PMU_RST0_DFUSE0_MASK 0x20 +#define GC_PMU_RST0_DFUSE0_LSB 0x4 +#define GC_PMU_RST0_DFUSE0_MASK 0x10 #define GC_PMU_RST0_DFUSE0_SIZE 0x1 #define GC_PMU_RST0_DFUSE0_DEFAULT 0x0 #define GC_PMU_RST0_DFUSE0_OFFSET 0x84 -#define GC_PMU_RST0_DGLOBALSEC_LSB 0x6 -#define GC_PMU_RST0_DGLOBALSEC_MASK 0x40 +#define GC_PMU_RST0_DGLOBALSEC_LSB 0x5 +#define GC_PMU_RST0_DGLOBALSEC_MASK 0x20 #define GC_PMU_RST0_DGLOBALSEC_SIZE 0x1 #define GC_PMU_RST0_DGLOBALSEC_DEFAULT 0x0 #define GC_PMU_RST0_DGLOBALSEC_OFFSET 0x84 -#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_LSB 0x7 -#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_MASK 0x80 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_LSB 0x6 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DGPIO0_LSB 0x8 -#define GC_PMU_RST0_DGPIO0_MASK 0x100 +#define GC_PMU_RST0_DGPIO0_LSB 0x7 +#define GC_PMU_RST0_DGPIO0_MASK 0x80 #define GC_PMU_RST0_DGPIO0_SIZE 0x1 #define GC_PMU_RST0_DGPIO0_DEFAULT 0x0 #define GC_PMU_RST0_DGPIO0_OFFSET 0x84 -#define GC_PMU_RST0_DGPIO1_LSB 0x9 -#define GC_PMU_RST0_DGPIO1_MASK 0x200 +#define GC_PMU_RST0_DGPIO1_LSB 0x8 +#define GC_PMU_RST0_DGPIO1_MASK 0x100 #define GC_PMU_RST0_DGPIO1_SIZE 0x1 #define GC_PMU_RST0_DGPIO1_DEFAULT 0x0 #define GC_PMU_RST0_DGPIO1_OFFSET 0x84 -#define GC_PMU_RST0_DI2C0_CLK_TIMER_LSB 0xa -#define GC_PMU_RST0_DI2C0_CLK_TIMER_MASK 0x400 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_LSB 0x9 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_MASK 0x200 #define GC_PMU_RST0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DI2C0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DI2C0_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DI2C1_CLK_TIMER_LSB 0xb -#define GC_PMU_RST0_DI2C1_CLK_TIMER_MASK 0x800 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_LSB 0xa +#define GC_PMU_RST0_DI2C1_CLK_TIMER_MASK 0x400 #define GC_PMU_RST0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DI2C1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DI2C1_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DI2CS0_LSB 0xc -#define GC_PMU_RST0_DI2CS0_MASK 0x1000 +#define GC_PMU_RST0_DI2CS0_LSB 0xb +#define GC_PMU_RST0_DI2CS0_MASK 0x800 #define GC_PMU_RST0_DI2CS0_SIZE 0x1 #define GC_PMU_RST0_DI2CS0_DEFAULT 0x0 #define GC_PMU_RST0_DI2CS0_OFFSET 0x84 -#define GC_PMU_RST0_DKEYMGR0_LSB 0xd -#define GC_PMU_RST0_DKEYMGR0_MASK 0x2000 +#define GC_PMU_RST0_DKEYMGR0_LSB 0xc +#define GC_PMU_RST0_DKEYMGR0_MASK 0x1000 #define GC_PMU_RST0_DKEYMGR0_SIZE 0x1 #define GC_PMU_RST0_DKEYMGR0_DEFAULT 0x0 #define GC_PMU_RST0_DKEYMGR0_OFFSET 0x84 -#define GC_PMU_RST0_DMAU_LSB 0xe -#define GC_PMU_RST0_DMAU_MASK 0x4000 +#define GC_PMU_RST0_DMAU_LSB 0xd +#define GC_PMU_RST0_DMAU_MASK 0x2000 #define GC_PMU_RST0_DMAU_SIZE 0x1 #define GC_PMU_RST0_DMAU_DEFAULT 0x0 #define GC_PMU_RST0_DMAU_OFFSET 0x84 -#define GC_PMU_RST0_DPERI_APB0_LSB 0xf -#define GC_PMU_RST0_DPERI_APB0_MASK 0x8000 +#define GC_PMU_RST0_DPERI_APB0_LSB 0xe +#define GC_PMU_RST0_DPERI_APB0_MASK 0x4000 #define GC_PMU_RST0_DPERI_APB0_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB0_DEFAULT 0x0 #define GC_PMU_RST0_DPERI_APB0_OFFSET 0x84 -#define GC_PMU_RST0_DPERI_APB1_LSB 0x10 -#define GC_PMU_RST0_DPERI_APB1_MASK 0x10000 +#define GC_PMU_RST0_DPERI_APB1_LSB 0xf +#define GC_PMU_RST0_DPERI_APB1_MASK 0x8000 #define GC_PMU_RST0_DPERI_APB1_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB1_DEFAULT 0x0 #define GC_PMU_RST0_DPERI_APB1_OFFSET 0x84 -#define GC_PMU_RST0_DPERI_APB2_LSB 0x11 -#define GC_PMU_RST0_DPERI_APB2_MASK 0x20000 +#define GC_PMU_RST0_DPERI_APB2_LSB 0x10 +#define GC_PMU_RST0_DPERI_APB2_MASK 0x10000 #define GC_PMU_RST0_DPERI_APB2_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB2_DEFAULT 0x0 #define GC_PMU_RST0_DPERI_APB2_OFFSET 0x84 -#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_LSB 0x12 -#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_MASK 0x40000 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_LSB 0x11 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DPINMUX_AON_LSB 0x13 -#define GC_PMU_RST0_DPINMUX_AON_MASK 0x80000 +#define GC_PMU_RST0_DPINMUX_AON_LSB 0x12 +#define GC_PMU_RST0_DPINMUX_AON_MASK 0x40000 #define GC_PMU_RST0_DPINMUX_AON_SIZE 0x1 #define GC_PMU_RST0_DPINMUX_AON_DEFAULT 0x0 #define GC_PMU_RST0_DPINMUX_AON_OFFSET 0x84 -#define GC_PMU_RST0_DPMU_AON_LSB 0x14 -#define GC_PMU_RST0_DPMU_AON_MASK 0x100000 +#define GC_PMU_RST0_DPMU_AON_LSB 0x13 +#define GC_PMU_RST0_DPMU_AON_MASK 0x80000 #define GC_PMU_RST0_DPMU_AON_SIZE 0x1 #define GC_PMU_RST0_DPMU_AON_DEFAULT 0x0 #define GC_PMU_RST0_DPMU_AON_OFFSET 0x84 -#define GC_PMU_RST0_DRBOX0_AON_LSB 0x15 -#define GC_PMU_RST0_DRBOX0_AON_MASK 0x200000 +#define GC_PMU_RST0_DRBOX0_AON_LSB 0x14 +#define GC_PMU_RST0_DRBOX0_AON_MASK 0x100000 #define GC_PMU_RST0_DRBOX0_AON_SIZE 0x1 #define GC_PMU_RST0_DRBOX0_AON_DEFAULT 0x0 #define GC_PMU_RST0_DRBOX0_AON_OFFSET 0x84 -#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_LSB 0x16 -#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_MASK 0x400000 -#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_SIZE 0x1 -#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DRBOX0_CLK_RTC_AON_OFFSET 0x84 -#define GC_PMU_RST0_DRDD0_LSB 0x17 -#define GC_PMU_RST0_DRDD0_MASK 0x800000 +#define GC_PMU_RST0_DRDD0_LSB 0x15 +#define GC_PMU_RST0_DRDD0_MASK 0x200000 #define GC_PMU_RST0_DRDD0_SIZE 0x1 #define GC_PMU_RST0_DRDD0_DEFAULT 0x0 #define GC_PMU_RST0_DRDD0_OFFSET 0x84 -#define GC_PMU_RST0_DRTC0_AON_LSB 0x18 -#define GC_PMU_RST0_DRTC0_AON_MASK 0x1000000 +#define GC_PMU_RST0_DRTC0_AON_LSB 0x16 +#define GC_PMU_RST0_DRTC0_AON_MASK 0x400000 #define GC_PMU_RST0_DRTC0_AON_SIZE 0x1 #define GC_PMU_RST0_DRTC0_AON_DEFAULT 0x0 #define GC_PMU_RST0_DRTC0_AON_OFFSET 0x84 -#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_LSB 0x19 -#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_MASK 0x2000000 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_LSB 0x17 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_MASK 0x800000 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_SIZE 0x1 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_DEFAULT 0x0 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_OFFSET 0x84 -#define GC_PMU_RST0_DSPI0_CLK_TIMER_LSB 0x1a -#define GC_PMU_RST0_DSPI0_CLK_TIMER_MASK 0x4000000 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_LSB 0x18 +#define GC_PMU_RST0_DSPI0_CLK_TIMER_MASK 0x1000000 #define GC_PMU_RST0_DSPI0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DSPI0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DSPI0_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DSPI1_CLK_TIMER_LSB 0x1b -#define GC_PMU_RST0_DSPI1_CLK_TIMER_MASK 0x8000000 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_LSB 0x19 +#define GC_PMU_RST0_DSPI1_CLK_TIMER_MASK 0x2000000 #define GC_PMU_RST0_DSPI1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DSPI1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST0_DSPI1_CLK_TIMER_OFFSET 0x84 -#define GC_PMU_RST0_DSPS0_LSB 0x1c -#define GC_PMU_RST0_DSPS0_MASK 0x10000000 +#define GC_PMU_RST0_DSPS0_LSB 0x1a +#define GC_PMU_RST0_DSPS0_MASK 0x4000000 #define GC_PMU_RST0_DSPS0_SIZE 0x1 #define GC_PMU_RST0_DSPS0_DEFAULT 0x0 #define GC_PMU_RST0_DSPS0_OFFSET 0x84 -#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_LSB 0x1d -#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_LSB 0x1b +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_MASK 0x8000000 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_OFFSET 0x84 -#define GC_PMU_RST0_DSWDP0_LSB 0x1e -#define GC_PMU_RST0_DSWDP0_MASK 0x40000000 +#define GC_PMU_RST0_DSWDP0_LSB 0x1c +#define GC_PMU_RST0_DSWDP0_MASK 0x10000000 #define GC_PMU_RST0_DSWDP0_SIZE 0x1 #define GC_PMU_RST0_DSWDP0_DEFAULT 0x0 #define GC_PMU_RST0_DSWDP0_OFFSET 0x84 -#define GC_PMU_RST0_DTEMP0_LSB 0x1f -#define GC_PMU_RST0_DTEMP0_MASK 0x80000000 +#define GC_PMU_RST0_DTEMP0_LSB 0x1d +#define GC_PMU_RST0_DTEMP0_MASK 0x20000000 #define GC_PMU_RST0_DTEMP0_SIZE 0x1 #define GC_PMU_RST0_DTEMP0_DEFAULT 0x0 #define GC_PMU_RST0_DTEMP0_OFFSET 0x84 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_LSB 0x0 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_MASK 0x1 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_SIZE 0x1 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_LSB 0x1 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_MASK 0x2 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_SIZE 0x1 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DTIMELS0_AON_LSB 0x2 -#define GC_PMU_RST1_DTIMELS0_AON_MASK 0x4 +#define GC_PMU_RST0_DTIMEHS0_CLK_TIMER_LSB 0x1e +#define GC_PMU_RST0_DTIMEHS0_CLK_TIMER_MASK 0x40000000 +#define GC_PMU_RST0_DTIMEHS0_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DTIMEHS0_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST0_DTIMEHS1_CLK_TIMER_LSB 0x1f +#define GC_PMU_RST0_DTIMEHS1_CLK_TIMER_MASK 0x80000000 +#define GC_PMU_RST0_DTIMEHS1_CLK_TIMER_SIZE 0x1 +#define GC_PMU_RST0_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 +#define GC_PMU_RST0_DTIMEHS1_CLK_TIMER_OFFSET 0x84 +#define GC_PMU_RST1_DTIMELS0_AON_LSB 0x0 +#define GC_PMU_RST1_DTIMELS0_AON_MASK 0x1 #define GC_PMU_RST1_DTIMELS0_AON_SIZE 0x1 #define GC_PMU_RST1_DTIMELS0_AON_DEFAULT 0x0 #define GC_PMU_RST1_DTIMELS0_AON_OFFSET 0x88 -#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_LSB 0x3 -#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_MASK 0x8 -#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_SIZE 0x1 -#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMELS0_CLK_RTC_AON_OFFSET 0x88 -#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_LSB 0x4 -#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_MASK 0x10 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_LSB 0x1 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_MASK 0x2 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DTRNG0_LSB 0x5 -#define GC_PMU_RST1_DTRNG0_MASK 0x20 +#define GC_PMU_RST1_DTRNG0_LSB 0x2 +#define GC_PMU_RST1_DTRNG0_MASK 0x4 #define GC_PMU_RST1_DTRNG0_SIZE 0x1 #define GC_PMU_RST1_DTRNG0_DEFAULT 0x0 #define GC_PMU_RST1_DTRNG0_OFFSET 0x88 -#define GC_PMU_RST1_DUART0_CLK_TIMER_LSB 0x6 -#define GC_PMU_RST1_DUART0_CLK_TIMER_MASK 0x40 +#define GC_PMU_RST1_DUART0_CLK_TIMER_LSB 0x3 +#define GC_PMU_RST1_DUART0_CLK_TIMER_MASK 0x8 #define GC_PMU_RST1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART0_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST1_DUART0_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DUART1_CLK_TIMER_LSB 0x7 -#define GC_PMU_RST1_DUART1_CLK_TIMER_MASK 0x80 +#define GC_PMU_RST1_DUART1_CLK_TIMER_LSB 0x4 +#define GC_PMU_RST1_DUART1_CLK_TIMER_MASK 0x10 #define GC_PMU_RST1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART1_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST1_DUART1_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DUART2_CLK_TIMER_LSB 0x8 -#define GC_PMU_RST1_DUART2_CLK_TIMER_MASK 0x100 +#define GC_PMU_RST1_DUART2_CLK_TIMER_LSB 0x5 +#define GC_PMU_RST1_DUART2_CLK_TIMER_MASK 0x20 #define GC_PMU_RST1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART2_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET 0x88 -#define GC_PMU_RST1_DUSB0_LSB 0x9 -#define GC_PMU_RST1_DUSB0_MASK 0x200 +#define GC_PMU_RST1_DUSB0_LSB 0x6 +#define GC_PMU_RST1_DUSB0_MASK 0x40 #define GC_PMU_RST1_DUSB0_SIZE 0x1 #define GC_PMU_RST1_DUSB0_DEFAULT 0x0 #define GC_PMU_RST1_DUSB0_OFFSET 0x88 -#define GC_PMU_RST1_DUSB0_AON_LSB 0xa -#define GC_PMU_RST1_DUSB0_AON_MASK 0x400 +#define GC_PMU_RST1_DUSB0_AON_LSB 0x7 +#define GC_PMU_RST1_DUSB0_AON_MASK 0x80 #define GC_PMU_RST1_DUSB0_AON_SIZE 0x1 #define GC_PMU_RST1_DUSB0_AON_DEFAULT 0x0 #define GC_PMU_RST1_DUSB0_AON_OFFSET 0x88 -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB 0xb -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK 0x800 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB 0x8 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK 0x100 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET 0x88 -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB 0xc -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK 0x1000 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB 0x9 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK 0x200 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_SIZE 0x1 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_DEFAULT 0x0 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x88 -#define GC_PMU_RST1_DVOLT0_LSB 0xd -#define GC_PMU_RST1_DVOLT0_MASK 0x2000 +#define GC_PMU_RST1_DVOLT0_LSB 0xa +#define GC_PMU_RST1_DVOLT0_MASK 0x400 #define GC_PMU_RST1_DVOLT0_SIZE 0x1 #define GC_PMU_RST1_DVOLT0_DEFAULT 0x0 #define GC_PMU_RST1_DVOLT0_OFFSET 0x88 -#define GC_PMU_RST1_DWATCHDOG0_LSB 0xe -#define GC_PMU_RST1_DWATCHDOG0_MASK 0x4000 +#define GC_PMU_RST1_DWATCHDOG0_LSB 0xb +#define GC_PMU_RST1_DWATCHDOG0_MASK 0x800 #define GC_PMU_RST1_DWATCHDOG0_SIZE 0x1 #define GC_PMU_RST1_DWATCHDOG0_DEFAULT 0x0 #define GC_PMU_RST1_DWATCHDOG0_OFFSET 0x88 -#define GC_PMU_RST1_DXO0_AON_LSB 0xf -#define GC_PMU_RST1_DXO0_AON_MASK 0x8000 +#define GC_PMU_RST1_DXO0_AON_LSB 0xc +#define GC_PMU_RST1_DXO0_AON_MASK 0x1000 #define GC_PMU_RST1_DXO0_AON_SIZE 0x1 #define GC_PMU_RST1_DXO0_AON_DEFAULT 0x0 #define GC_PMU_RST1_DXO0_AON_OFFSET 0x88 -#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB 0x10 -#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK 0x10000 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB 0xd +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK 0x2000 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_SIZE 0x1 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_DEFAULT 0x0 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET 0x88 -#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB 0x11 -#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK 0x20000 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB 0xe +#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK 0x4000 #define GC_PMU_RST1_PERI_MASTER_MATRIX_SIZE 0x1 #define GC_PMU_RST1_PERI_MASTER_MATRIX_DEFAULT 0x0 #define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET 0x88 -#define GC_PMU_RST1_PERI_MATRIX_LSB 0x12 -#define GC_PMU_RST1_PERI_MATRIX_MASK 0x40000 +#define GC_PMU_RST1_PERI_MATRIX_LSB 0xf +#define GC_PMU_RST1_PERI_MATRIX_MASK 0x8000 #define GC_PMU_RST1_PERI_MATRIX_SIZE 0x1 #define GC_PMU_RST1_PERI_MATRIX_DEFAULT 0x0 #define GC_PMU_RST1_PERI_MATRIX_OFFSET 0x88 -#define GC_PMU_RST1_SEC_FABRIC_LSB 0x13 -#define GC_PMU_RST1_SEC_FABRIC_MASK 0x80000 +#define GC_PMU_RST1_SEC_FABRIC_LSB 0x10 +#define GC_PMU_RST1_SEC_FABRIC_MASK 0x10000 #define GC_PMU_RST1_SEC_FABRIC_SIZE 0x1 #define GC_PMU_RST1_SEC_FABRIC_DEFAULT 0x0 #define GC_PMU_RST1_SEC_FABRIC_OFFSET 0x88 -#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB 0x14 -#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK 0x100000 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB 0x11 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK 0x20000 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET 0x88 @@ -13846,37 +15413,37 @@ #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_MASK 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x110 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_LSB 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_MASK 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x110 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_LSB 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_MASK 0x4 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x110 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_LSB 0x3 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_MASK 0x8 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x10c +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x110 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x120 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x124 #define GC_PMU_INT_STATE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_STATE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x124 +#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x128 #define GC_PMU_INT_TEST_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_TEST_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x128 +#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x12c #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1 @@ -13887,31 +15454,11 @@ #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_SIZE 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_DEFAULT 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_OFFSET 0x1008 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_LSB 0x0 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_MASK 0x1 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_SIZE 0x1 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TRNG_VLDO_EN_OFFSET 0x101c -#define GC_PMU_ANTEST_TEMP_DIFF_EN_LSB 0x0 -#define GC_PMU_ANTEST_TEMP_DIFF_EN_MASK 0x1 -#define GC_PMU_ANTEST_TEMP_DIFF_EN_SIZE 0x1 -#define GC_PMU_ANTEST_TEMP_DIFF_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_DIFF_EN_OFFSET 0x1020 -#define GC_PMU_ANTEST_TEMP_CM_EN_LSB 0x1 -#define GC_PMU_ANTEST_TEMP_CM_EN_MASK 0x2 -#define GC_PMU_ANTEST_TEMP_CM_EN_SIZE 0x1 -#define GC_PMU_ANTEST_TEMP_CM_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_CM_EN_OFFSET 0x1020 -#define GC_PMU_ANTEST_TEMP_REF_EN_LSB 0x2 -#define GC_PMU_ANTEST_TEMP_REF_EN_MASK 0x4 -#define GC_PMU_ANTEST_TEMP_REF_EN_SIZE 0x1 -#define GC_PMU_ANTEST_TEMP_REF_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_REF_EN_OFFSET 0x1020 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_LSB 0x3 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_MASK 0x8 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_SIZE 0x1 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_TEMP_VPTAT_EN_OFFSET 0x1020 +#define GC_PMU_ANTEST_XO_LDO_EN_LSB 0x0 +#define GC_PMU_ANTEST_XO_LDO_EN_MASK 0x1 +#define GC_PMU_ANTEST_XO_LDO_EN_SIZE 0x1 +#define GC_PMU_ANTEST_XO_LDO_EN_DEFAULT 0x0 +#define GC_PMU_ANTEST_XO_LDO_EN_OFFSET 0x101c #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_LSB 0x0 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_MASK 0xf #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_SIZE 0x4 @@ -13950,12 +15497,12 @@ #define GC_PMU_VERSION_CHANGE_LSB 0x0 #define GC_PMU_VERSION_CHANGE_MASK 0xffffff #define GC_PMU_VERSION_CHANGE_SIZE 0x18 -#define GC_PMU_VERSION_CHANGE_DEFAULT 0x10fc9 +#define GC_PMU_VERSION_CHANGE_DEFAULT 0x11f6d #define GC_PMU_VERSION_CHANGE_OFFSET 0x1fffc #define GC_PMU_VERSION_REVISION_LSB 0x18 #define GC_PMU_VERSION_REVISION_MASK 0xff000000 #define GC_PMU_VERSION_REVISION_SIZE 0x8 -#define GC_PMU_VERSION_REVISION_DEFAULT 0x21 +#define GC_PMU_VERSION_REVISION_DEFAULT 0x24 #define GC_PMU_VERSION_REVISION_OFFSET 0x1fffc #define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_LSB 0x0 #define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_MASK 0x1 @@ -14007,16 +15554,16 @@ #define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_SIZE 0x1 #define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_DEFAULT 0x0 #define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_OFFSET 0x0 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_LSB 0xa -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_MASK 0x400 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_SIZE 0x1 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_DEFAULT 0x0 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_RED_OFFSET 0x0 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_LSB 0xb -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_MASK 0x800 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_SIZE 0x1 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_DEFAULT 0x0 -#define GC_RBOX_INT_ENABLE_INTR_EC_RST_L_FED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_LSB 0xa +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_MASK 0x400 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_OFFSET 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_LSB 0xb +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_MASK 0x800 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_SIZE 0x1 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_DEFAULT 0x0 +#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_OFFSET 0x0 #define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_LSB 0xc #define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 #define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 @@ -14082,16 +15629,16 @@ #define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_SIZE 0x1 #define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_DEFAULT 0x0 #define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_OFFSET 0x4 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_LSB 0xa -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_MASK 0x400 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_SIZE 0x1 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_DEFAULT 0x0 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_RED_OFFSET 0x4 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_LSB 0xb -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_MASK 0x800 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_SIZE 0x1 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_DEFAULT 0x0 -#define GC_RBOX_INT_STATE_INTR_EC_RST_L_FED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_LSB 0xa +#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_MASK 0x400 +#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_OFFSET 0x4 +#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_LSB 0xb +#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_MASK 0x800 +#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_SIZE 0x1 +#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_DEFAULT 0x0 +#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_OFFSET 0x4 #define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_LSB 0xc #define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 #define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 @@ -14157,16 +15704,16 @@ #define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_SIZE 0x1 #define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_DEFAULT 0x0 #define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_OFFSET 0x8 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_LSB 0xa -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_MASK 0x400 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_SIZE 0x1 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_DEFAULT 0x0 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_RED_OFFSET 0x8 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_LSB 0xb -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_MASK 0x800 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_SIZE 0x1 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_DEFAULT 0x0 -#define GC_RBOX_INT_TEST_INTR_EC_RST_L_FED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_LSB 0xa +#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_MASK 0x400 +#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_OFFSET 0x8 +#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_LSB 0xb +#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_MASK 0x800 +#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_SIZE 0x1 +#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_DEFAULT 0x0 +#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_OFFSET 0x8 #define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_LSB 0xc #define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 #define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 @@ -14186,382 +15733,797 @@ #define GC_RBOX_OVERRIDE_OUTPUT_EN_MASK 0x7f #define GC_RBOX_OVERRIDE_OUTPUT_EN_SIZE 0x7 #define GC_RBOX_OVERRIDE_OUTPUT_EN_DEFAULT 0x0 -#define GC_RBOX_OVERRIDE_OUTPUT_EN_OFFSET 0x18 +#define GC_RBOX_OVERRIDE_OUTPUT_EN_OFFSET 0x14 #define GC_RBOX_OVERRIDE_OUTPUT_VAL_LSB 0x7 #define GC_RBOX_OVERRIDE_OUTPUT_VAL_MASK 0x3f80 #define GC_RBOX_OVERRIDE_OUTPUT_VAL_SIZE 0x7 -#define GC_RBOX_OVERRIDE_OUTPUT_VAL_DEFAULT 0x0 -#define GC_RBOX_OVERRIDE_OUTPUT_VAL_OFFSET 0x18 +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_DEFAULT 0x5d +#define GC_RBOX_OVERRIDE_OUTPUT_VAL_OFFSET 0x14 #define GC_RBOX_OVERRIDE_OUTPUT_OEN_LSB 0xe #define GC_RBOX_OVERRIDE_OUTPUT_OEN_MASK 0x1fc000 #define GC_RBOX_OVERRIDE_OUTPUT_OEN_SIZE 0x7 #define GC_RBOX_OVERRIDE_OUTPUT_OEN_DEFAULT 0x0 -#define GC_RBOX_OVERRIDE_OUTPUT_OEN_OFFSET 0x18 -#define GC_RBOX_CHECK_IO_INPUTS_LSB 0x0 -#define GC_RBOX_CHECK_IO_INPUTS_MASK 0x3f -#define GC_RBOX_CHECK_IO_INPUTS_SIZE 0x6 -#define GC_RBOX_CHECK_IO_INPUTS_DEFAULT 0x0 -#define GC_RBOX_CHECK_IO_INPUTS_OFFSET 0x1c -#define GC_RBOX_CHECK_IO_OUTPUTS_LSB 0x6 -#define GC_RBOX_CHECK_IO_OUTPUTS_MASK 0x1fc0 -#define GC_RBOX_CHECK_IO_OUTPUTS_SIZE 0x7 -#define GC_RBOX_CHECK_IO_OUTPUTS_DEFAULT 0x0 -#define GC_RBOX_CHECK_IO_OUTPUTS_OFFSET 0x1c -#define GC_RBOX_CHECK_IO_OENS_LSB 0xd -#define GC_RBOX_CHECK_IO_OENS_MASK 0xfe000 -#define GC_RBOX_CHECK_IO_OENS_SIZE 0x7 -#define GC_RBOX_CHECK_IO_OENS_DEFAULT 0x0 -#define GC_RBOX_CHECK_IO_OENS_OFFSET 0x1c +#define GC_RBOX_OVERRIDE_OUTPUT_OEN_OFFSET 0x14 +#define GC_RBOX_CHECK_INPUT_AC_PRESENT_LSB 0x0 +#define GC_RBOX_CHECK_INPUT_AC_PRESENT_MASK 0x1 +#define GC_RBOX_CHECK_INPUT_AC_PRESENT_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_AC_PRESENT_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_AC_PRESENT_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_ENTERING_RW_LSB 0x1 +#define GC_RBOX_CHECK_INPUT_ENTERING_RW_MASK 0x2 +#define GC_RBOX_CHECK_INPUT_ENTERING_RW_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_ENTERING_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_ENTERING_RW_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_PWRB_IN_LSB 0x2 +#define GC_RBOX_CHECK_INPUT_PWRB_IN_MASK 0x4 +#define GC_RBOX_CHECK_INPUT_PWRB_IN_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_PWRB_IN_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_KEY0_IN_LSB 0x3 +#define GC_RBOX_CHECK_INPUT_KEY0_IN_MASK 0x8 +#define GC_RBOX_CHECK_INPUT_KEY0_IN_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_KEY0_IN_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_KEY1_IN_LSB 0x4 +#define GC_RBOX_CHECK_INPUT_KEY1_IN_MASK 0x10 +#define GC_RBOX_CHECK_INPUT_KEY1_IN_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_KEY1_IN_OFFSET 0x18 +#define GC_RBOX_CHECK_INPUT_EC_RST_LSB 0x5 +#define GC_RBOX_CHECK_INPUT_EC_RST_MASK 0x20 +#define GC_RBOX_CHECK_INPUT_EC_RST_SIZE 0x1 +#define GC_RBOX_CHECK_INPUT_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CHECK_INPUT_EC_RST_OFFSET 0x18 +#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_LSB 0x0 +#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_MASK 0x1 +#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_LSB 0x1 +#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_MASK 0x2 +#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_LSB 0x2 +#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_MASK 0x4 +#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_LSB 0x3 +#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_MASK 0x8 +#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_LSB 0x4 +#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_MASK 0x10 +#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_LSB 0x5 +#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_MASK 0x20 +#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_OFFSET 0x1c +#define GC_RBOX_CHECK_OUTPUT_EC_RST_LSB 0x6 +#define GC_RBOX_CHECK_OUTPUT_EC_RST_MASK 0x40 +#define GC_RBOX_CHECK_OUTPUT_EC_RST_SIZE 0x1 +#define GC_RBOX_CHECK_OUTPUT_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CHECK_OUTPUT_EC_RST_OFFSET 0x1c +#define GC_RBOX_CHECK_OEN_BATT_DISABLE_LSB 0x0 +#define GC_RBOX_CHECK_OEN_BATT_DISABLE_MASK 0x1 +#define GC_RBOX_CHECK_OEN_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_BATT_DISABLE_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_EC_IN_RW_LSB 0x1 +#define GC_RBOX_CHECK_OEN_EC_IN_RW_MASK 0x2 +#define GC_RBOX_CHECK_OEN_EC_IN_RW_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_EC_IN_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_EC_IN_RW_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_PWRB_OUT_LSB 0x2 +#define GC_RBOX_CHECK_OEN_PWRB_OUT_MASK 0x4 +#define GC_RBOX_CHECK_OEN_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_PWRB_OUT_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_KEY0_OUT_LSB 0x3 +#define GC_RBOX_CHECK_OEN_KEY0_OUT_MASK 0x8 +#define GC_RBOX_CHECK_OEN_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_KEY0_OUT_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_KEY1_OUT_LSB 0x4 +#define GC_RBOX_CHECK_OEN_KEY1_OUT_MASK 0x10 +#define GC_RBOX_CHECK_OEN_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_KEY1_OUT_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_EC_WP_L_LSB 0x5 +#define GC_RBOX_CHECK_OEN_EC_WP_L_MASK 0x20 +#define GC_RBOX_CHECK_OEN_EC_WP_L_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_EC_WP_L_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_EC_WP_L_OFFSET 0x20 +#define GC_RBOX_CHECK_OEN_EC_RST_LSB 0x6 +#define GC_RBOX_CHECK_OEN_EC_RST_MASK 0x40 +#define GC_RBOX_CHECK_OEN_EC_RST_SIZE 0x1 +#define GC_RBOX_CHECK_OEN_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CHECK_OEN_EC_RST_OFFSET 0x20 +#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_LSB 0x0 +#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_MASK 0x1 +#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_LSB 0x1 +#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_MASK 0x2 +#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_LSB 0x2 +#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_MASK 0x4 +#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_LSB 0x3 +#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_MASK 0x8 +#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_LSB 0x4 +#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_MASK 0x10 +#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_LSB 0x5 +#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_MASK 0x20 +#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_LSB 0x6 +#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_MASK 0x40 +#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_LSB 0x7 +#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_MASK 0x80 +#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_LSB 0x8 +#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_MASK 0x100 +#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_LSB 0x9 +#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_MASK 0x200 +#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_EC_RST_LSB 0xa +#define GC_RBOX_CHECK_TERM_PU_EC_RST_MASK 0x400 +#define GC_RBOX_CHECK_TERM_PU_EC_RST_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_EC_RST_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_EC_RST_LSB 0xb +#define GC_RBOX_CHECK_TERM_PD_EC_RST_MASK 0x800 +#define GC_RBOX_CHECK_TERM_PD_EC_RST_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_EC_RST_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_LSB 0xc +#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_MASK 0x1000 +#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_LSB 0xd +#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_MASK 0x2000 +#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_LSB 0xe +#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_MASK 0x4000 +#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_LSB 0xf +#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_MASK 0x8000 +#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_LSB 0x10 +#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_MASK 0x10000 +#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_LSB 0x11 +#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_MASK 0x20000 +#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_LSB 0x12 +#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_MASK 0x40000 +#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_LSB 0x13 +#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_MASK 0x80000 +#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_LSB 0x14 +#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_MASK 0x100000 +#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_LSB 0x15 +#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_MASK 0x200000 +#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_LSB 0x16 +#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_MASK 0x400000 +#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_OFFSET 0x24 +#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_LSB 0x17 +#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_MASK 0x800000 +#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_SIZE 0x1 +#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_DEFAULT 0x0 +#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_OFFSET 0x24 #define GC_RBOX_STATUS_FUSE_READY_LSB 0x0 #define GC_RBOX_STATUS_FUSE_READY_MASK 0x1 #define GC_RBOX_STATUS_FUSE_READY_SIZE 0x1 #define GC_RBOX_STATUS_FUSE_READY_DEFAULT 0x0 -#define GC_RBOX_STATUS_FUSE_READY_OFFSET 0x20 +#define GC_RBOX_STATUS_FUSE_READY_OFFSET 0x28 #define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_LSB 0x1 #define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_MASK 0x2 #define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_SIZE 0x1 #define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_DEFAULT 0x0 -#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_OFFSET 0x20 +#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_OFFSET 0x28 #define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_LSB 0x2 -#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_MASK 0x4 -#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_SIZE 0x1 +#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_MASK 0x1fc +#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_SIZE 0x7 #define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_DEFAULT 0x0 -#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_OFFSET 0x20 +#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_OFFSET 0x28 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_LSB 0x0 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_MASK 0x1 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_SIZE 0x1 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_DEFAULT 0x0 -#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_OFFSET 0x2c #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_LSB 0x1 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_MASK 0x2 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_SIZE 0x1 #define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_DEFAULT 0x0 -#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_OFFSET 0x2c #define GC_RBOX_FUSE_CTRL_USE_SILEGO_LSB 0x2 #define GC_RBOX_FUSE_CTRL_USE_SILEGO_MASK 0x4 #define GC_RBOX_FUSE_CTRL_USE_SILEGO_SIZE 0x1 #define GC_RBOX_FUSE_CTRL_USE_SILEGO_DEFAULT 0x0 -#define GC_RBOX_FUSE_CTRL_USE_SILEGO_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_USE_SILEGO_OFFSET 0x2c #define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_LSB 0x3 #define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_MASK 0x8 #define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_SIZE 0x1 #define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_DEFAULT 0x0 -#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_OFFSET 0x24 +#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_OFFSET 0x2c +#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_LSB 0x0 +#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_MASK 0xffff +#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_SIZE 0x10 +#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_DEFAULT 0x0 +#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_OFFSET 0x30 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_LSB 0x10 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_MASK 0x10000 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_SIZE 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_OFFSET 0x30 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_LSB 0x11 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_MASK 0x20000 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_SIZE 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_OFFSET 0x30 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_LSB 0x12 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_MASK 0x40000 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_SIZE 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x1 +#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_OFFSET 0x30 #define GC_RBOX_DEBUG_KEY_COMBO0_VAL_LSB 0x0 #define GC_RBOX_DEBUG_KEY_COMBO0_VAL_MASK 0xff #define GC_RBOX_DEBUG_KEY_COMBO0_VAL_SIZE 0x8 #define GC_RBOX_DEBUG_KEY_COMBO0_VAL_DEFAULT 0xc0 -#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_OFFSET 0x2c +#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_OFFSET 0x34 #define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_LSB 0x8 #define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_MASK 0xff00 #define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_SIZE 0x8 -#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_DEFAULT 0x63 -#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_OFFSET 0x2c +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_OFFSET 0x34 #define GC_RBOX_DEBUG_KEY_COMBO1_VAL_LSB 0x0 #define GC_RBOX_DEBUG_KEY_COMBO1_VAL_MASK 0xff #define GC_RBOX_DEBUG_KEY_COMBO1_VAL_SIZE 0x8 #define GC_RBOX_DEBUG_KEY_COMBO1_VAL_DEFAULT 0x0 -#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_OFFSET 0x30 +#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_OFFSET 0x38 #define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_LSB 0x8 #define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_MASK 0xff00 #define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_SIZE 0x8 -#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_DEFAULT 0x63 -#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_OFFSET 0x30 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_OFFSET 0x38 #define GC_RBOX_DEBUG_KEY_COMBO2_VAL_LSB 0x0 #define GC_RBOX_DEBUG_KEY_COMBO2_VAL_MASK 0xff #define GC_RBOX_DEBUG_KEY_COMBO2_VAL_SIZE 0x8 #define GC_RBOX_DEBUG_KEY_COMBO2_VAL_DEFAULT 0x0 -#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_OFFSET 0x34 +#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_OFFSET 0x3c #define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_LSB 0x8 #define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_MASK 0xff00 #define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_SIZE 0x8 -#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_DEFAULT 0x63 -#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_OFFSET 0x34 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_LSB 0x0 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_MASK 0x1 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_SIZE 0x1 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_DEFAULT 0x0 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY0_OFFSET 0x38 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_LSB 0x1 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_MASK 0x2 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_SIZE 0x1 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_DEFAULT 0x0 -#define GC_RBOX_DEBUG_BLOCK_KEY_KEY1_OFFSET 0x38 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_DEFAULT 0x0 +#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_OFFSET 0x3c +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_LSB 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_MASK 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_OFFSET 0x40 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_LSB 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_MASK 0x2 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_OFFSET 0x40 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_LSB 0x2 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_MASK 0x4 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_OFFSET 0x40 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_LSB 0x3 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_MASK 0x8 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_SIZE 0x1 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_DEFAULT 0x0 +#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_OFFSET 0x40 #define GC_RBOX_DEBUG_POL_AC_PRESENT_LSB 0x0 #define GC_RBOX_DEBUG_POL_AC_PRESENT_MASK 0x1 #define GC_RBOX_DEBUG_POL_AC_PRESENT_SIZE 0x1 #define GC_RBOX_DEBUG_POL_AC_PRESENT_DEFAULT 0x1 -#define GC_RBOX_DEBUG_POL_AC_PRESENT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_AC_PRESENT_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_PWRB_IN_LSB 0x1 #define GC_RBOX_DEBUG_POL_PWRB_IN_MASK 0x2 #define GC_RBOX_DEBUG_POL_PWRB_IN_SIZE 0x1 #define GC_RBOX_DEBUG_POL_PWRB_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_PWRB_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_PWRB_IN_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_PWRB_OUT_LSB 0x2 #define GC_RBOX_DEBUG_POL_PWRB_OUT_MASK 0x4 #define GC_RBOX_DEBUG_POL_PWRB_OUT_SIZE 0x1 #define GC_RBOX_DEBUG_POL_PWRB_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_PWRB_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_PWRB_OUT_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_KEY0_IN_LSB 0x3 #define GC_RBOX_DEBUG_POL_KEY0_IN_MASK 0x8 #define GC_RBOX_DEBUG_POL_KEY0_IN_SIZE 0x1 #define GC_RBOX_DEBUG_POL_KEY0_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_KEY0_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY0_IN_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_KEY0_OUT_LSB 0x4 #define GC_RBOX_DEBUG_POL_KEY0_OUT_MASK 0x10 #define GC_RBOX_DEBUG_POL_KEY0_OUT_SIZE 0x1 #define GC_RBOX_DEBUG_POL_KEY0_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_KEY0_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY0_OUT_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_KEY1_IN_LSB 0x5 #define GC_RBOX_DEBUG_POL_KEY1_IN_MASK 0x20 #define GC_RBOX_DEBUG_POL_KEY1_IN_SIZE 0x1 #define GC_RBOX_DEBUG_POL_KEY1_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_KEY1_IN_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY1_IN_OFFSET 0x44 #define GC_RBOX_DEBUG_POL_KEY1_OUT_LSB 0x6 #define GC_RBOX_DEBUG_POL_KEY1_OUT_MASK 0x40 #define GC_RBOX_DEBUG_POL_KEY1_OUT_SIZE 0x1 #define GC_RBOX_DEBUG_POL_KEY1_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_POL_KEY1_OUT_OFFSET 0x3c +#define GC_RBOX_DEBUG_POL_KEY1_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_POL_EC_RST_LSB 0x7 +#define GC_RBOX_DEBUG_POL_EC_RST_MASK 0x80 +#define GC_RBOX_DEBUG_POL_EC_RST_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_EC_RST_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_EC_RST_OFFSET 0x44 +#define GC_RBOX_DEBUG_POL_BATT_DISABLE_LSB 0x8 +#define GC_RBOX_DEBUG_POL_BATT_DISABLE_MASK 0x100 +#define GC_RBOX_DEBUG_POL_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_DEBUG_POL_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_DEBUG_POL_BATT_DISABLE_OFFSET 0x44 #define GC_RBOX_DEBUG_TERM_AC_PRESENT_LSB 0x0 #define GC_RBOX_DEBUG_TERM_AC_PRESENT_MASK 0x3 #define GC_RBOX_DEBUG_TERM_AC_PRESENT_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_AC_PRESENT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_AC_PRESENT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_AC_PRESENT_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_ENTERING_RW_LSB 0x2 #define GC_RBOX_DEBUG_TERM_ENTERING_RW_MASK 0xc #define GC_RBOX_DEBUG_TERM_ENTERING_RW_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_ENTERING_RW_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_ENTERING_RW_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_ENTERING_RW_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_PWRB_IN_LSB 0x4 #define GC_RBOX_DEBUG_TERM_PWRB_IN_MASK 0x30 #define GC_RBOX_DEBUG_TERM_PWRB_IN_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_PWRB_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_PWRB_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_PWRB_IN_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_PWRB_OUT_LSB 0x6 #define GC_RBOX_DEBUG_TERM_PWRB_OUT_MASK 0xc0 #define GC_RBOX_DEBUG_TERM_PWRB_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_PWRB_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_PWRB_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_PWRB_OUT_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_KEY0_IN_LSB 0x8 #define GC_RBOX_DEBUG_TERM_KEY0_IN_MASK 0x300 #define GC_RBOX_DEBUG_TERM_KEY0_IN_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_KEY0_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_KEY0_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY0_IN_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_KEY0_OUT_LSB 0xa #define GC_RBOX_DEBUG_TERM_KEY0_OUT_MASK 0xc00 #define GC_RBOX_DEBUG_TERM_KEY0_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_KEY0_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_KEY0_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY0_OUT_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_KEY1_IN_LSB 0xc #define GC_RBOX_DEBUG_TERM_KEY1_IN_MASK 0x3000 #define GC_RBOX_DEBUG_TERM_KEY1_IN_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_KEY1_IN_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_KEY1_IN_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY1_IN_OFFSET 0x48 #define GC_RBOX_DEBUG_TERM_KEY1_OUT_LSB 0xe #define GC_RBOX_DEBUG_TERM_KEY1_OUT_MASK 0xc000 #define GC_RBOX_DEBUG_TERM_KEY1_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_TERM_KEY1_OUT_DEFAULT 0x0 -#define GC_RBOX_DEBUG_TERM_KEY1_OUT_OFFSET 0x40 +#define GC_RBOX_DEBUG_TERM_KEY1_OUT_OFFSET 0x48 #define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_LSB 0x0 #define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_MASK 0x3 #define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_DEFAULT 0x3 -#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_OFFSET 0x4c #define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_LSB 0x2 #define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_MASK 0xc #define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_DEFAULT 0x3 -#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_OFFSET 0x4c #define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_LSB 0x4 #define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_MASK 0x30 #define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_SIZE 0x2 #define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_DEFAULT 0x3 -#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_OFFSET 0x44 +#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_OFFSET 0x4c +#define GC_RBOX_DEBUG_DRIVE_EC_RST_LSB 0x6 +#define GC_RBOX_DEBUG_DRIVE_EC_RST_MASK 0xc0 +#define GC_RBOX_DEBUG_DRIVE_EC_RST_SIZE 0x2 +#define GC_RBOX_DEBUG_DRIVE_EC_RST_DEFAULT 0x1 +#define GC_RBOX_DEBUG_DRIVE_EC_RST_OFFSET 0x4c +#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_LSB 0x8 +#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_MASK 0x300 +#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_SIZE 0x2 +#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_DEFAULT 0x1 +#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_OFFSET 0x4c +#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_LSB 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_MASK 0xffff +#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_SIZE 0x10 +#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_OFFSET 0x6c +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_LSB 0x10 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_MASK 0x10000 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_SIZE 0x1 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_OFFSET 0x6c +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_LSB 0x11 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_MASK 0x20000 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_SIZE 0x1 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_OFFSET 0x6c +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_LSB 0x12 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_MASK 0x40000 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_SIZE 0x1 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_OFFSET 0x6c #define GC_RBOX_CONFIG_KEY_COMBO0_VAL_LSB 0x0 #define GC_RBOX_CONFIG_KEY_COMBO0_VAL_MASK 0xff #define GC_RBOX_CONFIG_KEY_COMBO0_VAL_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO0_VAL_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_OFFSET 0x70 #define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_LSB 0x8 #define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_MASK 0xff00 #define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_OFFSET 0x68 +#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_OFFSET 0x70 #define GC_RBOX_CONFIG_KEY_COMBO1_VAL_LSB 0x0 #define GC_RBOX_CONFIG_KEY_COMBO1_VAL_MASK 0xff #define GC_RBOX_CONFIG_KEY_COMBO1_VAL_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO1_VAL_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_OFFSET 0x74 #define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_LSB 0x8 #define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_MASK 0xff00 #define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_OFFSET 0x6c +#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_OFFSET 0x74 #define GC_RBOX_CONFIG_KEY_COMBO2_VAL_LSB 0x0 #define GC_RBOX_CONFIG_KEY_COMBO2_VAL_MASK 0xff #define GC_RBOX_CONFIG_KEY_COMBO2_VAL_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO2_VAL_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_OFFSET 0x70 +#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_OFFSET 0x78 #define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_LSB 0x8 #define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_MASK 0xff00 #define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_SIZE 0x8 #define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_DEFAULT 0x0 -#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_OFFSET 0x70 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_LSB 0x0 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_MASK 0x1 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_SIZE 0x1 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_DEFAULT 0x0 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY0_OFFSET 0x74 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_LSB 0x1 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_MASK 0x2 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_SIZE 0x1 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_DEFAULT 0x0 -#define GC_RBOX_CONFIG_BLOCK_KEY_KEY1_OFFSET 0x74 +#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_OFFSET 0x78 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_LSB 0x0 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_MASK 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_OFFSET 0x7c +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_LSB 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_MASK 0x2 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_OFFSET 0x7c +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_LSB 0x2 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_MASK 0x4 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_OFFSET 0x7c +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_LSB 0x3 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_MASK 0x8 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_SIZE 0x1 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_DEFAULT 0x0 +#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_OFFSET 0x7c #define GC_RBOX_CONFIG_POL_AC_PRESENT_LSB 0x0 #define GC_RBOX_CONFIG_POL_AC_PRESENT_MASK 0x1 #define GC_RBOX_CONFIG_POL_AC_PRESENT_SIZE 0x1 #define GC_RBOX_CONFIG_POL_AC_PRESENT_DEFAULT 0x1 -#define GC_RBOX_CONFIG_POL_AC_PRESENT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_AC_PRESENT_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_PWRB_IN_LSB 0x1 #define GC_RBOX_CONFIG_POL_PWRB_IN_MASK 0x2 #define GC_RBOX_CONFIG_POL_PWRB_IN_SIZE 0x1 #define GC_RBOX_CONFIG_POL_PWRB_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_PWRB_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_PWRB_IN_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_PWRB_OUT_LSB 0x2 #define GC_RBOX_CONFIG_POL_PWRB_OUT_MASK 0x4 #define GC_RBOX_CONFIG_POL_PWRB_OUT_SIZE 0x1 #define GC_RBOX_CONFIG_POL_PWRB_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_PWRB_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_PWRB_OUT_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_KEY0_IN_LSB 0x3 #define GC_RBOX_CONFIG_POL_KEY0_IN_MASK 0x8 #define GC_RBOX_CONFIG_POL_KEY0_IN_SIZE 0x1 #define GC_RBOX_CONFIG_POL_KEY0_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_KEY0_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY0_IN_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_KEY0_OUT_LSB 0x4 #define GC_RBOX_CONFIG_POL_KEY0_OUT_MASK 0x10 #define GC_RBOX_CONFIG_POL_KEY0_OUT_SIZE 0x1 #define GC_RBOX_CONFIG_POL_KEY0_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_KEY0_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY0_OUT_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_KEY1_IN_LSB 0x5 #define GC_RBOX_CONFIG_POL_KEY1_IN_MASK 0x20 #define GC_RBOX_CONFIG_POL_KEY1_IN_SIZE 0x1 #define GC_RBOX_CONFIG_POL_KEY1_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_KEY1_IN_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY1_IN_OFFSET 0x80 #define GC_RBOX_CONFIG_POL_KEY1_OUT_LSB 0x6 #define GC_RBOX_CONFIG_POL_KEY1_OUT_MASK 0x40 #define GC_RBOX_CONFIG_POL_KEY1_OUT_SIZE 0x1 #define GC_RBOX_CONFIG_POL_KEY1_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_POL_KEY1_OUT_OFFSET 0x78 +#define GC_RBOX_CONFIG_POL_KEY1_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_POL_EC_RST_LSB 0x7 +#define GC_RBOX_CONFIG_POL_EC_RST_MASK 0x80 +#define GC_RBOX_CONFIG_POL_EC_RST_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_EC_RST_OFFSET 0x80 +#define GC_RBOX_CONFIG_POL_BATT_DISABLE_LSB 0x8 +#define GC_RBOX_CONFIG_POL_BATT_DISABLE_MASK 0x100 +#define GC_RBOX_CONFIG_POL_BATT_DISABLE_SIZE 0x1 +#define GC_RBOX_CONFIG_POL_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CONFIG_POL_BATT_DISABLE_OFFSET 0x80 #define GC_RBOX_CONFIG_TERM_AC_PRESENT_LSB 0x0 #define GC_RBOX_CONFIG_TERM_AC_PRESENT_MASK 0x3 #define GC_RBOX_CONFIG_TERM_AC_PRESENT_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_AC_PRESENT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_AC_PRESENT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_AC_PRESENT_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_ENTERING_RW_LSB 0x2 #define GC_RBOX_CONFIG_TERM_ENTERING_RW_MASK 0xc #define GC_RBOX_CONFIG_TERM_ENTERING_RW_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_ENTERING_RW_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_ENTERING_RW_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_ENTERING_RW_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_PWRB_IN_LSB 0x4 #define GC_RBOX_CONFIG_TERM_PWRB_IN_MASK 0x30 #define GC_RBOX_CONFIG_TERM_PWRB_IN_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_PWRB_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_PWRB_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_PWRB_IN_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_PWRB_OUT_LSB 0x6 #define GC_RBOX_CONFIG_TERM_PWRB_OUT_MASK 0xc0 #define GC_RBOX_CONFIG_TERM_PWRB_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_PWRB_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_PWRB_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_PWRB_OUT_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_KEY0_IN_LSB 0x8 #define GC_RBOX_CONFIG_TERM_KEY0_IN_MASK 0x300 #define GC_RBOX_CONFIG_TERM_KEY0_IN_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_KEY0_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_KEY0_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY0_IN_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_KEY0_OUT_LSB 0xa #define GC_RBOX_CONFIG_TERM_KEY0_OUT_MASK 0xc00 #define GC_RBOX_CONFIG_TERM_KEY0_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_KEY0_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_KEY0_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY0_OUT_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_KEY1_IN_LSB 0xc #define GC_RBOX_CONFIG_TERM_KEY1_IN_MASK 0x3000 #define GC_RBOX_CONFIG_TERM_KEY1_IN_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_KEY1_IN_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_KEY1_IN_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY1_IN_OFFSET 0x84 #define GC_RBOX_CONFIG_TERM_KEY1_OUT_LSB 0xe #define GC_RBOX_CONFIG_TERM_KEY1_OUT_MASK 0xc000 #define GC_RBOX_CONFIG_TERM_KEY1_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_TERM_KEY1_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_TERM_KEY1_OUT_OFFSET 0x7c +#define GC_RBOX_CONFIG_TERM_KEY1_OUT_OFFSET 0x84 #define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_LSB 0x0 #define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_MASK 0x3 #define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_OFFSET 0x88 #define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_LSB 0x2 #define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_MASK 0xc #define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_OFFSET 0x88 #define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_LSB 0x4 #define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_MASK 0x30 #define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_SIZE 0x2 #define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_DEFAULT 0x0 -#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_OFFSET 0x80 +#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_OFFSET 0x88 +#define GC_RBOX_CONFIG_DRIVE_EC_RST_LSB 0x6 +#define GC_RBOX_CONFIG_DRIVE_EC_RST_MASK 0xc0 +#define GC_RBOX_CONFIG_DRIVE_EC_RST_SIZE 0x2 +#define GC_RBOX_CONFIG_DRIVE_EC_RST_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_EC_RST_OFFSET 0x88 +#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_LSB 0x8 +#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_MASK 0x300 +#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_SIZE 0x2 +#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_DEFAULT 0x0 +#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_OFFSET 0x88 +#define GC_RBOX_WAKEUP_ENABLE_LSB 0x0 +#define GC_RBOX_WAKEUP_ENABLE_MASK 0x1 +#define GC_RBOX_WAKEUP_ENABLE_SIZE 0x1 +#define GC_RBOX_WAKEUP_ENABLE_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_ENABLE_OFFSET 0x98 +#define GC_RBOX_WAKEUP_CLEAR_LSB 0x1 +#define GC_RBOX_WAKEUP_CLEAR_MASK 0x2 +#define GC_RBOX_WAKEUP_CLEAR_SIZE 0x1 +#define GC_RBOX_WAKEUP_CLEAR_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_CLEAR_OFFSET 0x98 +#define GC_RBOX_WAKEUP_MASK_LSB 0x2 +#define GC_RBOX_WAKEUP_MASK_MASK 0x4 +#define GC_RBOX_WAKEUP_MASK_SIZE 0x1 +#define GC_RBOX_WAKEUP_MASK_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_MASK_OFFSET 0x98 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_LSB 0x0 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_MASK 0x1 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_LSB 0x1 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_MASK 0x2 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_LSB 0x2 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_MASK 0x4 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_LSB 0x3 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_MASK 0x8 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_LSB 0x4 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_MASK 0x10 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_LSB 0x5 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_MASK 0x20 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_LSB 0x6 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_MASK 0x40 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_LSB 0x7 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_MASK 0x80 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_LSB 0x8 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_MASK 0x100 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_LSB 0x9 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_MASK 0x200 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_LSB 0xa +#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_MASK 0x400 +#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_LSB 0xb +#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_MASK 0x800 +#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_LSB 0xc +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_MASK 0x1000 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_LSB 0xd +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_MASK 0x2000 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_OFFSET 0x9c +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_LSB 0xe +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_MASK 0x4000 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_SIZE 0x1 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0 +#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_OFFSET 0x9c #define GC_RBOX_VERSION_CHANGE_LSB 0x0 #define GC_RBOX_VERSION_CHANGE_MASK 0xffffff #define GC_RBOX_VERSION_CHANGE_SIZE 0x18 -#define GC_RBOX_VERSION_CHANGE_DEFAULT 0x11174 -#define GC_RBOX_VERSION_CHANGE_OFFSET 0x90 +#define GC_RBOX_VERSION_CHANGE_DEFAULT 0x11ae4 +#define GC_RBOX_VERSION_CHANGE_OFFSET 0xa0 #define GC_RBOX_VERSION_REVISION_LSB 0x18 #define GC_RBOX_VERSION_REVISION_MASK 0xff000000 #define GC_RBOX_VERSION_REVISION_SIZE 0x8 -#define GC_RBOX_VERSION_REVISION_DEFAULT 0x2a -#define GC_RBOX_VERSION_REVISION_OFFSET 0x90 +#define GC_RBOX_VERSION_REVISION_DEFAULT 0x36 +#define GC_RBOX_VERSION_REVISION_OFFSET 0xa0 #define GC_RDD_VERSION_CHANGE_LSB 0x0 #define GC_RDD_VERSION_CHANGE_MASK 0xffffff #define GC_RDD_VERSION_CHANGE_SIZE 0x18 -#define GC_RDD_VERSION_CHANGE_DEFAULT 0xf210 +#define GC_RDD_VERSION_CHANGE_DEFAULT 0x11f09 #define GC_RDD_VERSION_CHANGE_OFFSET 0x0 #define GC_RDD_VERSION_REVISION_LSB 0x18 #define GC_RDD_VERSION_REVISION_MASK 0xff000000 #define GC_RDD_VERSION_REVISION_SIZE 0x8 -#define GC_RDD_VERSION_REVISION_DEFAULT 0x5 +#define GC_RDD_VERSION_REVISION_DEFAULT 0x24 #define GC_RDD_VERSION_REVISION_OFFSET 0x0 -#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_LSB 0x0 -#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_MASK 0x1 -#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_SIZE 0x1 -#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 -#define GC_RDD_INT_ENABLE_INTR_NEW_STATE_DETECTED_OFFSET 0x4 -#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_LSB 0x0 -#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_MASK 0x1 -#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_SIZE 0x1 -#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 -#define GC_RDD_INT_STATE_INTR_NEW_STATE_DETECTED_OFFSET 0x8 -#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_LSB 0x0 -#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_MASK 0x1 -#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_SIZE 0x1 -#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_DEFAULT 0x0 -#define GC_RDD_INT_TEST_INTR_NEW_STATE_DETECTED_OFFSET 0xc -#define GC_RDD_CUR_STABLE_STATE_OPEN_LSB 0x0 -#define GC_RDD_CUR_STABLE_STATE_OPEN_MASK 0x1 -#define GC_RDD_CUR_STABLE_STATE_OPEN_SIZE 0x1 -#define GC_RDD_CUR_STABLE_STATE_OPEN_DEFAULT 0x0 -#define GC_RDD_CUR_STABLE_STATE_OPEN_OFFSET 0x1c -#define GC_RDD_CUR_STABLE_STATE_DEBUG_LSB 0x1 -#define GC_RDD_CUR_STABLE_STATE_DEBUG_MASK 0x2 +#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_OFFSET 0x4 +#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_OFFSET 0x8 +#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_LSB 0x0 +#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_MASK 0x1 +#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_SIZE 0x1 +#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0 +#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_OFFSET 0xc +#define GC_RDD_ANTEST_EN_LSB 0x0 +#define GC_RDD_ANTEST_EN_MASK 0x1 +#define GC_RDD_ANTEST_EN_SIZE 0x1 +#define GC_RDD_ANTEST_EN_DEFAULT 0x0 +#define GC_RDD_ANTEST_EN_OFFSET 0x14 +#define GC_RDD_REF_ADJ_LVL0P2V_LSB 0x0 +#define GC_RDD_REF_ADJ_LVL0P2V_MASK 0x3 +#define GC_RDD_REF_ADJ_LVL0P2V_SIZE 0x2 +#define GC_RDD_REF_ADJ_LVL0P2V_DEFAULT 0x1 +#define GC_RDD_REF_ADJ_LVL0P2V_OFFSET 0x20 +#define GC_RDD_REF_ADJ_LVL0P4V_LSB 0x2 +#define GC_RDD_REF_ADJ_LVL0P4V_MASK 0xc +#define GC_RDD_REF_ADJ_LVL0P4V_SIZE 0x2 +#define GC_RDD_REF_ADJ_LVL0P4V_DEFAULT 0x1 +#define GC_RDD_REF_ADJ_LVL0P4V_OFFSET 0x20 +#define GC_RDD_REF_ADJ_LVL2P0V_LSB 0x4 +#define GC_RDD_REF_ADJ_LVL2P0V_MASK 0x30 +#define GC_RDD_REF_ADJ_LVL2P0V_SIZE 0x2 +#define GC_RDD_REF_ADJ_LVL2P0V_DEFAULT 0x1 +#define GC_RDD_REF_ADJ_LVL2P0V_OFFSET 0x20 +#define GC_RDD_INPUT_PIN_VALUES_CC1_LSB 0x0 +#define GC_RDD_INPUT_PIN_VALUES_CC1_MASK 0x7 +#define GC_RDD_INPUT_PIN_VALUES_CC1_SIZE 0x3 +#define GC_RDD_INPUT_PIN_VALUES_CC1_DEFAULT 0x0 +#define GC_RDD_INPUT_PIN_VALUES_CC1_OFFSET 0x24 +#define GC_RDD_INPUT_PIN_VALUES_CC2_LSB 0x3 +#define GC_RDD_INPUT_PIN_VALUES_CC2_MASK 0x38 +#define GC_RDD_INPUT_PIN_VALUES_CC2_SIZE 0x3 +#define GC_RDD_INPUT_PIN_VALUES_CC2_DEFAULT 0x3 +#define GC_RDD_INPUT_PIN_VALUES_CC2_OFFSET 0x24 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_LSB 0x0 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_MASK 0x1 #define GC_RDD_CUR_STABLE_STATE_DEBUG_SIZE 0x1 #define GC_RDD_CUR_STABLE_STATE_DEBUG_DEFAULT 0x0 -#define GC_RDD_CUR_STABLE_STATE_DEBUG_OFFSET 0x1c -#define GC_RDD_CUR_STABLE_STATE_INVALID_LSB 0x2 -#define GC_RDD_CUR_STABLE_STATE_INVALID_MASK 0x4 +#define GC_RDD_CUR_STABLE_STATE_DEBUG_OFFSET 0x2c +#define GC_RDD_CUR_STABLE_STATE_INVALID_LSB 0x1 +#define GC_RDD_CUR_STABLE_STATE_INVALID_MASK 0x2 #define GC_RDD_CUR_STABLE_STATE_INVALID_SIZE 0x1 #define GC_RDD_CUR_STABLE_STATE_INVALID_DEFAULT 0x1 -#define GC_RDD_CUR_STABLE_STATE_INVALID_OFFSET 0x1c -#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_LSB 0x3 -#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_MASK 0x8 -#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_SIZE 0x1 -#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_DEFAULT 0x0 -#define GC_RDD_CUR_STABLE_STATE_POWERED_CABLE_OFFSET 0x1c +#define GC_RDD_CUR_STABLE_STATE_INVALID_OFFSET 0x2c #define GC_RTC_CTRL_X_RTC_RC_CTRL_LSB 0x0 #define GC_RTC_CTRL_X_RTC_RC_CTRL_MASK 0xff #define GC_RTC_CTRL_X_RTC_RC_CTRL_SIZE 0x8 @@ -15227,6 +17189,11 @@ #define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_SIZE 0x4 #define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_DEFAULT 0x2 #define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_LSB 0xa +#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_MASK 0x400 +#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_DEFAULT 0x1 +#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_OFFSET 0x400 #define GC_SPS_BUSY_OPCODE0_EN_LSB 0x0 #define GC_SPS_BUSY_OPCODE0_EN_MASK 0x1 #define GC_SPS_BUSY_OPCODE0_EN_SIZE 0x1 @@ -15455,12 +17422,12 @@ #define GC_TEMP_VERSION_CHANGE_LSB 0x0 #define GC_TEMP_VERSION_CHANGE_MASK 0xffffff #define GC_TEMP_VERSION_CHANGE_SIZE 0x18 -#define GC_TEMP_VERSION_CHANGE_DEFAULT 0x10a2c +#define GC_TEMP_VERSION_CHANGE_DEFAULT 0x11f6d #define GC_TEMP_VERSION_CHANGE_OFFSET 0x0 #define GC_TEMP_VERSION_REVISION_LSB 0x18 #define GC_TEMP_VERSION_REVISION_MASK 0xff000000 #define GC_TEMP_VERSION_REVISION_SIZE 0x8 -#define GC_TEMP_VERSION_REVISION_DEFAULT 0x5 +#define GC_TEMP_VERSION_REVISION_DEFAULT 0x8 #define GC_TEMP_VERSION_REVISION_OFFSET 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK 0x1 @@ -15622,6 +17589,26 @@ #define GC_TEMP_METRIC_CTR_SIZE 0x14 #define GC_TEMP_METRIC_CTR_DEFAULT 0x0 #define GC_TEMP_METRIC_CTR_OFFSET 0x4c +#define GC_TEMP_ANTEST_EN_INPUTS_LSB 0x0 +#define GC_TEMP_ANTEST_EN_INPUTS_MASK 0x1 +#define GC_TEMP_ANTEST_EN_INPUTS_SIZE 0x1 +#define GC_TEMP_ANTEST_EN_INPUTS_DEFAULT 0x0 +#define GC_TEMP_ANTEST_EN_INPUTS_OFFSET 0x54 +#define GC_TEMP_ANTEST_EN_REF_LSB 0x1 +#define GC_TEMP_ANTEST_EN_REF_MASK 0x2 +#define GC_TEMP_ANTEST_EN_REF_SIZE 0x1 +#define GC_TEMP_ANTEST_EN_REF_DEFAULT 0x0 +#define GC_TEMP_ANTEST_EN_REF_OFFSET 0x54 +#define GC_TEMP_ANTEST_EN_VPTAT_LSB 0x2 +#define GC_TEMP_ANTEST_EN_VPTAT_MASK 0x4 +#define GC_TEMP_ANTEST_EN_VPTAT_SIZE 0x1 +#define GC_TEMP_ANTEST_EN_VPTAT_DEFAULT 0x0 +#define GC_TEMP_ANTEST_EN_VPTAT_OFFSET 0x54 +#define GC_TEMP_ANTEST_EN_CM_LSB 0x3 +#define GC_TEMP_ANTEST_EN_CM_MASK 0x8 +#define GC_TEMP_ANTEST_EN_CM_SIZE 0x1 +#define GC_TEMP_ANTEST_EN_CM_DEFAULT 0x0 +#define GC_TEMP_ANTEST_EN_CM_OFFSET 0x54 #define GC_TIMEHS_TIMER1CONTROL_ONESHOT_LSB 0x0 #define GC_TIMEHS_TIMER1CONTROL_ONESHOT_MASK 0x1 #define GC_TIMEHS_TIMER1CONTROL_ONESHOT_SIZE 0x1 @@ -15955,12 +17942,12 @@ #define GC_TRNG_VERSION_CHANGE_LSB 0x0 #define GC_TRNG_VERSION_CHANGE_MASK 0xffffff #define GC_TRNG_VERSION_CHANGE_SIZE 0x18 -#define GC_TRNG_VERSION_CHANGE_DEFAULT 0x10f59 +#define GC_TRNG_VERSION_CHANGE_DEFAULT 0x11f6d #define GC_TRNG_VERSION_CHANGE_OFFSET 0x0 #define GC_TRNG_VERSION_REVISION_LSB 0x18 #define GC_TRNG_VERSION_REVISION_MASK 0xff000000 #define GC_TRNG_VERSION_REVISION_SIZE 0x8 -#define GC_TRNG_VERSION_REVISION_DEFAULT 0x16 +#define GC_TRNG_VERSION_REVISION_DEFAULT 0x24 #define GC_TRNG_VERSION_REVISION_OFFSET 0x0 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB 0x0 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x1 @@ -16007,58 +17994,58 @@ #define GC_TRNG_INT_TEST_INTR_READ_EMPTY_SIZE 0x1 #define GC_TRNG_INT_TEST_INTR_READ_EMPTY_DEFAULT 0x0 #define GC_TRNG_INT_TEST_INTR_READ_EMPTY_OFFSET 0xc +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_LSB 0x0 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_MASK 0x1 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_SIZE 0x1 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_DEFAULT 0x1 +#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_OFFSET 0x10 #define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_LSB 0x0 #define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_MASK 0x1 #define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_SIZE 0x1 #define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_LSB 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_MASK 0x2 -#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_SIZE 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_MONOBIT_FREQ_COUNT_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_LSB 0x2 -#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_MASK 0x4 +#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_OFFSET 0x14 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_LSB 0x1 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_MASK 0x2 #define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_SIZE 0x1 #define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_LSB 0x3 -#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_MASK 0x8 +#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_OFFSET 0x14 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_LSB 0x2 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_MASK 0x4 #define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_SIZE 0x1 #define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_LSB 0x4 -#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_MASK 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_SIZE 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_OFFSET 0x10 -#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_LSB 0x5 -#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_MASK 0x20 +#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_OFFSET 0x14 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_LSB 0x3 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_MASK 0x8 #define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_SIZE 0x1 #define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_DEFAULT 0x1 -#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_OFFSET 0x10 +#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_OFFSET 0x14 #define GC_TRNG_FSM_STATE_FSM_IDLE_LSB 0x0 #define GC_TRNG_FSM_STATE_FSM_IDLE_MASK 0x1 #define GC_TRNG_FSM_STATE_FSM_IDLE_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_IDLE_DEFAULT 0x1 #define GC_TRNG_FSM_STATE_FSM_IDLE_OFFSET 0x2c -#define GC_TRNG_FSM_STATE_FSM_WAIT_LSB 0x1 -#define GC_TRNG_FSM_STATE_FSM_WAIT_MASK 0x2 +#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_LSB 0x1 +#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_MASK 0x2 +#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_SIZE 0x1 +#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_DEFAULT 0x0 +#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_OFFSET 0x2c +#define GC_TRNG_FSM_STATE_FSM_WAIT_LSB 0x2 +#define GC_TRNG_FSM_STATE_FSM_WAIT_MASK 0x4 #define GC_TRNG_FSM_STATE_FSM_WAIT_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_WAIT_DEFAULT 0x0 #define GC_TRNG_FSM_STATE_FSM_WAIT_OFFSET 0x2c -#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_LSB 0x2 -#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_MASK 0x4 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_LSB 0x3 +#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_MASK 0x8 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_DEFAULT 0x0 #define GC_TRNG_FSM_STATE_FSM_TIMEOUT_OFFSET 0x2c -#define GC_TRNG_FSM_STATE_FSM_CAPTURE_LSB 0x3 -#define GC_TRNG_FSM_STATE_FSM_CAPTURE_MASK 0x8 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_LSB 0x4 +#define GC_TRNG_FSM_STATE_FSM_CAPTURE_MASK 0x10 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_DEFAULT 0x0 #define GC_TRNG_FSM_STATE_FSM_CAPTURE_OFFSET 0x2c -#define GC_TRNG_FSM_STATE_FSM_FULL_LSB 0x4 -#define GC_TRNG_FSM_STATE_FSM_FULL_MASK 0x10 +#define GC_TRNG_FSM_STATE_FSM_FULL_LSB 0x5 +#define GC_TRNG_FSM_STATE_FSM_FULL_MASK 0x20 #define GC_TRNG_FSM_STATE_FSM_FULL_SIZE 0x1 #define GC_TRNG_FSM_STATE_FSM_FULL_DEFAULT 0x0 #define GC_TRNG_FSM_STATE_FSM_FULL_OFFSET 0x2c @@ -16072,6 +18059,66 @@ #define GC_TRNG_ALLOWED_VALUES_MAX_SIZE 0x3 #define GC_TRNG_ALLOWED_VALUES_MAX_DEFAULT 0x4 #define GC_TRNG_ALLOWED_VALUES_MAX_OFFSET 0x30 +#define GC_TRNG_ANTEST_VLDO_EN_LSB 0x0 +#define GC_TRNG_ANTEST_VLDO_EN_MASK 0x1 +#define GC_TRNG_ANTEST_VLDO_EN_SIZE 0x1 +#define GC_TRNG_ANTEST_VLDO_EN_DEFAULT 0x0 +#define GC_TRNG_ANTEST_VLDO_EN_OFFSET 0x50 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_LSB 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_MASK 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_DEFAULT 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_LSB 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_MASK 0x2 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_DEFAULT 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_LSB 0x2 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_MASK 0x4 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_DEFAULT 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_LSB 0x3 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_MASK 0x8 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_DEFAULT 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_LSB 0x4 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_MASK 0x10 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_DEFAULT 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_OFFSET 0x54 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_LSB 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_MASK 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_SIZE 0x1 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_DEFAULT 0x0 +#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_OFFSET 0x58 +#define GC_TRNG_ANALOG_TEST_DIV_EN_LSB 0x0 +#define GC_TRNG_ANALOG_TEST_DIV_EN_MASK 0x1 +#define GC_TRNG_ANALOG_TEST_DIV_EN_SIZE 0x1 +#define GC_TRNG_ANALOG_TEST_DIV_EN_DEFAULT 0x0 +#define GC_TRNG_ANALOG_TEST_DIV_EN_OFFSET 0x5c +#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_LSB 0x1 +#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_MASK 0x2 +#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_SIZE 0x1 +#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_DEFAULT 0x0 +#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_OFFSET 0x5c +#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_LSB 0x0 +#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_MASK 0x1 +#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_SIZE 0x1 +#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_DEFAULT 0x0 +#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_OFFSET 0x60 +#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_LSB 0x1 +#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_MASK 0x2 +#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_SIZE 0x1 +#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_DEFAULT 0x0 +#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_OFFSET 0x60 +#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_LSB 0x2 +#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_MASK 0xc +#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_SIZE 0x2 +#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_DEFAULT 0x0 +#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_OFFSET 0x60 #define GC_UART_CTRL_TX_LSB 0x0 #define GC_UART_CTRL_TX_MASK 0x1 #define GC_UART_CTRL_TX_SIZE 0x1 @@ -23075,12 +25122,12 @@ #define GC_VOLT_VERSION_CHANGE_LSB 0x0 #define GC_VOLT_VERSION_CHANGE_MASK 0xffffff #define GC_VOLT_VERSION_CHANGE_SIZE 0x18 -#define GC_VOLT_VERSION_CHANGE_DEFAULT 0x10ae0 +#define GC_VOLT_VERSION_CHANGE_DEFAULT 0x11f6d #define GC_VOLT_VERSION_CHANGE_OFFSET 0x0 #define GC_VOLT_VERSION_REVISION_LSB 0x18 #define GC_VOLT_VERSION_REVISION_MASK 0xff000000 #define GC_VOLT_VERSION_REVISION_SIZE 0x8 -#define GC_VOLT_VERSION_REVISION_DEFAULT 0x2 +#define GC_VOLT_VERSION_REVISION_DEFAULT 0x4 #define GC_VOLT_VERSION_REVISION_OFFSET 0x0 #define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_LSB 0x0 #define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_MASK 0x1 @@ -23135,963 +25182,1358 @@ #define GC_XO_VERSION_CHANGE_LSB 0x0 #define GC_XO_VERSION_CHANGE_MASK 0xffffff #define GC_XO_VERSION_CHANGE_SIZE 0x18 -#define GC_XO_VERSION_CHANGE_DEFAULT 0x10370 +#define GC_XO_VERSION_CHANGE_DEFAULT 0x11e43 #define GC_XO_VERSION_CHANGE_OFFSET 0x0 #define GC_XO_VERSION_REVISION_LSB 0x18 #define GC_XO_VERSION_REVISION_MASK 0xff000000 #define GC_XO_VERSION_REVISION_SIZE 0x8 -#define GC_XO_VERSION_REVISION_DEFAULT 0x14 +#define GC_XO_VERSION_REVISION_DEFAULT 0x15 #define GC_XO_VERSION_REVISION_OFFSET 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK 0x1 #define GC_XO_CLK_JTR_CTRL_HS_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CTRL_HS_SEL_DEFAULT 0x1 -#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET 0x4 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET 0x8 #define GC_XO_CLK_JTR_CTRL_SEL_LSB 0x1 #define GC_XO_CLK_JTR_CTRL_SEL_MASK 0x2 #define GC_XO_CLK_JTR_CTRL_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CTRL_SEL_DEFAULT 0x1 -#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET 0x4 +#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET 0x8 #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_LSB 0x0 #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_MASK 0xff #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_SIZE 0x8 #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x10 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x14 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_LSB 0x8 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_MASK 0xff00 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_SIZE 0x8 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET 0x10 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET 0x14 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x1c #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x1c #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x1c #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x18 +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x1c #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x70 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x70 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x70 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x70 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x6c +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x70 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x7c +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x80 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x84 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x88 #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x8c #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x90 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x94 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x98 #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0x9c #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0xa0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0xa0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xc0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xc0 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc0 +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc4 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xc8 #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xcc #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xd0 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd4 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xd8 #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xdc #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xe0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x104 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x104 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_LSB 0x0 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_MASK 0xffffff #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_SIZE 0x18 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x108 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x10c #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_LSB 0x18 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_MASK 0x1000000 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_SIZE 0x1 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x108 +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x10c #define GC_XO_CLK_TIMER_CTRL_HS_SEL_LSB 0x0 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_MASK 0x1 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_DEFAULT 0x1 -#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET 0x110 #define GC_XO_CLK_TIMER_CTRL_SEL_LSB 0x1 #define GC_XO_CLK_TIMER_CTRL_SEL_MASK 0x2 #define GC_XO_CLK_TIMER_CTRL_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CTRL_SEL_DEFAULT 0x1 -#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET 0x10c +#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET 0x110 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_LSB 0x0 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_MASK 0xff #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_SIZE 0x8 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x118 +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x11c #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_LSB 0x8 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_MASK 0xff00 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_SIZE 0x8 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x118 +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x11c #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x124 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x124 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x124 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x120 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x124 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x124 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x128 #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x134 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x138 #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x13c #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x140 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x144 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x148 #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x14c #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x150 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x154 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x158 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x158 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x178 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x178 #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x178 +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x17c #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x180 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x184 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x188 #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x18c #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x190 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x194 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x198 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x19c #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x19c #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_LSB 0x0 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_MASK 0xffffff #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_SIZE 0x18 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c4 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_LSB 0x18 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_MASK 0x1000000 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_SIZE 0x1 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c4 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_LSB 0x0 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_MASK 0xf #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_SIZE 0x4 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_DEFAULT 0x6 -#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET 0x1c8 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_LSB 0x4 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_MASK 0x10 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET 0x1c8 #define GC_XO_OSC_XTL_FREQ2X_SELB_LSB 0x5 #define GC_XO_OSC_XTL_FREQ2X_SELB_MASK 0x20 #define GC_XO_OSC_XTL_FREQ2X_SELB_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_SELB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET 0x1c4 +#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET 0x1c8 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_LSB 0x0 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_MASK 0xf #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_SIZE 0x4 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_DEFAULT 0x6 -#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_LSB 0x4 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_MASK 0x10 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_LSB 0x5 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_MASK 0x20 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET 0x1cc #define GC_XO_OSC_XTL_RC_FLTR_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_MASK 0xf #define GC_XO_OSC_XTL_RC_FLTR_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_DEFAULT 0x5 -#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x1d8 +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x1dc #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_LSB 0x4 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_MASK 0x10 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_SIZE 0x1 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_DEFAULT 0x1 -#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x1d8 +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x1dc #define GC_XO_OSC_XTL_OVRD_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_OVRD_TRIM_MASK 0xf #define GC_XO_OSC_XTL_OVRD_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_OVRD_TRIM_DEFAULT 0x7 -#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x1dc +#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x1e0 #define GC_XO_OSC_XTL_OVRD_ENB_LSB 0x4 #define GC_XO_OSC_XTL_OVRD_ENB_MASK 0x10 #define GC_XO_OSC_XTL_OVRD_ENB_SIZE 0x1 #define GC_XO_OSC_XTL_OVRD_ENB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x1dc +#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x1e0 #define GC_XO_OSC_XTL_TRIM_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x1e4 +#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x1e8 #define GC_XO_OSC_XTL_TRIM_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x1e4 +#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x1e8 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_STAT_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x1ec #define GC_XO_OSC_XTL_TRIM_STAT_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_STAT_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_STAT_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x1ec #define GC_XO_OSC_XTL_FSM_DONE_LSB 0x0 #define GC_XO_OSC_XTL_FSM_DONE_MASK 0x1 #define GC_XO_OSC_XTL_FSM_DONE_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_DONE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_TRIM_LSB 0x1 #define GC_XO_OSC_XTL_FSM_TRIM_MASK 0x1e #define GC_XO_OSC_XTL_FSM_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_STATUS_LSB 0x5 #define GC_XO_OSC_XTL_FSM_STATUS_MASK 0x20 #define GC_XO_OSC_XTL_FSM_STATUS_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_STATUS_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_STATE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_STATE_MASK 0x3c0 #define GC_XO_OSC_XTL_FSM_STATE_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_STATE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_LSB 0xa #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_MASK 0x400 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_LSB 0x0 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_MASK 0xf #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_DEFAULT 0x8 -#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_LSB 0x4 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_MASK 0x30 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_MASK 0xc0 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_DEFAULT 0x2 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_LSB 0x8 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_MASK 0x700 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_SIZE 0x3 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_DEFAULT 0x4 -#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_LSB 0xb #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_MASK 0xf800 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_DEFAULT 0xe -#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_LSB 0x10 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_MASK 0x1f0000 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd -#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x1fc #define GC_XO_OSC_SETHOLD_XTL_LSB 0x0 #define GC_XO_OSC_SETHOLD_XTL_MASK 0x1 #define GC_XO_OSC_SETHOLD_XTL_SIZE 0x1 #define GC_XO_OSC_SETHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x1fc +#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x200 #define GC_XO_OSC_SETHOLD_ANA_LSB 0x1 #define GC_XO_OSC_SETHOLD_ANA_MASK 0x2 #define GC_XO_OSC_SETHOLD_ANA_SIZE 0x1 #define GC_XO_OSC_SETHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x1fc +#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x200 #define GC_XO_OSC_CLRHOLD_XTL_LSB 0x0 #define GC_XO_OSC_CLRHOLD_XTL_MASK 0x1 #define GC_XO_OSC_CLRHOLD_XTL_SIZE 0x1 #define GC_XO_OSC_CLRHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x200 +#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x204 #define GC_XO_OSC_CLRHOLD_ANA_LSB 0x1 #define GC_XO_OSC_CLRHOLD_ANA_MASK 0x2 #define GC_XO_OSC_CLRHOLD_ANA_SIZE 0x1 #define GC_XO_OSC_CLRHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x200 +#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x204 #define GC_XO_OSC_TEST_CLK2X_EN_LSB 0x0 #define GC_XO_OSC_TEST_CLK2X_EN_MASK 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x204 +#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x208 #define GC_XO_OSC_TEST_CLK_JTR_EN_LSB 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_MASK 0x2 #define GC_XO_OSC_TEST_CLK_JTR_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x204 +#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x208 #define GC_XO_OSC_TEST_CLK_TIMER_EN_LSB 0x2 #define GC_XO_OSC_TEST_CLK_TIMER_EN_MASK 0x4 #define GC_XO_OSC_TEST_CLK_TIMER_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_TIMER_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x204 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x20c #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x208 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x210 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x214 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x210 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x214 +#define GC_M3_ITM_TCR_ITMENA_LSB 0x0 +#define GC_M3_ITM_TCR_ITMENA_MASK 0x1 +#define GC_M3_ITM_TCR_ITMENA_SIZE 0x1 +#define GC_M3_ITM_TCR_ITMENA_DEFAULT 0x0 +#define GC_M3_ITM_TCR_ITMENA_OFFSET 0xe80 +#define GC_M3_ITM_TCR_TSENA_LSB 0x1 +#define GC_M3_ITM_TCR_TSENA_MASK 0x2 +#define GC_M3_ITM_TCR_TSENA_SIZE 0x1 +#define GC_M3_ITM_TCR_TSENA_DEFAULT 0x0 +#define GC_M3_ITM_TCR_TSENA_OFFSET 0xe80 +#define GC_M3_ITM_TCR_SYNCENA_LSB 0x2 +#define GC_M3_ITM_TCR_SYNCENA_MASK 0x4 +#define GC_M3_ITM_TCR_SYNCENA_SIZE 0x1 +#define GC_M3_ITM_TCR_SYNCENA_DEFAULT 0x0 +#define GC_M3_ITM_TCR_SYNCENA_OFFSET 0xe80 +#define GC_M3_ITM_TCR_DWTENA_LSB 0x3 +#define GC_M3_ITM_TCR_DWTENA_MASK 0x8 +#define GC_M3_ITM_TCR_DWTENA_SIZE 0x1 +#define GC_M3_ITM_TCR_DWTENA_DEFAULT 0x0 +#define GC_M3_ITM_TCR_DWTENA_OFFSET 0xe80 +#define GC_M3_ITM_TCR_SWOENA_LSB 0x4 +#define GC_M3_ITM_TCR_SWOENA_MASK 0x10 +#define GC_M3_ITM_TCR_SWOENA_SIZE 0x1 +#define GC_M3_ITM_TCR_SWOENA_DEFAULT 0x0 +#define GC_M3_ITM_TCR_SWOENA_OFFSET 0xe80 +#define GC_M3_ITM_TCR_TSPRESCALE_LSB 0x8 +#define GC_M3_ITM_TCR_TSPRESCALE_MASK 0x300 +#define GC_M3_ITM_TCR_TSPRESCALE_SIZE 0x2 +#define GC_M3_ITM_TCR_TSPRESCALE_DEFAULT 0x0 +#define GC_M3_ITM_TCR_TSPRESCALE_OFFSET 0xe80 +#define GC_M3_ITM_TCR_ATBID_LSB 0x10 +#define GC_M3_ITM_TCR_ATBID_MASK 0x7f0000 +#define GC_M3_ITM_TCR_ATBID_SIZE 0x7 +#define GC_M3_ITM_TCR_ATBID_DEFAULT 0x0 +#define GC_M3_ITM_TCR_ATBID_OFFSET 0xe80 +#define GC_M3_ITM_TCR_BUSY_LSB 0x17 +#define GC_M3_ITM_TCR_BUSY_MASK 0x800000 +#define GC_M3_ITM_TCR_BUSY_SIZE 0x1 +#define GC_M3_ITM_TCR_BUSY_DEFAULT 0x0 +#define GC_M3_ITM_TCR_BUSY_OFFSET 0xe80 +#define GC_M3_ITM_LOCKSREG_PRESENT_LSB 0x0 +#define GC_M3_ITM_LOCKSREG_PRESENT_MASK 0x1 +#define GC_M3_ITM_LOCKSREG_PRESENT_SIZE 0x1 +#define GC_M3_ITM_LOCKSREG_PRESENT_DEFAULT 0x0 +#define GC_M3_ITM_LOCKSREG_PRESENT_OFFSET 0xfb4 +#define GC_M3_ITM_LOCKSREG_ACCESS_LSB 0x1 +#define GC_M3_ITM_LOCKSREG_ACCESS_MASK 0x2 +#define GC_M3_ITM_LOCKSREG_ACCESS_SIZE 0x1 +#define GC_M3_ITM_LOCKSREG_ACCESS_DEFAULT 0x0 +#define GC_M3_ITM_LOCKSREG_ACCESS_OFFSET 0xfb4 +#define GC_M3_ITM_LOCKSREG_BYTEACC_LSB 0x2 +#define GC_M3_ITM_LOCKSREG_BYTEACC_MASK 0x4 +#define GC_M3_ITM_LOCKSREG_BYTEACC_SIZE 0x1 +#define GC_M3_ITM_LOCKSREG_BYTEACC_DEFAULT 0x0 +#define GC_M3_ITM_LOCKSREG_BYTEACC_OFFSET 0xfb4 +#define GC_M3_DWT_CTRL_CYCCNTENA_LSB 0x0 +#define GC_M3_DWT_CTRL_CYCCNTENA_MASK 0x1 +#define GC_M3_DWT_CTRL_CYCCNTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_CYCCNTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_CYCCNTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_POSTRESET_LSB 0x1 +#define GC_M3_DWT_CTRL_POSTRESET_MASK 0x1e +#define GC_M3_DWT_CTRL_POSTRESET_SIZE 0x4 +#define GC_M3_DWT_CTRL_POSTRESET_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_POSTRESET_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_POSTCNT_LSB 0x5 +#define GC_M3_DWT_CTRL_POSTCNT_MASK 0x1e0 +#define GC_M3_DWT_CTRL_POSTCNT_SIZE 0x4 +#define GC_M3_DWT_CTRL_POSTCNT_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_POSTCNT_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_CYCTAP_LSB 0x9 +#define GC_M3_DWT_CTRL_CYCTAP_MASK 0x200 +#define GC_M3_DWT_CTRL_CYCTAP_SIZE 0x1 +#define GC_M3_DWT_CTRL_CYCTAP_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_CYCTAP_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_SYNCTAP_LSB 0xa +#define GC_M3_DWT_CTRL_SYNCTAP_MASK 0xc00 +#define GC_M3_DWT_CTRL_SYNCTAP_SIZE 0x2 +#define GC_M3_DWT_CTRL_SYNCTAP_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_SYNCTAP_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_PCSAMPLENA_LSB 0xc +#define GC_M3_DWT_CTRL_PCSAMPLENA_MASK 0x1000 +#define GC_M3_DWT_CTRL_PCSAMPLENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_PCSAMPLENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_PCSAMPLENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_EXCTRCENA_LSB 0x10 +#define GC_M3_DWT_CTRL_EXCTRCENA_MASK 0x10000 +#define GC_M3_DWT_CTRL_EXCTRCENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_EXCTRCENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_EXCTRCENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_CPIEVTENA_LSB 0x11 +#define GC_M3_DWT_CTRL_CPIEVTENA_MASK 0x20000 +#define GC_M3_DWT_CTRL_CPIEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_CPIEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_CPIEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_EXCEVTENA_LSB 0x12 +#define GC_M3_DWT_CTRL_EXCEVTENA_MASK 0x40000 +#define GC_M3_DWT_CTRL_EXCEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_EXCEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_EXCEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_SLEEPEVTENA_LSB 0x13 +#define GC_M3_DWT_CTRL_SLEEPEVTENA_MASK 0x80000 +#define GC_M3_DWT_CTRL_SLEEPEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_SLEEPEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_SLEEPEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_LSUEVTENA_LSB 0x14 +#define GC_M3_DWT_CTRL_LSUEVTENA_MASK 0x100000 +#define GC_M3_DWT_CTRL_LSUEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_LSUEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_LSUEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_FOLDEVTENA_LSB 0x15 +#define GC_M3_DWT_CTRL_FOLDEVTENA_MASK 0x200000 +#define GC_M3_DWT_CTRL_FOLDEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_FOLDEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_FOLDEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_CYCEVTENA_LSB 0x16 +#define GC_M3_DWT_CTRL_CYCEVTENA_MASK 0x400000 +#define GC_M3_DWT_CTRL_CYCEVTENA_SIZE 0x1 +#define GC_M3_DWT_CTRL_CYCEVTENA_DEFAULT 0x0 +#define GC_M3_DWT_CTRL_CYCEVTENA_OFFSET 0x1000 +#define GC_M3_DWT_CTRL_NUMCOMP_LSB 0x1c +#define GC_M3_DWT_CTRL_NUMCOMP_MASK 0xf0000000 +#define GC_M3_DWT_CTRL_NUMCOMP_SIZE 0x4 +#define GC_M3_DWT_CTRL_NUMCOMP_DEFAULT 0x4 +#define GC_M3_DWT_CTRL_NUMCOMP_OFFSET 0x1000 +#define GC_M3_DWT_FUNCTION0_FUNCTION_LSB 0x0 +#define GC_M3_DWT_FUNCTION0_FUNCTION_MASK 0xf +#define GC_M3_DWT_FUNCTION0_FUNCTION_SIZE 0x4 +#define GC_M3_DWT_FUNCTION0_FUNCTION_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_FUNCTION_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_EMITRANGE_LSB 0x5 +#define GC_M3_DWT_FUNCTION0_EMITRANGE_MASK 0x20 +#define GC_M3_DWT_FUNCTION0_EMITRANGE_SIZE 0x1 +#define GC_M3_DWT_FUNCTION0_EMITRANGE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_EMITRANGE_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_CYCMATCH_LSB 0x7 +#define GC_M3_DWT_FUNCTION0_CYCMATCH_MASK 0x80 +#define GC_M3_DWT_FUNCTION0_CYCMATCH_SIZE 0x1 +#define GC_M3_DWT_FUNCTION0_CYCMATCH_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_CYCMATCH_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_LNK1ENA_LSB 0x9 +#define GC_M3_DWT_FUNCTION0_LNK1ENA_MASK 0x200 +#define GC_M3_DWT_FUNCTION0_LNK1ENA_SIZE 0x1 +#define GC_M3_DWT_FUNCTION0_LNK1ENA_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_LNK1ENA_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_DATAVSIZE_LSB 0xa +#define GC_M3_DWT_FUNCTION0_DATAVSIZE_MASK 0xc00 +#define GC_M3_DWT_FUNCTION0_DATAVSIZE_SIZE 0x2 +#define GC_M3_DWT_FUNCTION0_DATAVSIZE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_DATAVSIZE_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION0_MATCHED_LSB 0x18 +#define GC_M3_DWT_FUNCTION0_MATCHED_MASK 0x1000000 +#define GC_M3_DWT_FUNCTION0_MATCHED_SIZE 0x1 +#define GC_M3_DWT_FUNCTION0_MATCHED_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION0_MATCHED_OFFSET 0x1028 +#define GC_M3_DWT_FUNCTION1_FUNCTION_LSB 0x0 +#define GC_M3_DWT_FUNCTION1_FUNCTION_MASK 0xf +#define GC_M3_DWT_FUNCTION1_FUNCTION_SIZE 0x4 +#define GC_M3_DWT_FUNCTION1_FUNCTION_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_FUNCTION_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_EMITRANGE_LSB 0x5 +#define GC_M3_DWT_FUNCTION1_EMITRANGE_MASK 0x20 +#define GC_M3_DWT_FUNCTION1_EMITRANGE_SIZE 0x1 +#define GC_M3_DWT_FUNCTION1_EMITRANGE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_EMITRANGE_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_DATAVMATCH_LSB 0x8 +#define GC_M3_DWT_FUNCTION1_DATAVMATCH_MASK 0x100 +#define GC_M3_DWT_FUNCTION1_DATAVMATCH_SIZE 0x1 +#define GC_M3_DWT_FUNCTION1_DATAVMATCH_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_DATAVMATCH_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_LNK1ENA_LSB 0x9 +#define GC_M3_DWT_FUNCTION1_LNK1ENA_MASK 0x200 +#define GC_M3_DWT_FUNCTION1_LNK1ENA_SIZE 0x1 +#define GC_M3_DWT_FUNCTION1_LNK1ENA_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_LNK1ENA_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_DATAVSIZE_LSB 0xa +#define GC_M3_DWT_FUNCTION1_DATAVSIZE_MASK 0xc00 +#define GC_M3_DWT_FUNCTION1_DATAVSIZE_SIZE 0x2 +#define GC_M3_DWT_FUNCTION1_DATAVSIZE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_DATAVSIZE_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_DATAVADDR0_LSB 0xc +#define GC_M3_DWT_FUNCTION1_DATAVADDR0_MASK 0xf000 +#define GC_M3_DWT_FUNCTION1_DATAVADDR0_SIZE 0x4 +#define GC_M3_DWT_FUNCTION1_DATAVADDR0_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_DATAVADDR0_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_DATAVADDR1_LSB 0x10 +#define GC_M3_DWT_FUNCTION1_DATAVADDR1_MASK 0xf0000 +#define GC_M3_DWT_FUNCTION1_DATAVADDR1_SIZE 0x4 +#define GC_M3_DWT_FUNCTION1_DATAVADDR1_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_DATAVADDR1_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION1_MATCHED_LSB 0x18 +#define GC_M3_DWT_FUNCTION1_MATCHED_MASK 0x1000000 +#define GC_M3_DWT_FUNCTION1_MATCHED_SIZE 0x1 +#define GC_M3_DWT_FUNCTION1_MATCHED_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION1_MATCHED_OFFSET 0x1038 +#define GC_M3_DWT_FUNCTION2_FUNCTION_LSB 0x0 +#define GC_M3_DWT_FUNCTION2_FUNCTION_MASK 0xf +#define GC_M3_DWT_FUNCTION2_FUNCTION_SIZE 0x4 +#define GC_M3_DWT_FUNCTION2_FUNCTION_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_FUNCTION_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION2_EMITRANGE_LSB 0x5 +#define GC_M3_DWT_FUNCTION2_EMITRANGE_MASK 0x20 +#define GC_M3_DWT_FUNCTION2_EMITRANGE_SIZE 0x1 +#define GC_M3_DWT_FUNCTION2_EMITRANGE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_EMITRANGE_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION2_LNK1ENA_LSB 0x9 +#define GC_M3_DWT_FUNCTION2_LNK1ENA_MASK 0x200 +#define GC_M3_DWT_FUNCTION2_LNK1ENA_SIZE 0x1 +#define GC_M3_DWT_FUNCTION2_LNK1ENA_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_LNK1ENA_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION2_DATAVSIZE_LSB 0xa +#define GC_M3_DWT_FUNCTION2_DATAVSIZE_MASK 0xc00 +#define GC_M3_DWT_FUNCTION2_DATAVSIZE_SIZE 0x2 +#define GC_M3_DWT_FUNCTION2_DATAVSIZE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_DATAVSIZE_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION2_MATCHED_LSB 0x18 +#define GC_M3_DWT_FUNCTION2_MATCHED_MASK 0x1000000 +#define GC_M3_DWT_FUNCTION2_MATCHED_SIZE 0x1 +#define GC_M3_DWT_FUNCTION2_MATCHED_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION2_MATCHED_OFFSET 0x1048 +#define GC_M3_DWT_FUNCTION3_FUNCTION_LSB 0x0 +#define GC_M3_DWT_FUNCTION3_FUNCTION_MASK 0xf +#define GC_M3_DWT_FUNCTION3_FUNCTION_SIZE 0x4 +#define GC_M3_DWT_FUNCTION3_FUNCTION_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_FUNCTION_OFFSET 0x1058 +#define GC_M3_DWT_FUNCTION3_EMITRANGE_LSB 0x5 +#define GC_M3_DWT_FUNCTION3_EMITRANGE_MASK 0x20 +#define GC_M3_DWT_FUNCTION3_EMITRANGE_SIZE 0x1 +#define GC_M3_DWT_FUNCTION3_EMITRANGE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_EMITRANGE_OFFSET 0x1058 +#define GC_M3_DWT_FUNCTION3_LNK1ENA_LSB 0x9 +#define GC_M3_DWT_FUNCTION3_LNK1ENA_MASK 0x200 +#define GC_M3_DWT_FUNCTION3_LNK1ENA_SIZE 0x1 +#define GC_M3_DWT_FUNCTION3_LNK1ENA_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_LNK1ENA_OFFSET 0x1058 +#define GC_M3_DWT_FUNCTION3_DATAVSIZE_LSB 0xa +#define GC_M3_DWT_FUNCTION3_DATAVSIZE_MASK 0xc00 +#define GC_M3_DWT_FUNCTION3_DATAVSIZE_SIZE 0x2 +#define GC_M3_DWT_FUNCTION3_DATAVSIZE_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_DATAVSIZE_OFFSET 0x1058 +#define GC_M3_DWT_FUNCTION3_MATCHED_LSB 0x18 +#define GC_M3_DWT_FUNCTION3_MATCHED_MASK 0x1000000 +#define GC_M3_DWT_FUNCTION3_MATCHED_SIZE 0x1 +#define GC_M3_DWT_FUNCTION3_MATCHED_DEFAULT 0x0 +#define GC_M3_DWT_FUNCTION3_MATCHED_OFFSET 0x1058 +#define GC_M3_FP_CTRL_ENABLE_LSB 0x0 +#define GC_M3_FP_CTRL_ENABLE_MASK 0x1 +#define GC_M3_FP_CTRL_ENABLE_SIZE 0x1 +#define GC_M3_FP_CTRL_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_CTRL_ENABLE_OFFSET 0x2000 +#define GC_M3_FP_CTRL_KEY_LSB 0x1 +#define GC_M3_FP_CTRL_KEY_MASK 0x2 +#define GC_M3_FP_CTRL_KEY_SIZE 0x1 +#define GC_M3_FP_CTRL_KEY_DEFAULT 0x0 +#define GC_M3_FP_CTRL_KEY_OFFSET 0x2000 +#define GC_M3_FP_CTRL_NUM_CODE1_LSB 0x4 +#define GC_M3_FP_CTRL_NUM_CODE1_MASK 0xf0 +#define GC_M3_FP_CTRL_NUM_CODE1_SIZE 0x4 +#define GC_M3_FP_CTRL_NUM_CODE1_DEFAULT 0x6 +#define GC_M3_FP_CTRL_NUM_CODE1_OFFSET 0x2000 +#define GC_M3_FP_CTRL_NUM_LIT_LSB 0x8 +#define GC_M3_FP_CTRL_NUM_LIT_MASK 0xf00 +#define GC_M3_FP_CTRL_NUM_LIT_SIZE 0x4 +#define GC_M3_FP_CTRL_NUM_LIT_DEFAULT 0x2 +#define GC_M3_FP_CTRL_NUM_LIT_OFFSET 0x2000 +#define GC_M3_FP_CTRL_NUM_CODE2_LSB 0xc +#define GC_M3_FP_CTRL_NUM_CODE2_MASK 0x3000 +#define GC_M3_FP_CTRL_NUM_CODE2_SIZE 0x2 +#define GC_M3_FP_CTRL_NUM_CODE2_DEFAULT 0x0 +#define GC_M3_FP_CTRL_NUM_CODE2_OFFSET 0x2000 +#define GC_M3_FP_REMAP_REMAP_LSB 0x5 +#define GC_M3_FP_REMAP_REMAP_MASK 0x1fffffe0 +#define GC_M3_FP_REMAP_REMAP_SIZE 0x18 +#define GC_M3_FP_REMAP_REMAP_DEFAULT 0x0 +#define GC_M3_FP_REMAP_REMAP_OFFSET 0x2004 +#define GC_M3_FP_COMP0_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP0_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP0_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP0_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP0_ENABLE_OFFSET 0x2008 +#define GC_M3_FP_COMP0_COMP_LSB 0x2 +#define GC_M3_FP_COMP0_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP0_COMP_SIZE 0x1b +#define GC_M3_FP_COMP0_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP0_COMP_OFFSET 0x2008 +#define GC_M3_FP_COMP0_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP0_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP0_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP0_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP0_REPLACE_OFFSET 0x2008 +#define GC_M3_FP_COMP1_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP1_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP1_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP1_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP1_ENABLE_OFFSET 0x200c +#define GC_M3_FP_COMP1_COMP_LSB 0x2 +#define GC_M3_FP_COMP1_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP1_COMP_SIZE 0x1b +#define GC_M3_FP_COMP1_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP1_COMP_OFFSET 0x200c +#define GC_M3_FP_COMP1_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP1_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP1_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP1_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP1_REPLACE_OFFSET 0x200c +#define GC_M3_FP_COMP2_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP2_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP2_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP2_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP2_ENABLE_OFFSET 0x2010 +#define GC_M3_FP_COMP2_COMP_LSB 0x2 +#define GC_M3_FP_COMP2_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP2_COMP_SIZE 0x1b +#define GC_M3_FP_COMP2_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP2_COMP_OFFSET 0x2010 +#define GC_M3_FP_COMP2_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP2_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP2_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP2_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP2_REPLACE_OFFSET 0x2010 +#define GC_M3_FP_COMP3_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP3_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP3_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP3_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP3_ENABLE_OFFSET 0x2014 +#define GC_M3_FP_COMP3_COMP_LSB 0x2 +#define GC_M3_FP_COMP3_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP3_COMP_SIZE 0x1b +#define GC_M3_FP_COMP3_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP3_COMP_OFFSET 0x2014 +#define GC_M3_FP_COMP3_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP3_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP3_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP3_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP3_REPLACE_OFFSET 0x2014 +#define GC_M3_FP_COMP4_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP4_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP4_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP4_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP4_ENABLE_OFFSET 0x2018 +#define GC_M3_FP_COMP4_COMP_LSB 0x2 +#define GC_M3_FP_COMP4_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP4_COMP_SIZE 0x1b +#define GC_M3_FP_COMP4_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP4_COMP_OFFSET 0x2018 +#define GC_M3_FP_COMP4_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP4_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP4_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP4_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP4_REPLACE_OFFSET 0x2018 +#define GC_M3_FP_COMP5_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP5_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP5_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP5_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP5_ENABLE_OFFSET 0x201c +#define GC_M3_FP_COMP5_COMP_LSB 0x2 +#define GC_M3_FP_COMP5_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP5_COMP_SIZE 0x1b +#define GC_M3_FP_COMP5_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP5_COMP_OFFSET 0x201c +#define GC_M3_FP_COMP5_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP5_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP5_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP5_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP5_REPLACE_OFFSET 0x201c +#define GC_M3_FP_COMP6_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP6_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP6_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP6_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP6_ENABLE_OFFSET 0x2020 +#define GC_M3_FP_COMP6_COMP_LSB 0x2 +#define GC_M3_FP_COMP6_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP6_COMP_SIZE 0x1b +#define GC_M3_FP_COMP6_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP6_COMP_OFFSET 0x2020 +#define GC_M3_FP_COMP6_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP6_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP6_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP6_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP6_REPLACE_OFFSET 0x2020 +#define GC_M3_FP_COMP7_ENABLE_LSB 0x0 +#define GC_M3_FP_COMP7_ENABLE_MASK 0x1 +#define GC_M3_FP_COMP7_ENABLE_SIZE 0x1 +#define GC_M3_FP_COMP7_ENABLE_DEFAULT 0x0 +#define GC_M3_FP_COMP7_ENABLE_OFFSET 0x2024 +#define GC_M3_FP_COMP7_COMP_LSB 0x2 +#define GC_M3_FP_COMP7_COMP_MASK 0x1ffffffc +#define GC_M3_FP_COMP7_COMP_SIZE 0x1b +#define GC_M3_FP_COMP7_COMP_DEFAULT 0x0 +#define GC_M3_FP_COMP7_COMP_OFFSET 0x2024 +#define GC_M3_FP_COMP7_REPLACE_LSB 0x1e +#define GC_M3_FP_COMP7_REPLACE_MASK 0xc0000000 +#define GC_M3_FP_COMP7_REPLACE_SIZE 0x2 +#define GC_M3_FP_COMP7_REPLACE_DEFAULT 0x0 +#define GC_M3_FP_COMP7_REPLACE_OFFSET 0x2024 #define GC_M3_ICTR_INTLINESNUM_LSB 0x0 #define GC_M3_ICTR_INTLINESNUM_MASK 0xf #define GC_M3_ICTR_INTLINESNUM_SIZE 0x4 @@ -24112,11 +26554,6 @@ #define GC_M3_SYST_CSR_CLKSOURCE_SIZE 0x1 #define GC_M3_SYST_CSR_CLKSOURCE_DEFAULT 0x1 #define GC_M3_SYST_CSR_CLKSOURCE_OFFSET 0xe010 -#define GC_M3_SYST_CSR_RESERVED_LSB 0x3 -#define GC_M3_SYST_CSR_RESERVED_MASK 0xfff8 -#define GC_M3_SYST_CSR_RESERVED_SIZE 0xd -#define GC_M3_SYST_CSR_RESERVED_DEFAULT 0x0 -#define GC_M3_SYST_CSR_RESERVED_OFFSET 0xe010 #define GC_M3_SYST_CSR_COUNTFLAG_LSB 0x10 #define GC_M3_SYST_CSR_COUNTFLAG_MASK 0x10000 #define GC_M3_SYST_CSR_COUNTFLAG_SIZE 0x1 @@ -24127,21 +26564,16 @@ #define GC_M3_SYST_RVR_RELOAD_SIZE 0x18 #define GC_M3_SYST_RVR_RELOAD_DEFAULT 0x0 #define GC_M3_SYST_RVR_RELOAD_OFFSET 0xe014 -#define GC_M3_SYST_CVR_RELOAD_LSB 0x0 -#define GC_M3_SYST_CVR_RELOAD_MASK 0xffffffff -#define GC_M3_SYST_CVR_RELOAD_SIZE 0x20 -#define GC_M3_SYST_CVR_RELOAD_DEFAULT 0x0 -#define GC_M3_SYST_CVR_RELOAD_OFFSET 0xe018 +#define GC_M3_SYST_CVR_CURRENT_LSB 0x0 +#define GC_M3_SYST_CVR_CURRENT_MASK 0xffffffff +#define GC_M3_SYST_CVR_CURRENT_SIZE 0x20 +#define GC_M3_SYST_CVR_CURRENT_DEFAULT 0x0 +#define GC_M3_SYST_CVR_CURRENT_OFFSET 0xe018 #define GC_M3_SYST_CALIB_TENMS_LSB 0x0 #define GC_M3_SYST_CALIB_TENMS_MASK 0xffffff #define GC_M3_SYST_CALIB_TENMS_SIZE 0x18 #define GC_M3_SYST_CALIB_TENMS_DEFAULT 0x3f79f #define GC_M3_SYST_CALIB_TENMS_OFFSET 0xe01c -#define GC_M3_SYST_CALIB_RESERVED_LSB 0x18 -#define GC_M3_SYST_CALIB_RESERVED_MASK 0x3f000000 -#define GC_M3_SYST_CALIB_RESERVED_SIZE 0x6 -#define GC_M3_SYST_CALIB_RESERVED_DEFAULT 0x0 -#define GC_M3_SYST_CALIB_RESERVED_OFFSET 0xe01c #define GC_M3_SYST_CALIB_SKEW_LSB 0x1e #define GC_M3_SYST_CALIB_SKEW_MASK 0x40000000 #define GC_M3_SYST_CALIB_SKEW_SIZE 0x1 @@ -24152,6 +26584,146 @@ #define GC_M3_SYST_CALIB_NOREF_SIZE 0x1 #define GC_M3_SYST_CALIB_NOREF_DEFAULT 0x0 #define GC_M3_SYST_CALIB_NOREF_OFFSET 0xe01c +#define GC_M3_CPUID_REVISION_LSB 0x0 +#define GC_M3_CPUID_REVISION_MASK 0xf +#define GC_M3_CPUID_REVISION_SIZE 0x4 +#define GC_M3_CPUID_REVISION_DEFAULT 0x1 +#define GC_M3_CPUID_REVISION_OFFSET 0xed00 +#define GC_M3_CPUID_PARTNO_LSB 0x4 +#define GC_M3_CPUID_PARTNO_MASK 0xfff0 +#define GC_M3_CPUID_PARTNO_SIZE 0xc +#define GC_M3_CPUID_PARTNO_DEFAULT 0xc23 +#define GC_M3_CPUID_PARTNO_OFFSET 0xed00 +#define GC_M3_CPUID_CONSTANT_LSB 0x10 +#define GC_M3_CPUID_CONSTANT_MASK 0xf0000 +#define GC_M3_CPUID_CONSTANT_SIZE 0x4 +#define GC_M3_CPUID_CONSTANT_DEFAULT 0xf +#define GC_M3_CPUID_CONSTANT_OFFSET 0xed00 +#define GC_M3_CPUID_VARIANT_LSB 0x14 +#define GC_M3_CPUID_VARIANT_MASK 0xf00000 +#define GC_M3_CPUID_VARIANT_SIZE 0x4 +#define GC_M3_CPUID_VARIANT_DEFAULT 0x2 +#define GC_M3_CPUID_VARIANT_OFFSET 0xed00 +#define GC_M3_CPUID_IMPLEMENTER_LSB 0x18 +#define GC_M3_CPUID_IMPLEMENTER_MASK 0xff000000 +#define GC_M3_CPUID_IMPLEMENTER_SIZE 0x8 +#define GC_M3_CPUID_IMPLEMENTER_DEFAULT 0x41 +#define GC_M3_CPUID_IMPLEMENTER_OFFSET 0xed00 +#define GC_M3_ICSR_VECTACTIVE_LSB 0x0 +#define GC_M3_ICSR_VECTACTIVE_MASK 0x1ff +#define GC_M3_ICSR_VECTACTIVE_SIZE 0x9 +#define GC_M3_ICSR_VECTACTIVE_DEFAULT 0x0 +#define GC_M3_ICSR_VECTACTIVE_OFFSET 0xed04 +#define GC_M3_ICSR_RETTOBASE_LSB 0xb +#define GC_M3_ICSR_RETTOBASE_MASK 0x800 +#define GC_M3_ICSR_RETTOBASE_SIZE 0x1 +#define GC_M3_ICSR_RETTOBASE_DEFAULT 0x0 +#define GC_M3_ICSR_RETTOBASE_OFFSET 0xed04 +#define GC_M3_ICSR_VECTPENDING_LSB 0xc +#define GC_M3_ICSR_VECTPENDING_MASK 0x3ff000 +#define GC_M3_ICSR_VECTPENDING_SIZE 0xa +#define GC_M3_ICSR_VECTPENDING_DEFAULT 0x0 +#define GC_M3_ICSR_VECTPENDING_OFFSET 0xed04 +#define GC_M3_ICSR_ISRPENDING_LSB 0x16 +#define GC_M3_ICSR_ISRPENDING_MASK 0x400000 +#define GC_M3_ICSR_ISRPENDING_SIZE 0x1 +#define GC_M3_ICSR_ISRPENDING_DEFAULT 0x0 +#define GC_M3_ICSR_ISRPENDING_OFFSET 0xed04 +#define GC_M3_ICSR_ISRPREEMPT_LSB 0x17 +#define GC_M3_ICSR_ISRPREEMPT_MASK 0x800000 +#define GC_M3_ICSR_ISRPREEMPT_SIZE 0x1 +#define GC_M3_ICSR_ISRPREEMPT_DEFAULT 0x0 +#define GC_M3_ICSR_ISRPREEMPT_OFFSET 0xed04 +#define GC_M3_ICSR_PENDSTCLR_LSB 0x19 +#define GC_M3_ICSR_PENDSTCLR_MASK 0x2000000 +#define GC_M3_ICSR_PENDSTCLR_SIZE 0x1 +#define GC_M3_ICSR_PENDSTCLR_DEFAULT 0x0 +#define GC_M3_ICSR_PENDSTCLR_OFFSET 0xed04 +#define GC_M3_ICSR_PENDSTSET_LSB 0x1a +#define GC_M3_ICSR_PENDSTSET_MASK 0x4000000 +#define GC_M3_ICSR_PENDSTSET_SIZE 0x1 +#define GC_M3_ICSR_PENDSTSET_DEFAULT 0x0 +#define GC_M3_ICSR_PENDSTSET_OFFSET 0xed04 +#define GC_M3_ICSR_PENDSVCLR_LSB 0x1b +#define GC_M3_ICSR_PENDSVCLR_MASK 0x8000000 +#define GC_M3_ICSR_PENDSVCLR_SIZE 0x1 +#define GC_M3_ICSR_PENDSVCLR_DEFAULT 0x0 +#define GC_M3_ICSR_PENDSVCLR_OFFSET 0xed04 +#define GC_M3_ICSR_PENDSVSET_LSB 0x1c +#define GC_M3_ICSR_PENDSVSET_MASK 0x10000000 +#define GC_M3_ICSR_PENDSVSET_SIZE 0x1 +#define GC_M3_ICSR_PENDSVSET_DEFAULT 0x0 +#define GC_M3_ICSR_PENDSVSET_OFFSET 0xed04 +#define GC_M3_ICSR_NMIPENDSET_LSB 0x1f +#define GC_M3_ICSR_NMIPENDSET_MASK 0x80000000 +#define GC_M3_ICSR_NMIPENDSET_SIZE 0x1 +#define GC_M3_ICSR_NMIPENDSET_DEFAULT 0x0 +#define GC_M3_ICSR_NMIPENDSET_OFFSET 0xed04 +#define GC_M3_DEMCR_VC_CORERESET_LSB 0x0 +#define GC_M3_DEMCR_VC_CORERESET_MASK 0x1 +#define GC_M3_DEMCR_VC_CORERESET_SIZE 0x1 +#define GC_M3_DEMCR_VC_CORERESET_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_CORERESET_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_MMERR_LSB 0x4 +#define GC_M3_DEMCR_VC_MMERR_MASK 0x10 +#define GC_M3_DEMCR_VC_MMERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_MMERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_MMERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_NOCPERR_LSB 0x5 +#define GC_M3_DEMCR_VC_NOCPERR_MASK 0x20 +#define GC_M3_DEMCR_VC_NOCPERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_NOCPERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_NOCPERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_CHKERR_LSB 0x6 +#define GC_M3_DEMCR_VC_CHKERR_MASK 0x40 +#define GC_M3_DEMCR_VC_CHKERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_CHKERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_CHKERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_STATERR_LSB 0x7 +#define GC_M3_DEMCR_VC_STATERR_MASK 0x80 +#define GC_M3_DEMCR_VC_STATERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_STATERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_STATERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_BUSERR_LSB 0x8 +#define GC_M3_DEMCR_VC_BUSERR_MASK 0x100 +#define GC_M3_DEMCR_VC_BUSERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_BUSERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_BUSERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_INTERR_LSB 0x9 +#define GC_M3_DEMCR_VC_INTERR_MASK 0x200 +#define GC_M3_DEMCR_VC_INTERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_INTERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_INTERR_OFFSET 0xedfc +#define GC_M3_DEMCR_VC_HARDERR_LSB 0xa +#define GC_M3_DEMCR_VC_HARDERR_MASK 0x400 +#define GC_M3_DEMCR_VC_HARDERR_SIZE 0x1 +#define GC_M3_DEMCR_VC_HARDERR_DEFAULT 0x0 +#define GC_M3_DEMCR_VC_HARDERR_OFFSET 0xedfc +#define GC_M3_DEMCR_MON_EN_LSB 0x10 +#define GC_M3_DEMCR_MON_EN_MASK 0x10000 +#define GC_M3_DEMCR_MON_EN_SIZE 0x1 +#define GC_M3_DEMCR_MON_EN_DEFAULT 0x0 +#define GC_M3_DEMCR_MON_EN_OFFSET 0xedfc +#define GC_M3_DEMCR_MON_PEND_LSB 0x11 +#define GC_M3_DEMCR_MON_PEND_MASK 0x20000 +#define GC_M3_DEMCR_MON_PEND_SIZE 0x1 +#define GC_M3_DEMCR_MON_PEND_DEFAULT 0x0 +#define GC_M3_DEMCR_MON_PEND_OFFSET 0xedfc +#define GC_M3_DEMCR_MON_STEP_LSB 0x12 +#define GC_M3_DEMCR_MON_STEP_MASK 0x40000 +#define GC_M3_DEMCR_MON_STEP_SIZE 0x1 +#define GC_M3_DEMCR_MON_STEP_DEFAULT 0x0 +#define GC_M3_DEMCR_MON_STEP_OFFSET 0xedfc +#define GC_M3_DEMCR_MON_REQ_LSB 0x13 +#define GC_M3_DEMCR_MON_REQ_MASK 0x80000 +#define GC_M3_DEMCR_MON_REQ_SIZE 0x1 +#define GC_M3_DEMCR_MON_REQ_DEFAULT 0x0 +#define GC_M3_DEMCR_MON_REQ_OFFSET 0xedfc +#define GC_M3_DEMCR_TRCENA_LSB 0x18 +#define GC_M3_DEMCR_TRCENA_MASK 0x1000000 +#define GC_M3_DEMCR_TRCENA_SIZE 0x1 +#define GC_M3_DEMCR_TRCENA_DEFAULT 0x0 +#define GC_M3_DEMCR_TRCENA_OFFSET 0xedfc #define GC_CRYPTO_DMEM_DUMMY_SIZE 0x1000 #define GC_CRYPTO_IMEM_DUMMY_SIZE 0x1000 #define GC_SPI_DATA_SIZE 0x100 @@ -24203,10 +26775,11 @@ -1 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */ -#endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */ #define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad #define GC_CONST_FSH_PE_EN 0xb11924e1 #define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818 #define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927 #define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 #define GC_CONST_FSH_OVRD_UNLOCK 0x13806488 + +#endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */ |