diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2014-09-23 14:19:47 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-24 08:56:21 +0000 |
| commit | 981836f44ce53fd76c4861c651f4d4152be4f2a4 (patch) | |
| tree | b235f3bd6d217188220f470a5e715e3d26920194 | |
| parent | 51bc6645da1fd946a76fe49ca8e562920afd1f29 (diff) | |
| download | chrome-ec-981836f44ce53fd76c4861c651f4d4152be4f2a4.tar.gz | |
stm32: Fix PWM driver
STM32F and STM32F0 series require an MOE bit to be set to enable PWM
output. In addition, require that the PWM alternate function # be
manually specified for STM32F0 -- there seems to be no logical mapping
here, unlike other STM32* parts.
BUG=chrome-os-partner:32089
TEST=Manual on samus-pd. Set ILIM PWM output to 50% duty cycle with pwm
driver functions, probe and verify avg. 1.62V on pin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Icb13a153fa3eee52be938d76a6c980fe6fd2bb3e
Reviewed-on: https://chromium-review.googlesource.com/219570
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
| -rw-r--r-- | chip/stm32/pwm.c | 16 | ||||
| -rw-r--r-- | chip/stm32/pwm_chip.h | 2 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 7 |
3 files changed, 22 insertions, 3 deletions
diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index 19740a42bd..073e2df511 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -47,7 +47,7 @@ static void pwm_configure(enum pwm_channel ch) if (using_pwm[ch]) return; -#ifdef CHIP_FAMILY_STM32F +#if defined(CHIP_FAMILY_STM32F) if (mask < 0x100) { gpio_cr = &STM32_GPIO_CRL(gpio->port); } else { @@ -63,7 +63,9 @@ static void pwm_configure(enum pwm_channel ch) val = *gpio_cr & ~(mask * 0xf); val |= mask * 0x9; *gpio_cr = val; -#else /* stm32l or stm32f0 */ +#elif defined(CHIP_FAMILY_STM32F0) + gpio_set_alternate_function(gpio->port, gpio->mask, pwm->gpio_alt_func); +#else /* stm32l */ gpio_set_alternate_function(gpio->port, gpio->mask, GPIO_ALT_TIM(pwm->tim.id)); #endif @@ -101,6 +103,13 @@ static void pwm_configure(enum pwm_channel ch) else tim->ccer = 1 << (pwm->channel * 4 - 4); + /* + * Main output enable. + * TODO(shawnn): BDTR is undocumented on STM32L. Verify this isn't + * harmful on STM32L. + */ + tim->bdtr |= (1 << 15); + /* Generate update event to force loading of shadow registers */ tim->egr |= 1; @@ -118,6 +127,9 @@ static void pwm_disable(enum pwm_channel ch) if (using_pwm[ch] == 0) return; + /* Main output disable */ + tim->bdtr &= ~(1 << 15); + /* Disable counter */ tim->cr1 &= ~0x1; diff --git a/chip/stm32/pwm_chip.h b/chip/stm32/pwm_chip.h index d588dabeaa..4e15e612c1 100644 --- a/chip/stm32/pwm_chip.h +++ b/chip/stm32/pwm_chip.h @@ -24,6 +24,8 @@ struct pwm_t { uint32_t flags; /* GPIO pin corresponding to the PWM channel */ enum gpio_signal pin; + /* GPIO alternate function - only needed for STM32F0 family */ + int gpio_alt_func; }; extern const struct pwm_t pwm_channels[]; diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index a806c74afa..351b1a657d 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -362,7 +362,12 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_GPIO_AFRH(b) REG32((b) + 0x24) #define STM32_GPIO_BRR(b) REG32((b) + 0x28) -#define GPIO_ALT_TIM(x) (0 /*TODO(fixme)*/) +#define GPIO_ALT_F0 0x0 +#define GPIO_ALT_F1 0x1 +#define GPIO_ALT_F2 0x2 +#define GPIO_ALT_F3 0x3 +#define GPIO_ALT_F4 0x4 +#define GPIO_ALT_F5 0x5 #elif defined(CHIP_FAMILY_STM32F) #define STM32_GPIOA_BASE 0x40010800 |