diff options
| author | Alexandru M Stan <amstan@chromium.org> | 2014-08-07 15:20:46 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-08-08 03:11:33 +0000 |
| commit | 5d208b992494ae4cdeffc0efdf4f341c6ada64e5 (patch) | |
| tree | 63e9823f07a2823c7ac8d2f2e6d61b8a8a4bc93a | |
| parent | d4839198a724812a1e6effc49eb72ee422f01768 (diff) | |
| download | chrome-ec-5d208b992494ae4cdeffc0efdf4f341c6ada64e5.tar.gz | |
STM32F0 SPI Fixes
The STM32F0 has a fancier SPI than the L1 series we've been using so far.
Notably it supports 16 bit data packing. This mode is activated automatically
by reading/writing to the SPI_DR register as 16 bits. We do not want this
feature since we only do 8 bit operations. This change prevents a misalignment
of the data where the MCU thinks it's doing 16 bit transfers and we want 8 bit
transfers.
Another unwanted feature is the FIFO. We rely on DMA and some buffers instead.
Keeping the FIFO enabled causes extra characters. The way this patch disables
the fifo is by changing the FIFO reception threshold to only 1 byte (which is
the same behavior that L1 has with no FIFO). Setting the FRXTH bit on the L1
chips should not affect anything as that area of the register is reserved.
BUG=none
BRANCH=none
TEST=Try SPI on both STM32L1xx(preexisting support, should not be broken) and
STM32F0(new support/veyron)
Change-Id: I90dc6bb8a82881e70058443591acaebc44ba982b
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211476
Reviewed-by: Doug Anderson <dianders@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 5 | ||||
| -rw-r--r-- | chip/stm32/spi.c | 12 |
2 files changed, 11 insertions, 6 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 2037ecd234..0b64208e20 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -684,8 +684,9 @@ struct stm32_spi_regs { uint16_t cr2; uint16_t _pad1; unsigned sr; - uint16_t dr; - uint16_t _pad2; + uint8_t dr; + uint8_t _pad2; + uint16_t _pad3; unsigned crcpr; unsigned rxcrcr; unsigned txcrcr; diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index c6fd24bc36..f784d94e31 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -26,12 +26,12 @@ /* DMA channel option */ static const struct dma_option dma_tx_option = { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }; static const struct dma_option dma_rx_option = { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, - STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT + STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }; /* @@ -550,8 +550,12 @@ static void spi_init(void) /* Enable clocks to SPI1 module */ STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; - /* Enable rx DMA and get ready to receive our first transaction */ - spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN; + /* + * Enable rx/tx DMA and get ready to receive our first transaction and + * "disable" FIFO by setting event to happen after only 1 byte + */ + spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN | + STM32_SPI_CR2_FRXTH; /* Enable the SPI peripheral */ spi->cr1 |= STM32_SPI_CR1_SPE; |