summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChris Zhong <zyw@rock-chips.com>2014-07-30 14:22:30 -0700
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2014-08-06 04:36:58 +0000
commit4c1665eb9c6914f54330a65ef01327ec1941af54 (patch)
tree8643666fe797f80dd13c010eb4a6b0afdd3db6ba
parent2125690c365fb6798569dc81423e4afa14dbcf1a (diff)
downloadchrome-ec-4c1665eb9c6914f54330a65ef01327ec1941af54.tar.gz
veyron: Change EC_INT pin to high-Z in S5
Change EC_INT pin to high-Z to reduce power draw in S5, and reset it to output High in S5S3. BUG=None TEST=Leakage did not happen, other functions also work correctly. BRANCH=None Change-Id: Id77bb9f34f25336cd097344be349f5aa43a75b52 Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/210545 Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--power/rockchip.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/power/rockchip.c b/power/rockchip.c
index b6eecdc437..898bba40ee 100644
--- a/power/rockchip.c
+++ b/power/rockchip.c
@@ -364,6 +364,8 @@ static void power_on(void)
/* enable interrupt */
gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT | GPIO_INT_BOTH
| GPIO_PULL_DOWN);
+
+ gpio_set_flags(GPIO_EC_INT, GPIO_OUTPUT | GPIO_OUT_HIGH);
/* Make sure we de-assert the PMI_SOURCE and AP_RESET_L pin. */
set_pmic_source(1);
set_ap_reset(0);
@@ -444,8 +446,9 @@ static void power_off(void)
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* switch off all rails */
chipset_turn_off_power_rails();
- /* Change SUSPEND_L pin to high-Z to reduce power draw. */
+ /* Change SUSPEND_L and EC_INT pin to high-Z to reduce power draw. */
gpio_set_flags(GPIO_SUSPEND_L, GPIO_INPUT);
+ gpio_set_flags(GPIO_EC_INT, GPIO_INPUT);
lid_opened = 0;
enable_sleep(SLEEP_MASK_AP_RUN);