pd: handle plug polarity

Use the plug polarity detected by the ADCs to do the PD communication on
the right CCx line.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:28339
TEST=make buildall
on Firefly, plug Zinger connector in both direction and see it can
control it either way.
on Fruitpie, use CC1 or CC2 and see it can communicate on both.

Change-Id: I81cb00f164cb8194fba73b383014e81c37d975e2
Reviewed-on: https://chromium-review.googlesource.com/197520
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>

6 files changed, 54 insertions, 25 deletions

diff --git a/board/fruitpie/usb_pd_config.h b/board/fruitpie/usb_pd_config.h
index cdbb0f365d..52f5448aa2 100644
--- a/board/fruitpie/usb_pd_config.h
+++ b/board/fruitpie/usb_pd_config.h
@@ -29,7 +29,7 @@ static inline void spi_enable_clock(void)
 #define DMAC_TIM_RX STM32_DMAC_CH2
 #define TIM_CCR_IDX 1
 #define TIM_CCR_CS  1
-#define EXTI_COMP 21
+#define EXTI_COMP_MASK (1 << 21)
 #define IRQ_COMP STM32_IRQ_COMP
 /* triggers packet detection on comparator falling edge */
 #define EXTI_XTSR STM32_EXTI_FTSR
@@ -44,17 +44,27 @@ static inline void pd_set_pins_speed(void)
 }
 
 /* Drive the CC line from the TX block */
-static inline void pd_tx_enable(void)
+static inline void pd_tx_enable(int polarity)
 {
 	gpio_set_level(GPIO_PD_TX_EN, 1);
 }
 
 /* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(void)
+static inline void pd_tx_disable(int polarity)
 {
 	gpio_set_level(GPIO_PD_TX_EN, 0);
 }
 
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int polarity)
+{
+	/* use the right comparator non inverted input for COMP1 */
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
+		| STM32_COMP_CMP1EN
+		| (polarity ? STM32_COMP_CMP1INSEL_INM4
+			    : STM32_COMP_CMP1INSEL_INM6);
+}
+
 /* Initialize pins used for TX and put them in Hi-Z */
 static inline void pd_tx_init(void)
 {
diff --git a/board/zinger/usb_pd_config.h b/board/zinger/usb_pd_config.h
index 0900f51a05..dac4bf2c63 100644
--- a/board/zinger/usb_pd_config.h
+++ b/board/zinger/usb_pd_config.h
@@ -29,7 +29,7 @@ static inline void spi_enable_clock(void)
 #define TIM_CCR_IDX 1
 /* connect TIM3 CH1 to TIM3_CH2 input */
 #define TIM_CCR_CS  2
-#define EXTI_COMP 7
+#define EXTI_COMP_MASK (1 << 7)
 #define IRQ_COMP STM32_IRQ_EXTI4_15
 /* the RX is inverted, triggers on rising edge */
 #define EXTI_XTSR STM32_EXTI_RTSR
@@ -44,7 +44,7 @@ static inline void pd_set_pins_speed(void)
 }
 
 /* Drive the CC line from the TX block */
-static inline void pd_tx_enable(void)
+static inline void pd_tx_enable(int polarity)
 {
 	/* Drive TX GND on PA4 */
 	STM32_GPIO_BSRR(GPIO_A) = 1 << (4 + 16 /* Reset */);
@@ -53,7 +53,7 @@ static inline void pd_tx_enable(void)
 }
 
 /* Put the TX driver in Hi-Z state */
-static inline void pd_tx_disable(void)
+static inline void pd_tx_disable(int polarity)
 {
 	/* Put TX GND (PA4) in Hi-Z state */
 	STM32_GPIO_BSRR(GPIO_A) = 1 << 4 /* Set */;
@@ -61,6 +61,12 @@ static inline void pd_tx_disable(void)
 	STM32_GPIO_MODER(GPIO_A) &= ~(0x3 << (2*6));
 }
 
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int polarity)
+{
+	/* captive cable : no polarity */
+}
+
 /* Initialize pins used for TX and put them in Hi-Z */
 static inline void pd_tx_init(void)
 {
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h
index 9195fd3f81..c6b2acef09 100644
--- a/chip/stm32/registers.h
+++ b/chip/stm32/registers.h
@@ -926,6 +926,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP2OUTSEL_NONE     (0 << 24)
 #define STM32_COMP_WNDWEN              (1 << 23)
 
+#define STM32_COMP_CMP2INSEL_MASK      (7 << 20)
 #define STM32_COMP_CMP2INSEL_INM6      (6 << 20)
 #define STM32_COMP_CMP2INSEL_INM5      (5 << 20)
 #define STM32_COMP_CMP2INSEL_INM4      (4 << 20)
@@ -957,6 +958,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
 #define STM32_COMP_CMP1OUTSEL_TIM1_BRK (1 << 8)
 #define STM32_COMP_CMP1OUTSEL_NONE     (0 << 8)
 
+#define STM32_COMP_CMP1INSEL_MASK      (7 << 4)
 #define STM32_COMP_CMP1INSEL_INM6      (6 << 4)
 #define STM32_COMP_CMP1INSEL_INM5      (5 << 4)
 #define STM32_COMP_CMP1INSEL_INM4      (4 << 4)
diff --git a/chip/stm32/usb_pd_phy.c b/chip/stm32/usb_pd_phy.c
index 2d33e9f96e..4417cd3f54 100644
--- a/chip/stm32/usb_pd_phy.c
+++ b/chip/stm32/usb_pd_phy.c
@@ -255,7 +255,7 @@ static const struct dma_option dma_tx_option = {
 	STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
 };
 
-void pd_start_tx(void *ctxt, int bit_len)
+void pd_start_tx(void *ctxt, int polarity, int bit_len)
 {
 	stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX);
 
@@ -271,7 +271,7 @@ void pd_start_tx(void *ctxt, int bit_len)
 	 * - set the low level reference.
 	 * - put SPI function on TX pin.
 	 */
-	pd_tx_enable();
+	pd_tx_enable(polarity);
 
 	/* Kick off the DMA to send the data */
 	dma_go(tx);
@@ -282,7 +282,7 @@ void pd_start_tx(void *ctxt, int bit_len)
 #endif
 }
 
-void pd_tx_done(void)
+void pd_tx_done(int polarity)
 {
 	stm32_spi_regs_t *spi = SPI_REGS;
 
@@ -321,7 +321,7 @@ void pd_tx_done(void)
 	dma_clear_isr(DMAC_SPI_TX);
 
 	/* put TX pins and reference in Hi-Z */
-	pd_tx_disable();
+	pd_tx_disable(polarity);
 }
 
 /* --- RX operation using comparator linked to timer --- */
@@ -352,7 +352,7 @@ void pd_rx_complete(void)
 void pd_rx_enable_monitoring(void)
 {
 	/* clear comparator external interrupt */
-	STM32_EXTI_PR = 1 << EXTI_COMP;
+	STM32_EXTI_PR = EXTI_COMP_MASK;
 	/* clean up older comparator event */
 	task_clear_pending_irq(IRQ_COMP);
 	/* re-enable comparator interrupt to detect packets */
@@ -364,7 +364,7 @@ void pd_rx_disable_monitoring(void)
 	/* stop monitoring RX during sampling */
 	task_disable_irq(IRQ_COMP);
 	/* clear comparator external interrupt */
-	STM32_EXTI_PR = 1 << EXTI_COMP;
+	STM32_EXTI_PR = EXTI_COMP_MASK;
 }
 
 /* detect an edge on the PD RX pin */
@@ -490,10 +490,14 @@ void *pd_hw_init(void)
 	/* turn on COMP/SYSCFG */
 	STM32_RCC_APB2ENR |= 1 << 0;
 	/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
-	STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_LSPEED |
+	STM32_COMP_CSR = STM32_COMP_CMP1MODE_LSPEED |
 			 STM32_COMP_CMP1INSEL_INM6 |
 			 STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
-			 STM32_COMP_CMP1HYST_HI;
+			 STM32_COMP_CMP1HYST_HI |
+			 STM32_COMP_CMP2MODE_LSPEED |
+			 STM32_COMP_CMP2INSEL_INM6 |
+			 STM32_COMP_CMP2OUTSEL_TIM1_IC1 |
+			 STM32_COMP_CMP2HYST_HI;
 #elif defined(CHIP_FAMILY_STM32L)
 	/* 40 MHz pin speed on PB4 */
 	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x300;
@@ -510,8 +514,8 @@ void *pd_hw_init(void)
 #endif /* CONFIG_USB_PD_INTERNAL_COMP */
 	/* DBG */usleep(250000);
 	/* comparator interrupt setup */
-	EXTI_XTSR |= 1 << EXTI_COMP;
-	STM32_EXTI_IMR |= 1 << EXTI_COMP;
+	EXTI_XTSR |= EXTI_COMP_MASK;
+	STM32_EXTI_IMR |= EXTI_COMP_MASK;
 	task_enable_irq(IRQ_COMP);
 
 	CPRINTF("USB PD initialized\n");
diff --git a/common/usb_pd_protocol.c b/common/usb_pd_protocol.c
index b5c64d83f8..23cb178bff 100644
--- a/common/usb_pd_protocol.c
+++ b/common/usb_pd_protocol.c
@@ -273,8 +273,8 @@ static void send_hard_reset(void *ctxt)
 	/* Ensure that we have a final edge */
 	off = pd_write_last_edge(ctxt, off);
 	/* Transmit the packet */
-	pd_start_tx(ctxt, off);
-	pd_tx_done();
+	pd_start_tx(ctxt, pd_polarity, off);
+	pd_tx_done(pd_polarity);
 }
 
 static int send_validate_message(void *ctxt, uint16_t header, uint8_t cnt,
@@ -290,8 +290,8 @@ static int send_validate_message(void *ctxt, uint16_t header, uint8_t cnt,
 		/* write the encoded packet in the transmission buffer */
 		bit_len = prepare_message(ctxt, header, cnt, data);
 		/* Transmit the packet */
-		pd_start_tx(ctxt, bit_len);
-		pd_tx_done();
+		pd_start_tx(ctxt, pd_polarity, bit_len);
+		pd_tx_done(pd_polarity);
 		/* starting waiting for GoodCrc */
 		pd_rx_start();
 		/* read the incoming packet if any */
@@ -336,8 +336,8 @@ static void send_goodcrc(void *ctxt, int id)
 	uint16_t header = PD_HEADER(PD_CTRL_GOOD_CRC, pd_role, id, 0);
 	int bit_len = prepare_message(ctxt, header, 0, NULL);
 
-	pd_start_tx(ctxt, bit_len);
-	pd_tx_done();
+	pd_start_tx(ctxt, pd_polarity, bit_len);
+	pd_tx_done(pd_polarity);
 }
 
 static int send_source_cap(void *ctxt)
@@ -654,6 +654,7 @@ void pd_task(void)
 			if ((cc1_volt < PD_SRC_VNC) ||
 			    (cc2_volt < PD_SRC_VNC)) {
 				pd_polarity = !(cc1_volt < PD_SRC_VNC);
+				pd_select_polarity(pd_polarity);
 				pd_task_state = PD_STATE_SRC_DISCOVERY;
 			}
 			timeout = 10000;
@@ -707,6 +708,7 @@ void pd_task(void)
 			if ((cc1_volt > PD_SNK_VA) ||
 			    (cc2_volt > PD_SNK_VA)) {
 				pd_polarity = !(cc1_volt > PD_SNK_VA);
+				pd_select_polarity(pd_polarity);
 				pd_task_state = PD_STATE_SNK_DISCOVERY;
 			}
 			timeout = 10000;
diff --git a/include/usb_pd.h b/include/usb_pd.h
index c3fac8b296..e11d712800 100644
--- a/include/usb_pd.h
+++ b/include/usb_pd.h
@@ -244,11 +244,16 @@ void pd_set_clock(int freq);
  * Start sending over the wire the prepared packet.
  *
  * @param ctxt    opaque context.
+ * @param polarity plug polarity (0=CC1, 1=CC2).
  * @param bit_len size of the packet in bits.
  */
-void pd_start_tx(void *ctxt, int bit_len);
-/* Call when we are done sending a packet */
-void pd_tx_done(void);
+void pd_start_tx(void *ctxt, int polarity, int bit_len);
+/**
+ * Call when we are done sending a packet.
+ *
+ * @param polarity plug polarity (0=CC1, 1=CC2).
+ */
+void pd_tx_done(int polarity);
 
 /* Callback when the hardware has detected an incoming packet */
 void pd_rx_event(void);