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| author | Diana Z <dzigterman@chromium.org> | 2022-07-13 17:02:53 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-18 16:35:47 +0000 |
| commit | c66c42bf01446a9d3418f5e69bcbee953ad9d3e3 (patch) | |
| tree | 6a9ae4ae03c1c8e2cfb44d8dcf8780ea4122d8b2 | |
| parent | 2fa3b7d9b5d436d9ba8aa9d2c3128dd1444116a4 (diff) | |
| download | chrome-ec-c66c42bf01446a9d3418f5e69bcbee953ad9d3e3.tar.gz | |
Skyrim: Apply MP2845A workaround
Apply a workaround for a MP2845A problem.
BRANCH=None
BUG=b:238879278
TEST=on skyrim, dump register in S0 to ensure the bit is cleared
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Id21004a165afa934e13d75ca54280bed274d0e6f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761365
Reviewed-by: Robert Zieba <robertzieba@google.com>
Commit-Queue: Robert Zieba <robertzieba@google.com>
| -rw-r--r-- | zephyr/projects/skyrim/power_signals.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/zephyr/projects/skyrim/power_signals.c b/zephyr/projects/skyrim/power_signals.c index c3d1826d78..ec0364519e 100644 --- a/zephyr/projects/skyrim/power_signals.c +++ b/zephyr/projects/skyrim/power_signals.c @@ -4,11 +4,14 @@ */ #include "ap_power/ap_power.h" +#include "charger.h" #include "chipset.h" #include "config.h" +#include "cros_board_info.h" #include "gpio_signal.h" #include "gpio/gpio_int.h" #include "hooks.h" +#include "i2c.h" #include "ioexpander.h" #include "power.h" #include "power/amd_x86.h" @@ -126,12 +129,36 @@ void baseboard_set_soc_pwr_pgood(enum gpio_signal unused) gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))); } +/* TODO: Remove when board versions are no longer supported */ +#define MP2845A_I2C_ADDR_FLAGS 0x20 +#define MP2854A_MFR_VOUT_CMPS_MAX_REG 0x69 +#define MP2854A_MFR_LOW_PWR_SEL BIT(12) + +static void setup_mp2845(void) +{ + int version; + + /* TODO: Remove when board versions are no longer supported */ + if ((cbi_get_board_version(&version) == EC_SUCCESS) && version > 3) + return; + + if (i2c_update16(chg_chips[CHARGER_SOLO].i2c_port, + MP2845A_I2C_ADDR_FLAGS, MP2854A_MFR_VOUT_CMPS_MAX_REG, + MP2854A_MFR_LOW_PWR_SEL, MASK_CLR)) + ccprints("Failed to send mp2845 workaround"); +} +DECLARE_DEFERRED(setup_mp2845); + void baseboard_s0_pgood(enum gpio_signal signal) { baseboard_set_soc_pwr_pgood(signal); /* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */ power_signal_interrupt(signal); + + /* Set up the MP2845, which is powered in S0 */ + if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_s0_pgood))) + hook_call_deferred(&setup_mp2845_data, 50 * MSEC); } /* Note: signal parameter unused */ |