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| author | Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com> | 2022-07-11 15:13:33 +0530 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-07-18 08:20:07 +0000 |
| commit | 79f3b8d7cd788ce78966ff76e1c7112c27136ce9 (patch) | |
| tree | feead00460a1342811369388c5ccdefa72c93815 | |
| parent | 524cba08cceb373050cf79c41e4f6f92ff519c5e (diff) | |
| download | chrome-ec-79f3b8d7cd788ce78966ff76e1c7112c27136ce9.tar.gz | |
ap_pwrseq: set VCCST_PWRGD_OD low early in power down sequence
In power down sequence or in S0 to S3 transition, VCCST_PWRGD_OD is
set to low in S0S3 state. This do not meet the timing requirements.
Hence change sets VCCST_PWRGD_OD set to low in S0 state when
SLP_S3 is found low.
PWR_VCCST_PWRGD declared as open-drain signal, measures 1.05v when set
to high. Hence gpio read of PWR_VCCST_PWRGD always returns 0.
Use api power_signals_on() to monitor the signal status correctly.
BUG=b:236664113
BRANCH=none
TEST=Verify boot and S3 on nivviks
Change-Id: I422cf78ba6d086af67a8e4b1ac275aa25772b430
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3754819
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
| -rw-r--r-- | zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c index 4d1425588f..50325240fb 100644 --- a/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c +++ b/zephyr/subsys/ap_pwrseq/x86_non_dsx_adlp_pwrseq_sm.c @@ -37,6 +37,12 @@ int all_sys_pwrgd_handler(void) { int retry = 0; + /* SLP_S3 is off */ + if (power_signal_get(PWR_SLP_S3) == 1) { + ap_off(); + return 1; + } + /* TODO: Add condition for no power sequencer */ power_wait_signals_timeout(POWER_SIGNAL_MASK(PWR_ALL_SYS_PWRGD), AP_PWRSEQ_DT_VALUE(all_sys_pwrgd_timeout)); @@ -58,7 +64,7 @@ int all_sys_pwrgd_handler(void) /* PG_EC_ALL_SYS_PWRGD is asserted, enable VCCST_PWRGD_OD. */ - if (power_signal_get(PWR_VCCST_PWRGD) == 0) { + if (!power_signals_on(POWER_SIGNAL_MASK(PWR_VCCST_PWRGD))) { k_msleep(AP_PWRSEQ_DT_VALUE(vccst_pwrgd_delay)); power_signal_set(PWR_VCCST_PWRGD, 1); } |