diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2014-10-20 15:17:57 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-21 22:44:53 +0000 |
| commit | ba98b92bbb03a62a466a36fbb50843a37602d98d (patch) | |
| tree | daa548b7689ddc39597065f2e5ede6791530e759 | |
| parent | cefb58066d2a706ad34726aff977be3a584fc001 (diff) | |
| download | chrome-ec-ba98b92bbb03a62a466a36fbb50843a37602d98d.tar.gz | |
cortex-m0: add more constraints on atomic implementation
In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | core/cortex-m0/atomic.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index ca3d3d47ba..8ba1b66739 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -24,7 +24,7 @@ " str %0, [%1]\n" \ " cpsie i\n" \ : "=&r" (reg0) \ - : "r" (a), "r" (v) : "cc"); \ + : "b" (a), "r" (v) : "cc"); \ } while (0) static inline void atomic_clear(uint32_t *addr, uint32_t bits) @@ -57,7 +57,7 @@ static inline uint32_t atomic_read_clear(uint32_t *addr) " str %2, [%1]\n" " cpsie i\n" : "=&r" (ret) - : "r" (addr), "r" (0) : "cc"); + : "b" (addr), "r" (0) : "cc"); return ret; } |