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| author | Patrick Georgi <pgeorgi@google.com> | 2018-05-16 11:22:13 +0200 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-04-20 14:25:23 +0000 |
| commit | 6f815b3b6c2423ecdb05cb912602df7550a42a00 (patch) | |
| tree | 121ca9bffd0cdb3c9cd4c7e34877c382f66a1116 | |
| parent | 19786459769bbbcc4bea50caf6fb63146617f157 (diff) | |
| download | chrome-ec-6f815b3b6c2423ecdb05cb912602df7550a42a00.tar.gz | |
Use gcc's name for ARMv6-with-svc on cortex-m chips
There were various longer discussions[0] over in gcc land and the
consensus pretty much is that gcc's "armv6-m" shouldn't really exist,
or rather map to its armv6s-m.
Cortex-M0 is documented as having the svc instruction[1], and we make
use of it, so let's go for armv6s-m as the safe option.
We need that on some compilers (gcc 7, gcc 8.1.0) since they actually
make that distinction. Newer ones won't, older ones apparently didn't.
[0] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85606
https://sourceware.org/bugzilla/show_bug.cgi?id=23126
[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0497a/BABBHFJE.html
BUG=b:65441143
BRANCH=none
TEST=builds with gcc 8.1
Change-Id: Ib0d5c484c2fbd72f033d8523cd1e0c6c8ce0c7e6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1061073
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit b3311c23b1fdc38daeb5e169d6e48fa62cac251e)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2723457
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/nrf51/build.mk | 6 | ||||
| -rw-r--r-- | chip/stm32/build.mk | 6 |
2 files changed, 10 insertions, 2 deletions
diff --git a/chip/nrf51/build.mk b/chip/nrf51/build.mk index 5680f10d91..d7354fbcb5 100644 --- a/chip/nrf51/build.mk +++ b/chip/nrf51/build.mk @@ -8,7 +8,11 @@ CORE:=cortex-m0 # Force ARMv6-M ISA used by the Cortex-M0 -CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0 +# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M +# without "svc" instruction, but that was short-lived. ARMv6S-M was the option +# with "svc". GCC kept that naming scheme even though the distinction is long +# gone. +CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 chip-y+=gpio.o system.o uart.o chip-y+=jtag.o watchdog.o ppi.o diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk index b44b3ac2fe..33fc44d145 100644 --- a/chip/stm32/build.mk +++ b/chip/stm32/build.mk @@ -10,7 +10,11 @@ ifeq ($(CHIP_FAMILY),stm32f0) # STM32F0xx sub-family has a Cortex-M0 ARM core CORE:=cortex-m0 # Force ARMv6-M ISA used by the Cortex-M0 -CFLAGS_CPU+=-march=armv6-m -mcpu=cortex-m0 +# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M +# without "svc" instruction, but that was short-lived. ARMv6S-M was the option +# with "svc". GCC kept that naming scheme even though the distinction is long +# gone. +CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4)) # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core CORE:=cortex-m |